# -------------------------------------------------------------------------------------------------
import sys
import serial
import os
os.environ[
"AMARANTH_ENV_Diamond"] = "/usr/local/diamond/3.11_x64/bin/lin64/diamond_env"
os.environ["AMARANTH_verbose"] = "Yes"
if __name__ == "__main__":
for arg in sys.argv[1:]:
if arg == "run":
FPGA.VersaECP55GPlatform(toolchain="Trellis").build(
SERDESTestbench(TS_TEST), do_program=True)
if arg == "grab":
port = serial.Serial(port='/dev/ttyUSB0', baudrate=1000000)
port.write(b"\x00")
indent = 0
while True:
#while True:
# if port.read(1) == b'\n': break
if port.read(1) == b'\n': break
for x in range(CAPTURE_DEPTH):
if TS_TEST:
# l = Link Number, L = Lane Number, v = Link Valid, V = Lane Valid, t = TS Valid, T = TS ID, n = FTS count, r = TS.rate, c = TS.ctrl, d = lane.det_status, D = lane.det_valid
# DdTcccccrrrrrrrrnnnnnnnnLLLLLtVvllllllll
serdes.lane.rx_align.eq(1),
serdes.lane.tx_symbol.eq(K(28, 3)),
serdes.lane.rx_invert.eq(0),
#aligner.rx_align.eq(1),
serdes.lane.det_enable.eq(0),
]
m.d.sync += platform.request("led", 0).o.eq(~serdes.lane.det_valid)
m.d.sync += platform.request("led", 1).o.eq(~serdes.lane.det_status)
m.d.sync += platform.request("led", 2).o.eq(~serdes.lane.rx_present)
m.d.sync += platform.request("led", 3).o.eq(~serdes.lane.rx_locked)
m.d.sync += platform.request("led", 4).o.eq(~serdes.lane.rx_aligned)
m.d.sync += platform.request("led", 5).o.eq(~(serdes.lane.rx_locked))
m.d.sync += platform.request("led", 6).o.eq(~(serdes.lane.tx_locked))
m.d.sync += platform.request("led", 7).o.eq(~1)
#with m.FSM():
# with m.State("start"):
# m.next = "a"
# with m.State("a"):
# m.d.sync += serdes.lane.det_enable.eq(0)
return m
import os
os.environ["AMARANTH_verbose"] = "Yes"
if __name__ == "__main__":
FPGA.VersaECP55GPlatform().build(Test(), do_program=True)
return m
# -------------------------------------------------------------------------------------------------
import sys
import serial
import os
os.environ["AMARANTH_verbose"] = "Yes"
if __name__ == "__main__":
for arg in sys.argv[1:]:
if arg == "run":
FPGA.VersaECP55GPlatform().build(SERDESTestbench(),
do_program=True)
if arg == "grab":
port = serial.Serial(port='/dev/ttyUSB1', baudrate=1000000)
port.write(b"\x00")
indent = 0
last_time = 0
last_realtime = 0
while True:
#while True:
# if port.read(1) == b'\n': break
if port.read(1) == b'\n': break
# Prints a symbol as K and D codes
def print_symbol(symbol, indent, end=""):
# -------------------------------------------------------------------------------------------------
import sys
import serial
from glob import glob
import os
os.environ["AMARANTH_verbose"] = "Yes"
if __name__ == "__main__":
for arg in sys.argv[1:]:
if arg == "run":
FPGA.VersaECP55GPlatform().build(SERDESTestbench(TS_TEST), do_program=True, nextpnr_opts="-r")
if arg == "grab":
port = serial.Serial(port=glob("/dev/serial/by-id/usb-FTDI_Lattice_ECP5_5G_VERSA_Board_*-if01-port0")[0], baudrate=1000000)
port.write(b"\x00")
indent = 0
last_time = 0
last_realtime = 0
while True:
#while True:
# if port.read(1) == b'\n': break
if port.read(1) == b'\n': break
# Prints a symbol as K and D codes
def print_symbol(symbol, indent, end=""):
return m
# -------------------------------------------------------------------------------------------------
import sys
import serial
import os
os.environ["AMARANTH_verbose"] = "Yes"
if __name__ == "__main__":
for arg in sys.argv[1:]:
if arg == "run":
FPGA.VersaECP55GPlatform().build(
SERDESTestbench(TS_TEST),
do_program=True,
nextpnr_opts="--timing-allow-fail")
if arg == "grab":
port = serial.Serial(port='/dev/ttyUSB0', baudrate=1000000)
port.write(b"\x00")
indent = 0
while True:
#while True:
# if port.read(1) == b'\n': break
if port.read(1) == b'\n': break
for x in range(CAPTURE_DEPTH):
if TS_TEST:
# l = Link Number, L = Lane Number, v = Link Valid, V = Lane Valid, t = TS Valid, T = TS ID, n = FTS count, r = TS.rate, c = TS.ctrl, d = lane.det_status, D = lane.det_valid
with m.State("send-pci-data"):
m.d.sync += uart.tx.data.eq(pci_rport.data)
m.d.sync += uart.tx.ack.eq(uart.tx.rdy)
# When the TX stops being ready, set the next byte. Doesn't work with 'Rose'.
with m.If(Fell(uart.tx.rdy)):
m.d.sync += pci_rport.addr.eq(pci_rport.addr + 1)
# Once all data has been sent, go back to waiting for '>' and strobe init_sent.
with m.If((pci_rport.addr == depth - 1)):
m.next = "uboot-1"
m.d.sync += self.init_sent.eq(1)
uart_pins = platform.request("uart", 0)
#m.d.comb += uart_pins.tx.o.eq(tx_pin.o)
m.d.comb += uart_pins.tx.o.eq(rx_pin.i)
return m
if (__name__ == "__main__"):
# Sends 'pci enum' in a loop
# GND: X4 pin 2 -> RP64 RPi-like header pin 6
# RX : X4 pin 4 -> RP64 RPi-like header pin 8
# TX : X4 pin 6 -> RP64 RPi-like header pin 10
FPGA.VersaECP55GPlatform().build(RP64PCIeInit("A13", "C13", Signal(), 1,
Signal()),
do_program=True,
nextpnr_opts="--timing-allow-fail")
return m
# -------------------------------------------------------------------------------------------------
import sys
import serial
from glob import glob
import os
#os.environ["AMARANTH_verbose"] = "Yes"
if __name__ == "__main__":
for arg in sys.argv[1:]:
if arg == "speed":
plat = FPGA.VersaECP55GPlatform(toolchain="Trellis")
plat.device = "LFE5UM-25F"
plat.speed = 6
plat.build(SERDESTestbench(), do_program=False)
if arg == "run":
print("Building...")
FPGA.VersaECP55GPlatform().build(SERDESTestbench(), do_program=True, nextpnr_opts="-r")
with open("build/top.tim") as logfile:
log = logfile.readlines()
utilisation = []
log_utilisation = False
def elaborate(self, platform: Platform) -> Module:
m = Module()
uart_pins = platform.request("uart", 0)
m.domains.slow = ClockDomain()
uart = serial.AsyncSerial(divisor=int(100 * 1000 * 1000 / 115200),
pins=uart_pins)
pllslow = PLL1Ch(ClockSignal("sync"),
Signal(),
Signal(),
CLKI_DIV=2,
CLKFB_DIV=1,
CLK_DIV=12) # 100 -> 600 -> 50 MHz
m.submodules += [uart, pllslow]
m.d.comb += ClockSignal("slow").eq(pllslow.clkout)
words = 4
data = Signal(words * 8)
m.d.slow += data.eq(data + 1)
debugger = UARTDebugger(uart, words, 100, data, "slow", data[5])
m.submodules += debugger
return m
import os
os.environ["AMARANTH_verbose"] = "Yes"
FPGA.VersaECP55GPlatform().build(UARTDebuggerTest(),
do_program=True,
nextpnr_opts="--timing-allow-fail -r")