def simulate(self, unit=None, id=None, convert_waveform=True, flags=None):
"""
Run simulation on a pc target. 'flags' contains a list of simulator-specific
flags, as a sort of escape hatch for features that are not yet supported
natively through anasymod.
"""
# Remove target-specific build dir to make sure there are no old files.
# However, don't fail when certain files can't be removed, because that
# might indicate that a waveform window is open
shutil.rmtree(self._prj_cfg.build_root, ignore_errors=True)
mkdir_p(self._prj_cfg.build_root)
self._setup_targets(target=self.act_cpu_target, gen_structures=True)
target = getattr(self, self.act_cpu_target)
# create sim result folder
if not os.path.exists(os.path.dirname(target.cfg.vcd_path)):
mkdir_p(os.path.dirname(target.cfg.vcd_path))
if not os.path.exists(os.path.dirname(target.result_path_raw)):
mkdir_p(os.path.dirname(target.result_path_raw))
# pick simulator
sim_cls = {
'icarus': IcarusSimulator,
'vivado': VivadoSimulator,
'xrun': XceliumSimulator
}[self.args.simulator_name]
# run simulation
sim = sim_cls(target=target, flags=flags)
if self.args.simulator_name == "xrun":
sim.unit = unit
sim.id = id
sim.simulate()
statpro.statpro_update(statpro.FEATURES.anasymod_sim +
self.args.simulator_name)
# post-process results
if convert_waveform:
ConvertWaveform(result_path_raw=target.result_path_raw,
result_type_raw=target.cfg.result_type_raw,
result_path=target.cfg.vcd_path,
str_cfg=target.str_cfg,
float_type=self.float_type,
debug=self._prj_cfg.cfg.cpu_debug_mode,
dt_scale=self._prj_cfg.cfg.dt_scale)
def build(self):
"""
Generate bitstream for FPGA target
"""
shutil.rmtree(
self._prj_cfg.build_root
) # Remove target specific build dir to make sure there is no legacy
mkdir_p(self._prj_cfg.build_root)
self._setup_targets(target=self.act_fpga_target, gen_structures=True)
# Check if active target is an FPGA target
target = getattr(self, self.act_fpga_target)
VivadoEmulation(target=target).build()
statpro.statpro_update(statpro.FEATURES.anasymod_build_vivado)
def emulate(self, server_addr=None, convert_waveform=True):
"""
Program bitstream to FPGA and run simulation/emulation on FPGA
:param server_addr: Address of Vivado hardware server used for communication to FPGA board
"""
if server_addr is None:
server_addr = self.args.server_addr
# create target object, but don't generate instrumentation structure again in case target object does not exist yet
if not hasattr(self, self.act_fpga_target):
self._setup_targets(target=self.act_fpga_target)
# check if bitstream was generated for active fpga target
target = getattr(self, self.act_fpga_target)
if not os.path.isfile(getattr(target, 'bitfile_path')):
raise Exception(
f'Bitstream for active FPGA target was not generated beforehand; please do so before running emulation.'
)
# create sim result folders
if not os.path.exists(os.path.dirname(target.cfg.vcd_path)):
mkdir_p(os.path.dirname(target.cfg.vcd_path))
if not os.path.exists(os.path.dirname(target.result_path_raw)):
mkdir_p(os.path.dirname(target.result_path_raw))
# run the emulation
VivadoEmulation(target=target).run_FPGA(
start_time=self.args.start_time,
stop_time=self.args.stop_time,
server_addr=server_addr)
statpro.statpro_update(statpro.FEATURES.anasymod_emulate_vivado)
# post-process results
if convert_waveform:
ConvertWaveform(result_path_raw=target.result_path_raw,
result_type_raw=target.cfg.result_type_raw,
result_path=target.cfg.vcd_path,
str_cfg=target.str_cfg,
float_type=self.float_type,
dt_scale=self._prj_cfg.cfg.dt_scale)
def build(self, *args, **kwargs):
"""
Generate bitstream for FPGA target
"""
shutil.rmtree(
self._prj_cfg.build_root
) # Remove target specific build dir to make sure there is no legacy
mkdir_p(self._prj_cfg.build_root)
self._setup_targets(target=self.act_fpga_target, gen_structures=True)
# Check if active target is an FPGA target
target = getattr(self, self.act_fpga_target)
VivadoEmulation(target=target).build()
# Build firmware for ctrl infrastructure if needed
if target.cfg.fpga_sim_ctrl == FPGASimCtrl.UART_ZYNQ:
self._build_firmware(*args, **kwargs)
statpro.statpro_update(statpro.FEATURES.anasymod_build_vivado)
def launch(self, server_addr=None, debug=False):
"""
Program bitstream to FPGA, setup control infrastructure and wait for interactive commands.
:param server_addr: Address of Vivado hardware server used for communication to FPGA board
:param debug: Enable or disable debug mode when running an interactive simulation
"""
if server_addr is None:
server_addr = self.args.server_addr
# create target object, but don't generate instrumentation structure again in case target object does not exist yet
if not hasattr(self, self.act_fpga_target):
self._setup_targets(target=self.act_fpga_target, debug=debug)
# check if bitstream was generated for active fpga target
target = getattr(self, self.act_fpga_target)
if not os.path.isfile(getattr(target, 'bitfile_path')):
raise Exception(
f'Bitstream for active FPGA target was not generated beforehand; please do so before running emulation.'
)
# create sim result folders
if not os.path.exists(os.path.dirname(target.cfg.vcd_path)):
mkdir_p(os.path.dirname(target.cfg.vcd_path))
if not os.path.exists(os.path.dirname(target.result_path_raw)):
mkdir_p(os.path.dirname(target.result_path_raw))
# launch the emulation
ctrl_handle = VivadoEmulation(target=target).launch_FPGA(
server_addr=server_addr)
statpro.statpro_update(statpro.FEATURES.anasymod_emulate_vivado)
# Return ctrl handle for interactive control
return ctrl_handle
def build(self, *args, **kwargs):
"""
Generate bitstream for FPGA target
"""
shutil.rmtree(
self._prj_cfg.build_root
) # Remove target specific build dir to make sure there is no legacy
mkdir_p(self._prj_cfg.build_root)
self._setup_targets(target=self.act_fpga_target, gen_structures=True)
# Check if active target is an FPGA target
target = getattr(self, self.act_fpga_target)
VivadoEmulation(target=target).build()
# Build firmware for ctrl infrastructure if needed, first
# waiting a short time for outputs from Vivado to sync
# to disk. This seems to be an issue with NFS.
if target.cfg.fpga_sim_ctrl == FPGASimCtrl.UART_ZYNQ:
time.sleep(1)
self._build_firmware(*args, **kwargs)
statpro.statpro_update(statpro.FEATURES.anasymod_build_vivado)
from .files import get_full_path from .util import json2obj, ExampleControl from anasymod.utils import statpro as __statpro __statpro.statpro_update(__statpro.FEATURES.anasymod_import)