def __init__(self,
a: Wire,
b: Wire,
prefix: str = "",
outid: int = 0,
parent_component: object = None):
super().__init__(a, b, prefix, outid, parent_component)
self.gate_type = "and_gate"
self.cgp_function = 2
self.operator = "&"
# Logic gate output wire generation based on input values
# If constant input is present, logic gate is not generated and corresponding
# input value is propagated to the output to connect to other components
if a.is_const() and a.value == 1:
self.out = b
self.disable_generation = True
elif a.is_const() and a.value == 0:
self.out = ConstantWireValue0()
self.disable_generation = True
elif b.is_const() and b.value == 1:
self.out = a
self.disable_generation = True
elif b.is_const() and b.value == 0:
self.out = ConstantWireValue0()
self.disable_generation = True
else:
self.out = Wire(name=prefix)
def __init__(self,
a: Wire = Wire(name="a"),
b: Wire = Wire(name="b"),
prefix: str = "pg_logic"):
super().__init__(a, b, prefix)
# 3 wires for component's bus output (propagate, generate, sum)
self.out = Bus(self.prefix + "_out", 3)
# PG logic
propagate_or = OrGate(a,
b,
prefix=self.prefix + "_or" +
str(self.get_instance_num(cls=OrGate)),
outid=0,
parent_component=self)
self.add_component(propagate_or)
generate_and = AndGate(a,
b,
prefix=self.prefix + "_and" +
str(self.get_instance_num(cls=AndGate)),
outid=1,
parent_component=self)
self.add_component(generate_and)
sum_xor = XorGate(a,
b,
prefix=self.prefix + "_xor" +
str(self.get_instance_num(cls=XorGate)),
outid=2,
parent_component=self)
self.add_component(sum_xor)
self.out.connect(0, propagate_or.out)
self.out.connect(1, generate_and.out)
self.out.connect(2, sum_xor.out)
def __init__(self,
a: Wire = Wire(name="a"),
b: Wire = Wire(name="b"),
prefix: str = "ha"):
super().__init__(a, b, prefix)
# 2 wires for component's bus output (sum, cout)
self.out = Bus(self.prefix + "_out", 2)
# Sum
# XOR gate for calculation of 1-bit sum
obj_xor = XorGate(a,
b,
prefix=self.prefix + "_xor" +
str(self.get_instance_num(cls=XorGate)),
outid=0,
parent_component=self)
self.add_component(obj_xor)
self.out.connect(0, obj_xor.out)
# Cout
# AND gate for calculation of 1-bit cout
obj_and = AndGate(a,
b,
prefix=self.prefix + "_and" +
str(self.get_instance_num(cls=AndGate)),
outid=1,
parent_component=self)
self.add_component(obj_and)
self.out.connect(1, obj_and.out)
def __init__(self,
a: Wire = Wire(name="a"),
b: Wire = Wire(name="b"),
prefix: str = "hs"):
super().__init__(a, b, prefix)
# 2 wires for component's bus output (difference, bout)
self.out = Bus(self.prefix + "_out", 2)
# Difference
# XOR gate for calculation of 1-bit difference
difference_xor = XorGate(a=self.a,
b=self.b,
prefix=self.prefix + "_xor" +
str(self.get_instance_num(cls=XorGate)),
outid=0,
parent_component=self)
self.add_component(difference_xor)
self.out.connect(0, difference_xor.out)
# Bout
# NOT and AND gates for calculation of 1-bit borrow out
not_obj = NotGate(a=self.a,
prefix=self.prefix + "_not" +
str(self.get_instance_num(cls=NotGate)),
parent_component=self)
self.add_component(not_obj)
borrow_and = AndGate(a=not_obj.out,
b=self.b,
prefix=self.prefix + "_xor" +
str(self.get_instance_num(cls=XorGate)),
outid=1,
parent_component=self)
self.add_component(borrow_and)
self.out.connect(1, borrow_and.out)
def __init__(self,
a: Wire = Wire(name="d0"),
b: Wire = Wire(name="d1"),
c: Wire = Wire(name="sel"),
prefix: str = "mux2to1"):
super().__init__(a, b, c, prefix)
# Represents select signal (self.c naming for proper unified generation)
self.c = c
# 1 wire for component's output bus
self.out = Bus(self.prefix + "_out", 1)
# 2:1MUX logic
and_obj = AndGate(a=self.b,
b=self.c,
prefix=self.prefix + "_and" +
str(self.get_instance_num(cls=AndGate)),
parent_component=self)
self.add_component(and_obj)
not_obj = NotGate(a=self.c,
prefix=self.prefix + "_not" +
str(self.get_instance_num(cls=NotGate)),
parent_component=self)
self.add_component(not_obj)
and_obj = AndGate(a=self.a,
b=self.get_previous_component().out,
prefix=self.prefix + "_and" +
str(self.get_instance_num(cls=AndGate)),
parent_component=self)
self.add_component(and_obj)
xor_obj = XorGate(a=self.get_previous_component(3).out,
b=self.get_previous_component().out,
prefix=self.prefix + "_xor" +
str(self.get_instance_num(cls=XorGate)),
parent_component=self)
self.add_component(xor_obj)
# Connection of MUX output wire
self.out.connect(0, xor_obj.out)
def __init__(self,
a: Wire,
b: Wire,
prefix: str = "",
outid: int = 0,
parent_component: object = None):
super().__init__(a, b, prefix, outid, parent_component)
self.gate_type = "xnor_gate"
self.cgp_function = 7
self.operator = "^"
# Logic gate output wire generation based on input values
# If constant input is present, logic gate is not generated and corresponding
# input value is propagated to the output to connect to other components
if a.is_const() and a.value == 1:
self.out = b
self.disable_generation = True
elif a.is_const() and a.value == 0:
output = NotGate(a=b,
prefix=prefix,
outid=outid,
parent_component=parent_component)
self.parent_component.add_component(
output) if parent_component is not None else None
self.out = output.out
self.disable_generation = True
elif b.is_const() and b.value == 1:
self.out = a
self.disable_generation = True
elif b.is_const() and b.value == 0:
output = NotGate(a=a,
prefix=prefix,
outid=outid,
parent_component=parent_component)
self.parent_component.add_component(
output) if parent_component is not None else None
self.out = output.out
self.disable_generation = True
else:
self.out = Wire(name=prefix)
def __init__(self,
a: Wire = Wire(name="a"),
b: Wire = Wire(name="b"),
c: Wire = Wire(name="bin"),
prefix: str = "fs"):
super().__init__(a, b, c, prefix)
# 2 wires for component's bus output (difference, bout)
self.out = Bus(self.prefix + "_out", 2)
# Difference
xor_obj = XorGate(a=self.a,
b=self.b,
prefix=self.prefix + "_xor" +
str(self.get_instance_num(cls=XorGate)),
parent_component=self)
self.add_component(xor_obj)
not_obj = NotGate(a=self.a,
prefix=self.prefix + "_not" +
str(self.get_instance_num(cls=NotGate)),
parent_component=self)
self.add_component(not_obj)
and_obj = AndGate(a=not_obj.out,
b=self.b,
prefix=self.prefix + "_and" +
str(self.get_instance_num(cls=AndGate)),
parent_component=self)
self.add_component(and_obj)
difference_xor = XorGate(a=self.c,
b=xor_obj.out,
prefix=self.prefix + "_xor" +
str(self.get_instance_num(cls=XorGate)),
outid=0,
parent_component=self)
self.add_component(difference_xor)
self.out.connect(0, difference_xor.out)
# Borrow out
not_obj = NotGate(a=xor_obj.out,
prefix=self.prefix + "_not" +
str(self.get_instance_num(cls=NotGate)),
parent_component=self)
self.add_component(not_obj)
and_obj = AndGate(a=not_obj.out,
b=self.c,
prefix=self.prefix + "_and" +
str(self.get_instance_num(cls=AndGate)),
parent_component=self)
self.add_component(and_obj)
borrow_out_or = OrGate(a=and_obj.out,
b=self.get_previous_component(4).out,
prefix=self.prefix + "_or" +
str(self.get_instance_num(cls=OrGate)),
outid=1,
parent_component=self)
self.add_component(borrow_out_or)
self.out.connect(1, borrow_out_or.out)