def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif processor.registers.current_mode_is_user_or_system(): print('unpredictable') elif self.mode == 0b11010: print('unpredictable') else: if not processor.registers.is_secure(): if self.mode == 0b10110 or (self.mode == 0b10001 and processor.registers.nsacr.rfr): print('unpredictable') base = processor.registers.get_rmode(13, self.mode) address = base if self.increment else sub(base, 8, 32) if self.word_higher: address = add(address, 0b100, 32) processor.mem_a_set(address, 4, processor.registers.get_lr()) processor.mem_a_set(add(address, 4, 32), 4, processor.registers.get_spsr()) if self.wback: processor.registers.set_rmode( 13, self.mode, add(base, 8, 32) if self.increment else sub( base, 8, 32))
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif (not processor.registers.current_mode_is_not_user() or processor.registers.current_instr_set() == InstrSet.THUMB_EE): print('unpredictable') else: address = (processor.registers.get(self.n) if self.increment else sub(processor.registers.get(self.n), 8, 32)) if self.word_higher: address = add(address, 4, 32) new_pc_value = processor.mem_a_get(address, 4) spsr_value = processor.mem_a_get(add(address, 4, 32), 4) if self.wback: processor.registers.set( self.n, (add(processor.registers.get(self.n), 8, 32) if self.increment else sub(processor.registers.get(self.n), 8, 32)) ) processor.registers.cpsr_write_by_instr(spsr_value, 0b1111, True) if (processor.registers.cpsr.m == 0b11010 and processor.registers.cpsr.j and processor.registers.cpsr.t): print('unpredictable') else: processor.branch_write_pc(new_pc_value)
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif (not processor.registers.current_mode_is_not_user() or processor.registers.current_instr_set() == InstrSet.InstrSet_ThumbEE): print "unpredictable" else: address = (processor.registers.get(self.n) if self.increment else sub(processor.registers.get(self.n), BitArray(bin="1000"), 32)) if self.word_higher: address = add(address, BitArray(bin="100"), 32) new_pc_value = processor.mem_a_get(address, 4) spsr_value = processor.mem_a_get(add(address, BitArray(bin="100"), 32), 4) if self.wback: processor.registers.set( self.n, (add(processor.registers.get(self.n), BitArray(bin="1000"), 32) if self.increment else sub(processor.registers.get(self.n), BitArray(bin="1000"), 32)) ) processor.registers.cpsr_write_by_instr(spsr_value, BitArray(bin="1111"), True) if (processor.registers.cpsr.get_m() == "0b11010" and processor.registers.cpsr.get_j() and processor.registers.cpsr.get_t()): print "unpredictable" else: processor.branch_write_pc(new_pc_value)
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif (processor.registers.current_mode_is_user_or_system() or processor.registers.current_instr_set() == InstrSet.THUMB_EE): print('unpredictable') else: length = (4 * bit_count(self.registers, 1, 16)) + 4 address = processor.registers.get( self.n) if self.increment else sub( processor.registers.get(self.n), length, 32) if self.word_higher: address = add(address, 4, 32) for i in range(15): if bit_at(self.registers, i): processor.registers.set( i, processor.mem_a_get(address, 4)) address = add(address, 4, 32) new_pc_value = processor.mem_a_get(address, 4) if self.wback and not bit_at(self.registers, self.n): processor.registers.set( self.n, (add(processor.registers.get( self.n), length, 32) if self.increment else sub( processor.registers.get(self.n), length, 32))) if self.wback and bit_at(self.registers, self.n): processor.registers.set(self.n, 0x00000000) # unknown processor.registers.cpsr_write_by_instr( processor.registers.get_spsr(), 0b1111, True) if processor.registers.cpsr.m == 0b11010 and processor.registers.cpsr.j and processor.registers.cpsr.t: print('unpredictable') else: processor.branch_write_pc(new_pc_value)
def execute(self, processor): if processor.condition_passed(): try: processor.null_check_if_thumbee(self.n) except EndOfInstruction: pass else: address = sub(processor.registers.get(self.n), 4 * bit_count(self.registers, 1, 16), 32) for i in range(15): if bit_at(self.registers, i): if i == self.n and self.wback and i != lowest_set_bit_ref( self.registers): processor.mem_a_set(address, 4, 0x00000000) # unknown else: processor.mem_a_set(address, 4, processor.registers.get(i)) address = add(address, 4, 32) if bit_at(self.registers, 15): processor.mem_a_set(address, 4, processor.registers.pc_store_value()) if self.wback: processor.registers.set( self.n, sub(processor.registers.get(self.n), 4 * bit_count(self.registers, 1, 16), 32))
def take_svc_exception(self): self.it_advance() new_lr_value = bits_ops.sub(self.get_pc(), 2, 32) if self.cpsr.t else bits_ops.sub( self.get_pc(), 4, 32) new_spsr_value = self.cpsr.value vect_offset = 8 take_to_hyp = have_virt_ext() and have_security_ext( ) and self.scr.ns and self.cpsr.m == 0b11010 route_to_hyp = (have_virt_ext() and have_security_ext() and not self.is_secure() and self.hcr.tge and self.cpsr.m == 0b10000) preferred_exceptn_return = new_lr_value if take_to_hyp: self.enter_hyp_mode(new_spsr_value, preferred_exceptn_return, vect_offset) elif route_to_hyp: self.enter_hyp_mode(new_spsr_value, preferred_exceptn_return, 20) else: if self.cpsr.m == 0b10110: self.scr.ns = 0 self.cpsr.m = 0b10011 self.set_spsr(new_spsr_value) self.set(14, new_lr_value) self.cpsr.i = 1 self.cpsr.it = 0b00000000 self.cpsr.j = 0 self.cpsr.t = self.sctlr.te self.cpsr.e = self.sctlr.ee self.branch_to( bits_ops.add(self.exc_vector_base(), vect_offset, 32))
def execute(self, processor): if processor.condition_passed(): try: processor.null_check_if_thumbee(13) except EndOfInstruction: pass else: address = sub(processor.registers.get_sp(), 4 * bit_count(self.registers, 1, 32), 32) for i in range(15): if bit_at(self.registers, i): if i == 13 and i != lowest_set_bit_ref(self.registers): processor.mem_a_set(address, 4, 0x00000000) # unknown else: if self.unaligned_allowed: processor.mem_u_set(address, 4, processor.registers.get(i)) else: processor.mem_a_set(address, 4, processor.registers.get(i)) address = add(address, 4, 32) if bit_at(self.registers, 15): if self.unaligned_allowed: processor.mem_u_set( address, 4, processor.registers.pc_store_value()) else: processor.mem_a_set( address, 4, processor.registers.pc_store_value()) processor.registers.set_sp( sub(processor.registers.get_sp(), 4 * bit_count(self.registers, 1, 32), 32))
def execute(self, processor): register_count = bit_count(self.registers, 1, 16) if processor.condition_passed(): address = sub(processor.registers.get(self.n), (4 * register_count), 32) + 4 for i in range(15): if bit_at(self.registers, i): if i == self.n and self.wback and i != lowest_set_bit_ref(self.registers): processor.mem_a_set(address, 4, 0x00000000) # unknown else: processor.mem_a_set(address, 4, processor.registers.get(i)) address = address + 4 if bit_at(self.registers, 15): processor.mem_a_set(address, 4, processor.registers.pc_store_value()) if self.wback: processor.registers.set(self.n, sub(processor.registers.get(self.n), 4 * register_count, 32))
def execute(self, processor): registers_count = bit_count(self.registers, 1, 16) if processor.condition_passed(): address = sub(processor.registers.get(self.n), 4 * registers_count, 32) + 4 for i in range(15): if bit_at(self.registers, i): processor.registers.set(i, processor.mem_a_get(address, 4)) address = add(address, 4, 32) if bit_at(self.registers, 15): processor.load_write_pc(processor.mem_a_get(address, 4)) if self.wback and not bit_at(self.registers, self.n): processor.registers.set( self.n, sub(processor.registers.get(self.n), 4 * registers_count, 32)) if self.wback and bit_at(self.registers, self.n): processor.registers.set(self.n, 0x00000000) # unknown
def execute(self, processor): if processor.condition_passed(): address = sub( processor.registers.get(self.n), BitArray(uint=(4 * self.registers.count(1) - 4), length=32), 32) for i in xrange(15): if self.registers[15 - i]: processor.registers.set(i, processor.mem_a_get(address, 4)) address = add(address, BitArray(bin="100"), 32) if self.registers[0]: processor.load_write_pc(processor.mem_a_get(address, 4)) if self.wback and not self.registers[15 - self.n]: processor.registers.set( self.n, sub( processor.registers.get(self.n), BitArray(uint=(4 * self.registers.count(1)), length=32), 32)) if self.wback and self.registers[15 - self.n]: processor.registers.set(self.n, BitArray(length=32)) # unknown
def take_physical_fiq_exception(self): new_lr_value = self.get_pc() if self.cpsr.t else bits_ops.sub( self.get_pc(), 4, 32) new_spsr_value = self.cpsr.value vect_offset = 28 route_to_monitor = have_security_ext() and self.scr.fiq route_to_hyp = ((have_virt_ext() and have_security_ext() and not self.scr.fiq and self.hcr.fmo and not self.is_secure()) or self.cpsr.m == 0b11010) if route_to_monitor: if self.cpsr.m == 0b10110: self.scr.ns = 0 self.enter_monitor_mode(new_spsr_value, new_lr_value, vect_offset) elif route_to_hyp: self.hsr.value = 0x00000000 # unknown preferred_exceptn_return = bits_ops.sub(new_lr_value, 4, 32) self.enter_hyp_mode(new_spsr_value, preferred_exceptn_return, vect_offset) else: if self.cpsr.m == 0b10110: self.scr.ns = 0 self.cpsr.m = 0b10001 self.set_spsr(new_spsr_value) self.set(14, new_lr_value) self.cpsr.i = 1 if not have_security_ext() or have_virt_ext( ) or not self.scr.ns or self.scr.fw: self.cpsr.f = 1 if not have_security_ext() or have_virt_ext( ) or not self.scr.ns or self.scr.aw: self.cpsr.a = 1 self.cpsr.it = 0b00000000 self.cpsr.j = 0 self.cpsr.t = self.sctlr.te self.cpsr.e = self.sctlr.ee if self.sctlr.ve: self.branch_to(configurations.impdef_fiq_vector) else: self.branch_to( bits_ops.add(self.exc_vector_base(), vect_offset, 32))
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif (processor.registers.current_mode_is_user_or_system() or processor.registers.current_instr_set() == InstrSet.InstrSet_ThumbEE): print "unpredictable" else: length = 4 * self.registers.count(1) + 4 address = processor.registers.get( self.n) if self.increment else sub( processor.registers.get(self.n), BitArray(uint=length, length=32), 32) if self.word_higher: address = add(address, BitArray(bin="100"), 32) for i in xrange(15): if self.registers[15 - i]: processor.registers.set( i, processor.mem_a_get(address, 4)) address = add(address, BitArray(bin="100"), 32) new_pc_value = processor.mem_a_get(address, 4) if self.wback and not self.registers[15 - self.n]: processor.registers.set( self.n, (add(processor.registers.get(self.n), BitArray(uint=length, length=32), 32) if self.increment else sub( processor.registers.get(self.n), BitArray(uint=length, length=32), 32))) if self.wback and self.registers[15 - self.n]: processor.registers.set(self.n, BitArray(length=32)) # unknown processor.registers.cpsr_write_by_instr( processor.registers.get_spsr(), BitArray(bin="1111"), True) if (processor.registers.cpsr.get_m() == "0b11010" and processor.registers.cpsr.get_j() and processor.registers.cpsr.get_t()): print "unpredictable" else: processor.branch_write_pc(new_pc_value)
def execute(self, processor): if processor.condition_passed(): try: processor.null_check_if_thumbee(self.n) except EndOfInstruction: pass else: address = sub(processor.registers.get(self.n), 4 * bit_count(self.registers, 1, 16), 32) for i in range(15): if bit_at(self.registers, i): processor.registers.set( i, processor.mem_a_get(address, 4)) address = add(address, 4, 32) if bit_at(self.registers, 15): processor.load_write_pc(processor.mem_a_get(address, 4)) if self.wback and not bit_at(self.registers, self.n): processor.registers.set( self.n, sub(processor.registers.get(self.n), 4 * bit_count(self.registers, 1, 16), 32)) if self.wback and bit_at(self.registers, self.n): processor.registers.set(self.n, 0x00000000) # unknown
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_instr_set() == InstrSet.ARM: processor.registers.set_lr( sub(processor.registers.get_pc(), 4, 32)) else: processor.registers.set_lr(processor.registers.get_pc() | 0b1) if self.target_instr_set == InstrSet.ARM: target_address = add(align(processor.registers.get_pc(), 4), self.imm32, 32) else: target_address = add(processor.registers.get_pc(), self.imm32, 32) processor.registers.select_instr_set(self.target_instr_set) processor.branch_write_pc(target_address)
def execute(self, processor): if processor.condition_passed(): try: processor.null_check_if_thumbee(13) except EndOfInstruction: pass else: address = sub( processor.registers.get_sp(), BitArray(uint=(4 * self.registers.count(1)), length=32), 32) for i in xrange(15): if self.registers[15 - i]: if i == 13 and i != lowest_set_bit_ref(self.registers): processor.mem_a_set(address, 4, BitArray(length=32)) # unknown else: if self.unaligned_allowed: processor.mem_u_set(address, 4, processor.registers.get(i)) else: processor.mem_a_set(address, 4, processor.registers.get(i)) address = add(address, BitArray(bin="100"), 32) if self.registers[0]: if self.unaligned_allowed: processor.mem_u_set( address, 4, processor.registers.pc_store_value()) else: processor.mem_a_set( address, 4, processor.registers.pc_store_value()) processor.registers.set_sp( sub( processor.registers.get_sp(), BitArray(uint=(4 * self.registers.count(1)), length=32), 32))
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif processor.registers.current_mode_is_user_or_system(): print "unpredictable" else: length = 4 * self.registers.count(1) address = processor.registers.get(self.n) if self.increment else sub( processor.registers.get(self.n), BitArray(uint=length, length=32), 32) if self.word_higher: address = add(address, BitArray(bin="100"), 32) for i in xrange(15): if self.registers[15 - i]: processor.registers.set_rmode(i, BitArray(bin="10000"), processor.mem_a_get(address, 4)) address = add(address, BitArray(bin="100"), 32)
def take_data_abort_exception(self, dabort_exception): new_lr_value = bits_ops.add(self.get_pc(), 4, 32) if self.cpsr.t else self.get_pc() new_spsr_value = self.cpsr.value vect_offset = 16 preferred_exceptn_return = bits_ops.sub(new_lr_value, 8, 32) route_to_monitor = have_security_ext( ) and self.scr.ea and self.is_external_abort() take_to_hyp = have_virt_ext() and have_security_ext( ) and self.scr.ns and self.cpsr.m == 0b11010 route_to_hyp = ( have_virt_ext() and have_security_ext() and not self.is_secure() and (dabort_exception.second_stage_abort() or (self.cpsr.m != 0b11010 and (self.is_external_abort() and self.is_async_abort() and self.hcr.amo) or (self.debug_exception() and self.hdcr.tde)) or (self.cpsr.m == 0b10000 and self.hcr.tge and (dabort_exception.is_alignment_fault() or (self.is_external_abort() and not self.is_async_abort()))))) if route_to_monitor: if self.cpsr.m == 0b10110: self.scr.ns = 0 self.enter_monitor_mode(new_spsr_value, new_lr_value, vect_offset) elif take_to_hyp: self.enter_hyp_mode(new_spsr_value, preferred_exceptn_return, vect_offset) elif route_to_hyp: self.enter_hyp_mode(new_spsr_value, preferred_exceptn_return, 20) else: if have_security_ext() and self.cpsr.m == 0b10110: self.scr.ns = 0 self.cpsr.m = 0b10111 self.set_spsr(new_spsr_value) self.set(14, new_lr_value) self.cpsr.i = 1 if not have_security_ext() or have_virt_ext( ) or not self.scr.ns or self.scr.aw: self.cpsr.a = 1 self.cpsr.it = 0b00000000 self.cpsr.j = 0 self.cpsr.t = self.sctlr.te self.cpsr.e = self.sctlr.ee self.branch_to( bits_ops.add(self.exc_vector_base(), vect_offset, 32))
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): raise UndefinedInstructionException() elif processor.registers.current_mode_is_user_or_system(): print('unpredictable') else: length = 4 * bit_count(self.registers, 1, 16) address = processor.registers.get( self.n) if self.increment else sub( processor.registers.get(self.n), length, 32) if self.word_higher: address = add(address, 4, 32) for i in range(15): if bit_at(self.registers, i): processor.registers.set_rmode( i, 0b10000, processor.mem_a_get(address, 4)) address = add(address, 4, 32)