Exemple #1
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 def testADC_64bit(self):
     logging.debug("------------------------------------------")
     logging.debug("TestDecode:testADC_64bit")
     code = 0xE2910001  # ADDALS R0, R1, #1
     globals.regs[1] = 0xFFFFFFFF
     globals.regs[0] = 0
     globals.regs[globals.CPSR] = 0
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
     code = 0xE2B10001  # ADCALS R0, R1, #1
     globals.regs[1] = 0
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:00000002", reg)
Exemple #2
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 def testEOR(self):
     print "TestDecode:testEOR"
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000000001000000000000000000000, 0)
     logging.debug(instrStr)
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000010001000000000000000000000, 0)
     logging.debug(instrStr)
     # --- test EOR R0, #3
     globals.regs[0] = 3
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:00000003", reg)
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000010001000000000000000011110, 1)
     logging.debug(instrStr)
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:0000001D", reg)
Exemple #3
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    def testADD_ImmShft(self):
        logging.debug("------------------------------------------")
        logging.debug("TestDecode:testADD_ImmShft")
        code = 0xE0856004
        instrStr = armv6instrdecode.getInstructionFromCode(self,  code, 0)
        logging.debug("1:" + instrStr)
        self.assertEqual(instrStr, " E0856004 ADD AL    R06, R05 R04", instrStr)

        globals.regs[4] = 3  # 3 shift <--- 2 = 12
        globals.regs[5] = 1
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
        reg = utils.buildRegValString(self, 6)
        self.assertEqual(reg, "R06:00000009", reg)
Exemple #4
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    def testADC_ImmShft(self):
        logging.debug("------------------------------------------")
        logging.debug("TestDecode:testADC_ImmShft")
        code = 0b11100010101010011010000000001111
        instrStr = armv6instrdecode.getInstructionFromCode(self,  code, 0)
        logging.debug("1:" + instrStr)
        self.assertEqual(instrStr, " E2A9A00F ADC AL    R10, R09 #0F", instrStr)

        globals.regs[9] = 3  # 3 shift <--- 2 = 12
        globals.regs[10] = 1
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
        reg = utils.buildRegValString(self, 10)
        self.assertEqual(reg, "R10:00000013", reg)
Exemple #5
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 def testAND(self):
     print "TestDecode:testAND"
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000000000000000000000000000000, 0)
     logging.debug("1:" + instrStr)
     self.assertEqual(instrStr, " 00000000 AND EQ    R00 R00", instrStr)
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000010000000000000000000000000, 0)
     logging.debug("2:" + instrStr)
     # --- test AND R0, #3
     globals.regs[0] = 3
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:00000003", reg)
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000010000000000000000000011110, 1)
     logging.debug("3:" + instrStr)
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:00000002", reg)
Exemple #6
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 def testADD_Imm1(self):
     logging.debug("------------------------------------------")
     logging.debug("TestDecode:testADD_Imm1")
     code = 0xE2810A01  # ADDAL R0, R1, #4096
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
     logging.debug("1:" + instrStr)
     self.assertEqual(instrStr, " E2810A01 ADD AL    R00, R01 #01", instrStr)
     logging.debug("2:" + instrStr)
     globals.regs[1] = 3  # 3 shift <--- 2 = 12
     globals.regs[0] = 1
     reg = utils.buildRegValString(self, 1)
     self.assertEqual(reg, "R01:00000003", reg)
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:00001003", reg)
Exemple #7
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    def testADC_RegShft(self):
        logging.debug("------------------------------------------")
        logging.debug("TestDecode:testADC_RegShft")
        code = 0b11100000101001100110010000010101
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
        logging.debug("1:" + instrStr)
        self.assertEqual(instrStr, " E0A66415 ADC AL    R06, R05 LSL R04", instrStr)

        globals.regs[4] = 1  
        globals.regs[5] = 0x40000000
        globals.regs[6] = 1
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
        reg = utils.buildRegValString(self, 6)
        self.assertEqual(reg, "R06:80000002", reg)
Exemple #8
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 def testBKPT(self):
     logging.debug("------------------------------------------")
     logging.debug("TestDecode:testBKPT")
     code = 0xE1210070  # BKPT #4096
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
     logging.debug("1:" + instrStr)
     self.assertEqual(instrStr, " E1210070 BKPT AL    BKPT #4096", instrStr)
Exemple #9
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    def testADC_Imm(self):
        logging.debug("------------------------------------------")
        logging.debug("TestDecode:testADC_Imm")
        #   1098 7654 3210 9876 5432 1098 7654 3210
        # 0b1110 0010 1010 0101 0110 0000 0000 0101 - 25=1 4=0 - DP imm
        #---------------------------------------------------------------------------
        code = 0b11100010101001010110000000000101
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
        logging.debug("1:" + instrStr)
        self.assertEqual(instrStr, " E2A56005 ADC AL    R06, R05 #05", instrStr)

        globals.regs[5] = 0x40000000
        globals.regs[6] = 1
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
        reg = utils.buildRegValString(self, 6)
        self.assertEqual(reg, "R06:40000006", reg)
Exemple #10
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 def testADD_Imm2(self):
     logging.debug("------------------------------------------")
     logging.debug("TestDecode:testADD_Imm2")
     #        33222222222211111111110000000000
     #        10987654321098765432109876543210
     code = 0xE289A00F  #2000101
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
     logging.debug("1:" + instrStr)
     # RN:3, RD:1 r1 = r3 +
     # Rd = Rn + shifter_operand + C Flag
     self.assertEqual(instrStr, " E289A00F ADD AL    R10, R09 #0F", instrStr)
     logging.debug("2:" + instrStr)
     globals.regs[9] = 3  # 3 shift <--- 2 = 12
     globals.regs[10] = 1
     reg = utils.buildRegValString(self, 9)
     self.assertEqual(reg, "R09:00000003", reg)
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
     reg = utils.buildRegValString(self, 10)
     self.assertEqual(reg, "R10:00000012", reg)
Exemple #11
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 def testADC_2(self):
     logging.debug("------------------------------------------")
     logging.debug("TestDecode:testADC_2")
     #        33222222222211111111110000000000
     #        10987654321098765432109876543210
     code = 0b11100000101000110011000100000010  #2000101
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
     logging.debug("1:" + instrStr)
     # RN:3, RD:1 r1 = r3 +
     # Rd = Rn + shifter_operand + C Flag
     self.assertEqual(instrStr, " E0A33102 ADC AL    R03, R02 LSL #02", instrStr)
     logging.debug("2:" + instrStr)
     globals.regs[2] = 3  # 3 shift <--- 2 = 12
     globals.regs[3] = 1
     reg = utils.buildRegValString(self, 2)
     self.assertEqual(reg, "R02:00000003", reg)
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
     reg = utils.buildRegValString(self, 3)
     self.assertEqual(reg, "R03:0000000D", reg)
Exemple #12
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 def testGetImm_1(self):
     logging.debug("\n----------------------------------------------------------")
     logging.debug("TestDecode:testGetImm_1")
     # 32 bit imm
     #        33222222222211111111110000000000
     #        10987654321098765432109876543210
     code = 0b00000010000000000000000000000001
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
     logging.debug("testGetImm_1:1:" + instrStr)
     val = armv6instrdecode.getOP2DataProcessing(self, code, 0)
     logging.debug("testGetImm_1:1:" + str(val))
     self.assertEqual(val, 1, val)
     #        33222222222211111111110000000000
     #        10987654321098765432109876543210
     code = 0b00000010000000000000000100000001  #2000101
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
     logging.debug("testGetImm_1:2:" + instrStr)
     val = armv6instrdecode.getOP2DataProcessing(self, code, 0)
     logging.debug("testGetImm_1:2:" + str("%08X"%val))
     self.assertEqual(val, 1073741824, hex(val))
Exemple #13
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    def testGetImm_3_2(self):
        # OP3:  -Rs-0ss1-Rm-  # Bit 25 = 0, 4 = 1 # register shift
        logging.debug("\n----------------------------------------------------------")
        logging.debug("TestDecode:testGetImm_3_2")
        #   1098 7654 3210 9876 5432 1098 7654 3210
        # 0b1110 0000 1010 0101 0101 0110 0011 0100 E0A55634 3456A5E0 ADCAL R5, R4, LSR R6  @ Arithmetic shift right  Rm ASR Rs
        #---------------------------------------------------------------------------
        code = 0b11100000101001010101011000110100  # 
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
        logging.debug("testGetImm_3:2:" + instrStr)
        self.assertEqual(instrStr, " E0A55634 ADC AL    R05, R04 LSR R06", instrStr)

        globals.regs[4] = 2
        globals.regs[6] = 1
        val = armv6instrdecode.getOP2DataProcessing(self, code, 0)
        logging.debug("testGetImm_3:2:" + str(val))
        self.assertEqual(val, 1, val)
Exemple #14
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    def testGetImm_3_1(self):
        # OP3:  -Rs-0ss1-Rm-  # Bit 25 = 0, 4 = 1 # register shift
        logging.debug("\n----------------------------------------------------------")
        logging.debug("TestDecode:testGetImm_3_1")
        #   1098 7654 3210 9876 5432 1098 7654 3210
        # 0b1110 0000 1010 0101 0101 0110 0001 0100 E0A55614 1456A5E0 ADCAL R5, R4, LSL R6  @ Logical shift right     Rm LSR Rs
        #---------------------------------------------------------------------------
        code = 0b11100000101001010101011000010100  # 
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
        logging.debug("testGetImm_3:1:" + instrStr)
        self.assertEqual(instrStr, " E0A55614 ADC AL    R05, R04 LSL R06", instrStr)

        globals.regs[4] = 1 # this reg to get shifted
        globals.regs[6] = 2 # by this value
        val = armv6instrdecode.getOP2DataProcessing(self, code, 0)
        logging.debug("testGetImm_3:1:" + str(val))
        self.assertEqual(val, 4, val)
Exemple #15
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    def testGetImm_2_3(self):
        # OP2:  SftIMss0-Rm-  # Bit 25 = 0, 4 = 0 # immd shift
        # ANDAL R1, R9, R2, OP #1
        logging.debug("\n----------------------------------------------------------")
        logging.debug("TestDecode:testGetImm_2_3")
        #   1098 7654 3210 9876 5432 1098 7654 3210
        # 0b1110 0000 1010 0101 0101 1111 1100 0110 E0A5FAC6 C65FA5E0 ADCAL R5, R6, ASR #31 @ Rotate right            Rm ROR #5bit_Imm
        #---------------------------------------------------------------------------
        code = 0b11100000101001010101111111000110
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
        logging.debug("testGetImm_2:3:" + instrStr)
        self.assertEqual(instrStr, " E0A55FC6 ADC AL    R05, R06 ASR #1F", instrStr)

        globals.regs[6] = ARMCPU.HIGHBIT
        val = armv6instrdecode.getOP2DataProcessing(self, code, 0)
        logging.debug("testGetImm_2:3:" + str(val))
        self.assertEqual(val, 4294967295, val)
Exemple #16
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    def testGetImm_3_4(self):
        # OP3:  -Rs-0ss1-Rm-  # Bit 25 = 0, 4 = 1 # register shift
        logging.debug("\n----------------------------------------------------------")
        logging.debug("TestDecode:testGetImm_3_4")
        #   1098 7654 3210 9876 5432 1098 7654 3210
        # 0b1110 0000 1010 0101 0101 0110 0111 0100 E0A55674 7456A5E0 ADCAL R5, R4, ROR R6  @ Rotate right extended   Rm RRX
        #---------------------------------------------------------------------------
        code = 0b11100000101001010101011001110100  # 
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
        logging.debug("testGetImm_3:4:" + instrStr)
        self.assertEqual(instrStr, " E0A55674 ADC AL    R05, R04 ROR R06", instrStr)

        globals.regs[4] = 1
        globals.regs[6] = 1
        val = armv6instrdecode.getOP2DataProcessing(self, code, 0)
        logging.debug("testGetImm_3:4:" + str(val))
        self.assertEqual(val, 0x80000000, val)
Exemple #17
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    def testGetImm_2_4(self):
        # OP2:  SftIMss0-Rm-  # Bit 25 = 0, 4 = 0 # immd shift
        # ANDAL R1, R9, R2, OP #1
        logging.debug("\n----------------------------------------------------------")
        logging.debug("TestDecode:testGetImm_2_4")
        #   1098 7654 3210 9876 5432 1098 7654 3210
        # 0b1110 0000 1010 0101 0101 1111 1110 0110 E0A55FE6 E65FA5E0 ADCAL R5, R6, ROR #31 @ Register                Rm
        #---------------------------------------------------------------------------
        code = 0b11100000101001010101111111100110
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
        logging.debug("testGetImm_2:4:" + instrStr)
        self.assertEqual(instrStr, " E0A55FE6 ADC AL    R05, R06 ROR #1F", instrStr)

        globals.regs[6] = 1
        val = armv6instrdecode.getOP2DataProcessing(self, code, 0)
        logging.debug("testGetImm_2:4:" + str(val))
        self.assertEqual(val, 2, val)
Exemple #18
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    def testGetImm_2_2(self):
        # OP2:  SftIMss0-Rm-  # Bit 25 = 0, 4 = 0 # immd shift
        # ANDAL R1, R9, R2, OP #1
        logging.debug("\n----------------------------------------------------------")
        logging.debug("TestDecode:testGetImm_2_2")
        #   1098 7654 3210 9876 5432 1098 7654 3210
        # 0b1110 0000 1010 0101 0101 1111 1010 0110 E0A5FAA6 A65FA5E0 ADCAL R5, R6, LSR #31 @ Arithmetic shift right  Rm ASR #5bit_Imm
        #---------------------------------------------------------------------------
        code = 0b11100000101001010101111110100110
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
        logging.debug("testGetImm_2:2:" + instrStr)
        self.assertEqual(instrStr, " E0A55FA6 ADC AL    R05, R06 LSR #1F", instrStr)

        globals.regs[6] = 2147483648
        val = armv6instrdecode.getOP2DataProcessing(self, code, 0)
        logging.debug("testGetImm_2:2:" + str(val))
        self.assertEqual(val, 1, val)
Exemple #19
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 def testADD_setflag_o(self):
     logging.debug("------------------------------------------")
     logging.debug("TestDecode:testADD_setflag_o - should produce an overflow")
     code = 0xE2910001  # ADDALS R0, R1, #1
     globals.regs[1] = 0x7FFFFFFF
     globals.regs[0] = 0
     globals.regs[globals.CPSR] = 0
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 1)
     reg = utils.buildRegValString(self, 0)
     self.assertEqual(reg, "R00:80000000", reg)
     # N Flag = Rd[31]
     self.assertEqual(1, globals.regs[globals.CPSR] & ARMCPU.NEGATIVEBIT > 0, 1)
     # Z Flag = if Rd == 0 then 1 else 0
     self.assertEqual(1, globals.regs[globals.CPSR] & ARMCPU.ZEROBIT == 0, 1)
     # C Flag = CarryFrom(Rn + shifter_operand)
     # V Flag = OverflowFrom(Rn + shifter_operand)
     #logging.debug(hex(globals.regs[globals.CPSR] & ARMCPU.OVERBIT))
     self.assertEqual(1, globals.regs[globals.CPSR] & ARMCPU.OVERBIT > 0, 1)
Exemple #20
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    def testGetImm_2_5(self):
        # OP2:  SftIMss0-Rm-  # Bit 25 = 0, 4 = 0 # immd shift
        # ANDAL R1, R9, R2, OP #1
        logging.debug("\n----------------------------------------------------------")
        logging.debug("TestDecode:testGetImm_2_5")
        #   1098 7654 3210 9876 5432 1098 7654 3210
        # 0b1110 0000 1010 0101 0101 0000 0000 0110 E0A55006 0650A5E0 ADCAL R5, R6          @ Logical shift left      Rm LSL Rs
        #---------------------------------------------------------------------------
        code = 0b11100000101001010101000000000110
        instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
        logging.debug("testGetImm_2:5:" + instrStr)
        self.assertEqual(instrStr, " E0A55006 ADC AL    R05, R06", instrStr)

        globals.regs[5] = 1
        globals.regs[6] = 1
        val = armv6instrdecode.getOP2DataProcessing(self, code, 0)
        logging.debug("testGetImm_2:5:" + str(val))
        self.assertEqual(val, 2, val)
Exemple #21
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 def testGetImm_3_5(self):
     # OP3:  -Rs-0ss1-Rm-  # Bit 25 = 0, 4 = 1 # register shift
     logging.debug("\n----------------------------------------------------------")
     logging.debug("TestDecode:testGetImm_3_5")
     #   1098 7654 3210 9876 5432 1098 7654 3210
     # 0b1110 0000 1010 0101 0101 0000 0110 0110 E0A55066 6650A5E0 ADCAL R5, R6, RRX
     #---------------------------------------------------------------------------
     code = 0b11100000101001010101000001100110  # 
     instrStr = armv6instrdecode.getInstructionFromCode(self, code, 0)
     logging.debug("testGetImm_3:5:" + instrStr)
     self.assertEqual(instrStr, " E0A55066 ADC AL    R05, R06 RRX", instrStr)
     
     logging.debug("\n----------------------------------------------------------")
     # carry set - be bit 32
     globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
     globals.regs[6] = 0  # ROR carry in
     val = armv6instrdecode.getOP2DataProcessing(self, code, 0)
     logging.debug("testGetImm_3:5a:" + str(val))
     self.assertEqual(val, 0x80000000, val)
     cbit = (globals.regs[globals.CPSR] & ARMCPU.CARRYBIT) == 0 # shift out is 0 -false
     self.assertEqual(cbit, 0, cbit)
             
     logging.debug("\n----------------------------------------------------------")
     # carry clear
     globals.regs[globals.CPSR] = 0
     globals.regs[6] = 0x80000000 # ROR clear carry
     val = armv6instrdecode.getOP2DataProcessing(self, code, 0)
     logging.debug("testGetImm_3:5b:" + str(val))
     self.assertEqual(val, 0x40000000, val)
     
     logging.debug("\n----------------------------------------------------------")
     # carry out
     globals.regs[globals.CPSR] = 0
     globals.regs[6] = 1 # ROR clear set
     val = armv6instrdecode.getOP2DataProcessing(self, code, 0)
     logging.debug("testGetImm_3:5c:" + str(val))
     cbit = (globals.regs[globals.CPSR] & ARMCPU.CARRYBIT) > 0 # shift out is 0 -false
     self.assertEqual(cbit, 1, cbit)
Exemple #22
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 def testANDShift(self):
     print "TestDecode:testAND"
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b11100010000000010000110000000001, 0)
     logging.debug("1:" + instrStr)
Exemple #23
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 def testBL(self):
     print "TestDecode:testBL"
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0x0A000000, 0)
     logging.debug(instrStr)
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0x0B000000, 0)
     logging.debug(instrStr)
Exemple #24
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 def testRSC(self):
     print "TestDecode:testRSC"
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000000111000000000000000000000, 0)
     logging.debug(instrStr)
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000010111000000000000000000000, 0)
     logging.debug(instrStr)
Exemple #25
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 def testADC_1(self):
     logging.debug("------------------------------------------")
     logging.debug("TestDecode:testADC_1")
     instrStr = armv6instrdecode.getInstructionFromCode(self, 0b11100000101000110011000010000010, 0)
     logging.debug("1:" + instrStr)
     self.assertEqual(instrStr, " E0A33082 ADC AL    R03, R02 LSL #01", instrStr)
Exemple #26
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    def testCondExec(self):
        """ basic test:
            set cond code
            setup reg with value
            setup mov imm with value2
            exec mov
            check reg for """
        # 0000 	EQ 	Equal / equals zero 	             Z
        logging.debug("0000 	EQ 	Equal / equals zero 	             Z")
        logging.debug("--- Bit set, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.ZEROBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00000011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)

        # 0001 	NE 	Not equal 	                     !Z
        logging.debug("0001 	NE 	Not equal 	                     !Z")
        logging.debug("--- Bit clear, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00010011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.ZEROBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00010011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 0010 	CS / HS Carry set / unsigned higher or same  C
        logging.debug("0010 	CS / HS Carry set / unsigned higher or same  C")
        logging.debug("--- Bit set, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00100011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00100011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 0011 	CC / LO Carry clear / unsigned lower 	     !C
        logging.debug("0011 	CC / LO Carry clear / unsigned lower 	     !C")
        logging.debug("--- Bit clear, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00110011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b00110011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 0100 	MI 	Minus / negative 	             N
        logging.debug("0100 	MI 	Minus / negative 	             N")
        logging.debug("--- Bit set, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.NEGATIVEBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01000011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01000011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 0101 	PL 	Plus / positive or zero 	     !N
        logging.debug("0101 	PL 	Plus / positive or zero 	     !N")
        logging.debug("--- Bit clear, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01010011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.NEGATIVEBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01010011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 0110 	VS 	Overflow 	                     V
        logging.debug("0110 	VS 	Overflow 	                     V")
        logging.debug("--- Bit set, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.OVERBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01100011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01100011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 0111 	VC 	No overflow 	                     !V
        logging.debug("0111 	VC 	No overflow 	                     !V")
        logging.debug("--- Bit clear, exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01110011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit not set, skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.OVERBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b01110011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 1000 	HI 	Unsigned higher 	             C and !Z
        logging.debug("1000 	HI 	Unsigned higher 	             C and !Z")
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10000011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit , skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.ZEROBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10000011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 1001 	LS 	Unsigned lower or same 	             !C or Z
        logging.debug("1001 	LS 	Unsigned lower or same 	             !C or Z")
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.ZEROBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10010011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit , skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.CARRYBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10010011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 1010 	GE 	Signed greater than or equal 	     N == V
        logging.debug("1010 	GE 	Signed greater than or equal 	     N == V")
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.NEGATIVEBIT | ARMCPU.OVERBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10100011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10100011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)

        logging.debug("--- Bit , skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.NEGATIVEBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10100011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 1011 	LT 	Signed less than 	             N != V
        logging.debug("1011 	LT 	Signed less than 	             N != V")
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.NEGATIVEBIT | ARMCPU.OVERBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10100011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10100011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)

        logging.debug("--- Bit , skip exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.NEGATIVEBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b10100011101000000000000011111110, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:00000000", reg)
        
        # 1100 	GT 	Signed greater than 	             !Z and (N == V)
        logging.debug("1100 	GT 	Signed greater than 	             !Z and (N == V)")
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = 0
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b11000011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)
        
        # 1101 	LE 	Signed less than or equal 	     Z or (N != V)
        logging.debug("1101 	LE 	Signed less than or equal 	     Z or (N != V)")
        logging.debug("--- Bit , exec")
        globals.regs[0] = 0
        globals.regs[globals.CPSR] = globals.regs[globals.CPSR] | ARMCPU.ZEROBIT
        instrStr = armv6instrdecode.getInstructionFromCode(self, 0b11010011101000000000000011111111, 1)
        logging.debug(instrStr)
        reg = utils.buildRegValString(self, 0)
        self.assertEqual(reg, "R00:000000FF", reg)