def __init__(self, with_sawg, **kwargs): SatelliteBase.__init__( self, 150e6, identifier_suffix=".without-sawg" if not with_sawg else "", **kwargs) platform = self.platform self.submodules += RTMUARTForward(platform) # RTM bitstream upload slave_fpga_cfg = self.platform.request("rtm_fpga_cfg") self.submodules.slave_fpga_cfg = gpio.GPIOTristate([ slave_fpga_cfg.cclk, slave_fpga_cfg.din, slave_fpga_cfg.done, slave_fpga_cfg.init_b, slave_fpga_cfg.program_b, ]) self.csr_devices.append("slave_fpga_cfg") self.config["SLAVE_FPGA_GATEWARE"] = 0x200000 rtio_channels = [] for i in range(4): phy = ttl_simple.Output(platform.request("user_led", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) mcx_io = platform.request("mcx_io", 0) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) self.comb += mcx_io.direction.eq(phy.oe) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) mcx_io = platform.request("mcx_io", 1) phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level) self.comb += mcx_io.direction.eq(phy.oe) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.submodules.jesd_crg = jesd204_tools.UltrascaleCRG( platform, use_rtio_clock=True) if with_sawg: cls = JDCG else: cls = JDCGNoSAWG self.submodules.jdcg_0 = cls(platform, self.crg, self.jesd_crg, 0) self.submodules.jdcg_1 = cls(platform, self.crg, self.jesd_crg, 1) self.csr_devices.append("jesd_crg") self.csr_devices.append("jdcg_0") self.csr_devices.append("jdcg_1") self.config["HAS_JDCG"] = None self.add_csr_group("jdcg", ["jdcg_0", "jdcg_1"]) self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels) rtio_channels.extend( rtio.Channel.from_phy(phy) for sawg in self.jdcg_0.sawgs + self.jdcg_1.sawgs for phy in sawg.phys) self.add_rtio(rtio_channels) self.submodules.sysref_sampler = jesd204_tools.SysrefSampler( platform.request("amc_fpga_sysref", 0), self.rtio_tsc.coarse_ts) self.csr_devices.append("sysref_sampler") self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref) self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref) # DDMTD # https://github.com/sinara-hw/Sayma_RTM/issues/68 sysref_pads = platform.request("amc_fpga_sysref", 1) self.submodules.sysref_ddmtd = jesd204_tools.DDMTD( sysref_pads, self.rtio_clk_freq) self.csr_devices.append("sysref_ddmtd")
def __init__(self, **kwargs): _SatelliteBase.__init__(self, **kwargs) platform = self.platform rtio_channels = [] for bm in range(2): print("BaseMod{} RF switches starting at RTIO channel 0x{:06x}" .format(bm, len(rtio_channels))) for i in range(4): phy = ttl_serdes_7series.Output_8X(platform.request("basemod{}_rfsw".format(bm), i), invert=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) print("BaseMod{} attenuator starting at RTIO channel 0x{:06x}" .format(bm, len(rtio_channels))) basemod_att = platform.request("basemod{}_att".format(bm)) for name in "rst_n clk le".split(): signal = getattr(basemod_att, name) for i in range(len(signal)): phy = ttl_simple.Output(signal[i]) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.Output(basemod_att.mosi[0]) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(3): self.comb += basemod_att.mosi[i+1].eq(basemod_att.miso[i]) phy = ttl_simple.InOut(basemod_att.miso[3]) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_rtio(rtio_channels) self.comb += platform.request("clk_src_ext_sel").eq(0) # HMC clock chip and DAC control self.comb += [ platform.request("ad9154_rst_n", 0).eq(1), platform.request("ad9154_rst_n", 1).eq(1) ] self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface( platform.request("hmc_spi"), platform.request("ad9154_spi", 0), platform.request("ad9154_spi", 1))) self.csr_devices.append("converter_spi") self.submodules.hmc7043_reset = gpio.GPIOOut( platform.request("hmc7043_reset"), reset_out=1) self.csr_devices.append("hmc7043_reset") self.submodules.hmc7043_gpo = gpio.GPIOIn( platform.request("hmc7043_gpo")) self.csr_devices.append("hmc7043_gpo") self.config["HAS_HMC830_7043"] = None self.config["HAS_AD9154"] = None self.config["AD9154_COUNT"] = 2 self.config["CONVERTER_SPI_HMC830_CS"] = 0 self.config["CONVERTER_SPI_HMC7043_CS"] = 1 self.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2 self.config["HMC830_REF"] = str(int(self.rtio_clk_freq/1e6)) # HMC workarounds self.comb += platform.request("hmc830_pwr_en").eq(1) self.submodules.hmc7043_out_en = gpio.GPIOOut( platform.request("hmc7043_out_en")) self.csr_devices.append("hmc7043_out_en") # DDMTD sysref_pads = platform.request("rtm_fpga_sysref", 0) self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(sysref_pads, self.rtio_clk_freq) self.csr_devices.append("sysref_ddmtd") platform.add_false_path_constraints( self.sysref_ddmtd.cd_helper.clk, self.drtio_transceiver.gtps[0].txoutclk) platform.add_false_path_constraints( self.sysref_ddmtd.cd_helper.clk, self.crg.cd_sys.clk)
def __init__(self, platform): csr_devices = [] self.submodules.crg = CRG(platform) clk_freq = 125e6 self.submodules.rtm_magic = RTMMagic() csr_devices.append("rtm_magic") self.submodules.rtm_identifier = identifier.Identifier(artiq_version) csr_devices.append("rtm_identifier") self.submodules.rtm_scratch = RTMScratch() csr_devices.append("rtm_scratch") # clock mux: 100MHz ext SMA clock to HMC830 input self.submodules.clock_mux = gpio.GPIOOut(Cat( platform.request("clk_src_ext_sel"), platform.request("ref_clk_src_sel"), platform.request("dac_clk_src_sel"), platform.request("ref_lo_clk_sel")), reset_out=0b0111) csr_devices.append("clock_mux") # Allaki: enable RF output, GPIO access to attenuator self.comb += [ platform.request("allaki0_rfsw0").eq(1), platform.request("allaki0_rfsw1").eq(1), platform.request("allaki1_rfsw0").eq(1), platform.request("allaki1_rfsw1").eq(1), platform.request("allaki2_rfsw0").eq(1), platform.request("allaki2_rfsw1").eq(1), platform.request("allaki3_rfsw0").eq(1), platform.request("allaki3_rfsw1").eq(1), ] allaki_atts = [ platform.request("allaki0_att0"), platform.request("allaki0_att1"), platform.request("allaki1_att0"), platform.request("allaki1_att1"), platform.request("allaki2_att0"), platform.request("allaki2_att1"), platform.request("allaki3_att0"), platform.request("allaki3_att1"), ] allaki_att_gpio = [] for allaki_att in allaki_atts: allaki_att_gpio += [ allaki_att.le, allaki_att.sin, allaki_att.clk, allaki_att.rst_n, ] self.submodules.allaki_atts = gpio.GPIOOut(Cat(*allaki_att_gpio)) csr_devices.append("allaki_atts") # HMC clock chip and DAC control self.comb += platform.request("ad9154_rst_n").eq(1) self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface( platform.request("hmc_spi"), platform.request("ad9154_spi", 0), platform.request("ad9154_spi", 1))) csr_devices.append("converter_spi") self.submodules.hmc7043_reset = gpio.GPIOOut( platform.request("hmc7043_reset"), reset_out=1) csr_devices.append("hmc7043_reset") self.submodules.hmc7043_gpo = gpio.GPIOIn( platform.request("hmc7043_gpo")) csr_devices.append("hmc7043_gpo") # DDMTD self.clock_domains.cd_rtio = ClockDomain(reset_less=True) rtio_clock_pads = platform.request("si5324_clkout_fabric") self.specials += Instance("IBUFGDS", i_I=rtio_clock_pads.p, i_IB=rtio_clock_pads.n, o_O=self.cd_rtio.clk) self.submodules.sysref_ddmtd = jesd204_tools.DDMTD( platform.request("rtm_master_aux_clk"), 150e6) csr_devices.append("sysref_ddmtd") # AMC/RTM serwb serwb_pads = platform.request("amc_rtm_serwb") platform.add_period_constraint(serwb_pads.clk, 8.) serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave") self.submodules.serwb_phy_rtm = serwb_phy_rtm self.comb += [ self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk), self.crg.serwb_reset.eq(serwb_phy_rtm.serdes.reset) ] csr_devices.append("serwb_phy_rtm") serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master") self.submodules += serwb_core # process CSR devices and connect them to serwb self.csr_regions = [] wb_slaves = WishboneSlaveManager(0x10000000) for i, name in enumerate(csr_devices): origin = i*CSR_RANGE_SIZE module = getattr(self, name) csrs = module.get_csrs() bank = wishbone.CSRBank(csrs) self.submodules += bank wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus) self.csr_regions.append((name, origin, 32, csrs)) self.submodules += wishbone.Decoder(serwb_core.etherbone.wishbone.bus, wb_slaves.get_interconnect_slaves(), register=True)