def __init__(self, ws):
sequence = [b for write in test_writes for b in encode_record(*write)]
sequence.append(0)
sequence = pack(sequence, ws)
bus = wishbone.Interface(ws * 8)
self.submodules.memory = wishbone.SRAM(1024, init=sequence, bus=bus)
self.submodules.dut = dma.DMA(bus)
def __init__(self, ws):
sequence1 = encode_sequence(test_writes1, ws)
sequence2 = encode_sequence(test_writes2, ws)
offset = 512 // ws
assert len(sequence1) < offset
sequence = (sequence1 + [
prng.randrange(2**(ws * 8)) for _ in range(offset - len(sequence1))
] + sequence2)
bus = wishbone.Interface(ws * 8)
self.submodules.memory = wishbone.SRAM(1024, init=sequence, bus=bus)
self.submodules.dut = dma.DMA(bus)
def __init__(self, ws):
self.ttl0 = Signal()
self.ttl1 = Signal()
self.submodules.phy0 = ttl_simple.Output(self.ttl0)
self.submodules.phy1 = ttl_simple.Output(self.ttl1)
rtio_channels = [
rtio.Channel.from_phy(self.phy0),
rtio.Channel.from_phy(self.phy1)
]
sequence = encode_sequence(test_writes_full_stack, ws)
bus = wishbone.Interface(ws * 8)
self.submodules.memory = wishbone.SRAM(256, init=sequence, bus=bus)
self.submodules.dut = dma.DMA(bus)
self.submodules.rtio = rtio.Core(rtio_channels)
self.comb += self.dut.cri.connect(self.rtio.cri)
