def add_std(cls, target, eem, eem_aux=None, ttl_out_cls=None): cls.add_extension(target, eem, eem_aux) phy = grabber.Grabber( target.platform.request("grabber{}_video".format(eem))) name = "grabber{}".format(len(target.grabber_csr_group)) setattr(target.submodules, name, phy) target.grabber_csr_group.append(name) target.csr_devices.append(name) target.rtio_channels += [ rtio.Channel(phy.config), rtio.Channel(phy.gate_data) ] if ttl_out_cls is not None: for signal in "cc0 cc1 cc2".split(): pads = target.platform.request("grabber{}_{}".format( eem, signal)) phy = ttl_out_cls(pads.p, pads.n) target.submodules += phy target.rtio_channels.append(rtio.Channel.from_phy(phy)) if eem_aux is not None: pads = target.platform.request("grabber{}_cc3".format(eem)) phy = ttl_out_cls(pads.p, pads.n) target.submodules += phy target.rtio_channels.append(rtio.Channel.from_phy(phy))
def add_std(cls, target, eem, eem_aux=None, ttl_out_cls=None, iostandard="LVDS_25"): cls.add_extension(target, eem, eem_aux, iostandard=iostandard) pads = target.platform.request("grabber{}_video".format(eem)) target.platform.add_period_constraint(pads.clk_p, 14.71) phy = grabber.Grabber(pads) name = "grabber{}".format(len(target.grabber_csr_group)) setattr(target.submodules, name, phy) target.platform.add_false_path_constraints( target.crg.cd_sys.clk, phy.deserializer.cd_cl.clk) # Avoid bogus s/h violations at the clock input being sampled # by the ISERDES. This uses dynamic calibration. target.platform.add_false_path_constraints( pads.clk_p, phy.deserializer.cd_cl7x.clk) target.grabber_csr_group.append(name) target.csr_devices.append(name) target.rtio_channels += [ rtio.Channel(phy.config), rtio.Channel(phy.gate_data) ] if ttl_out_cls is not None: for signal in "cc0 cc1 cc2".split(): pads = target.platform.request("grabber{}_{}".format(eem, signal)) phy = ttl_out_cls(pads.p, pads.n) target.submodules += phy target.rtio_channels.append(rtio.Channel.from_phy(phy)) if eem_aux is not None: pads = target.platform.request("grabber{}_cc3".format(eem)) phy = ttl_out_cls(pads.p, pads.n) target.submodules += phy target.rtio_channels.append(rtio.Channel.from_phy(phy))
def __init__(self, clock_pads, tx_pads, sys_clk_freq, **kwargs): self.clock_domains.cd_rtio = ClockDomain() self.rtio_channels = [] # # # gtx = GTXTransmitter(clock_pads=clock_pads, tx_pads=tx_pads, sys_clk_freq=sys_clk_freq) self.submodules += gtx self.comb += [ self.cd_rtio.clk.eq(ClockSignal("tx")), self.cd_rtio.rst.eq(ResetSignal("tx")), ] ttl_values = Signal(32) frame_counter = Signal(max=3) self.sync.tx += [ If( frame_counter == 0, gtx.encoder.k[0].eq(1), gtx.encoder.d[0].eq((5 << 5) | 28), gtx.encoder.k[1].eq(0), gtx.encoder.d[1].eq(0), frame_counter.eq(1), ).Elif(frame_counter == 1, gtx.encoder.k[0].eq(0), gtx.encoder.d[0].eq(ttl_values[0:8]), gtx.encoder.k[1].eq(0), gtx.encoder.d[1].eq(ttl_values[8:16]), frame_counter.eq(2)).Else( gtx.encoder.k[0].eq(0), gtx.encoder.d[0].eq(ttl_values[16:24]), gtx.encoder.k[1].eq(0), gtx.encoder.d[1].eq(ttl_values[24:32]), frame_counter.eq(0)) ] for i in range(32): value = ttl_values[i] rtlink = rtio.rtlink.Interface(rtio.rtlink.OInterface(1)) probes = [value] override_en = Signal() override_o = Signal() overrides = [override_en, override_o] channel = rtio.Channel(rtlink, probes, overrides, **kwargs) self.rtio_channels.append(channel) value_k = Signal() self.sync.rio_phy += [ If(rtlink.o.stb, value_k.eq(rtlink.o.data)), If(override_en, value.eq(override_o)).Else(value.eq(value_k)) ]