def __init__(self,
dev = '/dev/datadev_0',
**kwargs):
super().__init__(
dev = dev,
pollEn = False,
initRead = False,
**kwargs)
self.memMap = axipcie.createAxiPcieMemMap(dev, 'localhost', 8000)
self.memMap.setName('PCIe_Bar0')
self.add(_Device(name = 'DevPcie',
memBase = self.memMap))
def __init__(
self,
dataDebug=False,
dev='/dev/datadev_0', # path to PCIe device
enLclsI=True,
enLclsII=False,
startupMode=False, # False = LCLS-I timing mode, True = LCLS-II timing mode
standAloneMode=False, # False = using fiber timing, True = locally generated timing
pgp3=False, # true = PGPv3, false = PGP2b
pollEn=True, # Enable automatic polling registers
initRead=True, # Read all registers at start of the system
numLanes=4, # Number of PGP lanes
camType=None,
defaultFile=None,
enableDump=False,
clDevTarget=clDev.ClinkDevKcu1500,
**kwargs):
# Set the firmware Version lock = firmware/targets/shared_version.mk
self.FwVersionLock = 0x04090000
# Set number of lanes to min. requirement
if numLanes > len(camType):
laneSize = len(camType)
else:
laneSize = numLanes
# Set local variables
self.camType = [camType[i] for i in range(laneSize)]
self.defaultFile = defaultFile
self.dev = dev
self.startupMode = startupMode
self.standAloneMode = standAloneMode
self.enableDump = enableDump
# Check for simulation
if dev == 'sim':
kwargs['timeout'] = 100000000 # 100 s
else:
kwargs['timeout'] = 5000000 # 5 s
# Pass custom value to parent via super function
super().__init__(dev=dev,
pgp3=pgp3,
pollEn=pollEn,
initRead=initRead,
numLanes=laneSize,
**kwargs)
# Unhide the RemoteVariableDump command
self.RemoteVariableDump.hidden = False
# Create memory interface
self.memMap = axipcie.createAxiPcieMemMap(dev, 'localhost', 8000)
self.memMap.setName('PCIe_Bar0')
# Instantiate the top level Device and pass it the memory map
self.add(
clDevTarget(
name='ClinkPcie',
memBase=self.memMap,
numLanes=laneSize,
pgp3=pgp3,
enLclsI=enLclsI,
enLclsII=enLclsII,
expand=True,
))
# CLink SRP, CLink serial
destList = [0, 2]
# Create DMA streams
self.dmaStreams = axipcie.createAxiPcieDmaStreams(
dev,
{lane: {dest
for dest in destList}
for lane in range(laneSize)}, 'localhost', 8000)
# Check if not doing simulation
if (dev != 'sim'):
# Create arrays to be filled
self._srp = [None for lane in range(laneSize)]
# Create the stream interface
for lane in range(laneSize):
# SRP
self._srp[lane] = rogue.protocols.srp.SrpV3()
self._srp[lane].setName(f'SRPv3[{lane}]')
pr.streamConnectBiDir(self.dmaStreams[lane][0],
self._srp[lane])
# CameraLink Feb Board
self.add(
feb.ClinkFeb(
name=(f'ClinkFeb[{lane}]'),
memBase=self._srp[lane],
serial=self.dmaStreams[lane][2],
camType=self.camType[lane],
version3=pgp3,
enableDeps=[
self.ClinkPcie.Hsio.PgpMon[lane].RxRemLinkReady
], # Only allow access if the PGP link is established
expand=True,
))
# Else doing Rogue VCS simulation
else:
self.roguePgp = shared.RogueStreams(numLanes=laneSize, pgp3=pgp3)
# Create arrays to be filled
self._frameGen = [None for lane in range(laneSize)]
# Create the stream interface
for lane in range(laneSize):
# Create the frame generator
self._frameGen[lane] = MyCustomMaster()
# Connect the frame generator
print(self.roguePgp.pgpStreams)
self._frameGen[lane] >> self.roguePgp.pgpStreams[lane][1]
# Create a command to execute the frame generator
self.add(
pr.BaseCommand(
name=f'GenFrame[{lane}]',
function=lambda cmd, lane=lane: self._frameGen[lane].
myFrameGen(),
))
# Create a command to execute the frame generator. Accepts user data argument
self.add(
pr.BaseCommand(
name=f'GenUserFrame[{lane}]',
function=lambda cmd, lane=lane: self._frameGen[lane].
myFrameGen,
))
# Create arrays to be filled
self._dbg = [None for lane in range(laneSize)]
self.unbatchers = [
rogue.protocols.batcher.SplitterV1() for lane in range(laneSize)
]
# Create the stream interface
for lane in range(laneSize):
# Debug slave
if dataDebug:
# Connect the streams
self.dmaStreams[lane][1] >> self.unbatchers[lane] >> self._dbg[
lane]
self.add(
pr.LocalVariable(
name='RunState',
description=
'Run state status, which is controlled by the StopRun() and StartRun() commands',
mode='RO',
value=False,
))
@self.command(
description='Stops the triggers and blows off data in the pipeline'
)
def StopRun():
print('ClinkDev.StopRun() executed')
# Get devices
eventBuilder = self.find(typ=batcher.AxiStreamBatcherEventBuilder)
trigger = self.find(typ=l2si.TriggerEventBuffer)
# Turn off the triggering
for devPtr in trigger:
devPtr.MasterEnable.set(False)
# Flush the downstream data/trigger pipelines
for devPtr in eventBuilder:
devPtr.Blowoff.set(True)
# Update the run state status variable
self.RunState.set(False)
@self.command(
description=
'starts the triggers and allow steams to flow to DMA engine')
def StartRun():
print('ClinkDev.StartRun() executed')
# Get devices
eventBuilder = self.find(typ=batcher.AxiStreamBatcherEventBuilder)
trigger = self.find(typ=l2si.TriggerEventBuffer)
# Reset all counters
self.CountReset()
# Arm for data/trigger stream
for devPtr in eventBuilder:
devPtr.Blowoff.set(False)
devPtr.SoftRst()
# Turn on the triggering
for devPtr in trigger:
devPtr.MasterEnable.set(True)
# Update the run state status variable
self.RunState.set(True)
def __init__(self,
dataDebug = False,
dev = '/dev/datadev_0',# path to PCIe device
pgp3 = True, # true = PGPv3, false = PGP2b
pollEn = True, # Enable automatic polling registers
initRead = True, # Read all registers at start of the system
defaultFile = None,
hwType = None,
**kwargs):
# Set the min. firmware Versions
self.PcieVersion = 0x04000000
self.FebVersion = 0x04000000
# Set local variables
self.defaultFile = defaultFile
self.dev = dev
kwargs['timeout'] = 5000000 # 5 s
devTarget = None
numPgpLanes = 0
numTimingLanes = 0
if hwType == 'DrpPgpTDet':
devTarget = l2si_drp.DrpPgpTDet
numPgpLanes = 1
numTimingLanes = 1
numDmaLanes = numPgpLanes + numTimingLanes
# Pass custom value to parent via super function
super().__init__(
dev = dev,
pgp3 = pgp3,
pollEn = pollEn,
initRead = initRead,
numLanes = numDmaLanes,
**kwargs)
# Create memory interface
self.memMap = axipcie.createAxiPcieMemMap(dev, 'localhost', 8000)
# Instantiate the top level Device and pass it the memory map
self.add(devTarget(
name = 'PgpPcie',
memBase = self.memMap,
numPgpLanes = numPgpLanes,
numTimingLanes = numTimingLanes,
pgp3 = pgp3,
expand = True,
))
# Create DMA streams
vcs = [0,1,2] if dataDebug else [0,2]
self.dmaStreams = axipcie.createAxiPcieDmaStreams(dev, {lane:{dest for dest in vcs} for lane in range(numDmaLanes)}, 'localhost', 8000)
# Check if not doing simulation
if (dev!='sim'):
# Create arrays to be filled
self._srp = [None for lane in range(numPgpLanes)]
# Create the stream interface
for lane in range(numPgpLanes):
# SRP
self._srp[lane] = rogue.protocols.srp.SrpV3()
pr.streamConnectBiDir(self.dmaStreams[lane][0],self._srp[lane])
# CameraLink Feb Board
self.add(feb.ClinkFeb(
name = (f'ClinkFeb[{lane}]'),
memBase = self._srp[lane],
serial = self.dmaStreams[lane][2],
camType = self.camType[lane],
version3 = pgp3,
enableDeps = [self.ClinkPcie.Hsio.PgpMon[lane].RxRemLinkReady], # Only allow access if the PGP link is established
expand = True,
))
# Create arrays to be filled
self._dbg = [None for lane in range(numPgpLanes)]
self.unbatchers = [rogue.protocols.batcher.SplitterV1() for lane in range(numPgpLanes)]
# Create the stream interface
for lane in range(numPgpLanes):
# Debug slave
if dataDebug:
# Connect the streams
#self.dmaStreams[lane][1] >> self.unbatchers[lane] >> self._dbg[lane]
self.dmaStreams[lane][1] >> self.unbatchers[lane]
self.add(pr.LocalVariable(
name = 'RunState',
description = 'Run state status, which is controlled by the StopRun() and StartRun() commands',
mode = 'RO',
value = False,
))
def __init__(
self,
*,
dev='/dev/datadev_0', # path to PCIe device
dataCapture=False,
dataDebug=False,
pgp3=False, # true = PGPv3, false = PGP2b
pollEn=True, # Enable automatic polling registers
initRead=True, # Read all registers at start of the system
numLanes=1,
**kwargs):
if dev == 'sim':
kwargs['timeout'] = 100000000
super().__init__(dev=dev,
pgp3=pgp3,
pollEn=pollEn,
initRead=initRead,
numLanes=numLanes,
**kwargs)
# Create memory interface
self.memMap = axipcie.createAxiPcieMemMap(dev, 'localhost', 8000)
# Instantiate the top level Device and pass it the memeory map
self.add(
lcls2_timetool.TimeToolKcu1500(memBase=self.memMap,
pgp3=pgp3,
expand=True))
# Create DMA streams
if dataCapture:
self.add(lcls2_timetool.RunControl())
self.add(pyrogue.utilities.fileio.StreamWriter(name='DataWriter'))
vcList = [0, 1, 2] # CLink SRP, Data, CLink serial
else:
vcList = [0, 2] # CLink SRP, CLink serial
self.dmaStreams = axipcie.createAxiPcieDmaStreams(
dev, {lane: {vc
for vc in vcList}
for lane in range(numLanes)}, 'localhost', 8000)
# Map dma streams to SRP, CLinkFebs
if (dev != 'sim'):
# Create arrays to be filled
self._srp = [None for lane in range(numLanes)]
# Create the stream interface
for lane in range(numLanes):
# SRP
self._srp[lane] = rogue.protocols.srp.SrpV3()
self.dmaStreams[lane][0] == self._srp[lane]
# CameraLink Feb Board
self.add(
ClinkFeb.ClinkFeb(
name=(f'ClinkFeb[{lane}]'),
memBase=self._srp[lane],
serial=self.dmaStreams[lane][2],
camType='Piranha4',
version3=pgp3,
enableDeps=[
self.TimeToolKcu1500.Kcu1500Hsio.PgpMon[lane].
RxRemLinkReady
], # Only allow access if the PGP link is established
expand=False))
# Else doing Rogue VCS simulation
else:
self.roguePgp = lcls2_pgp_fw_lib.hardware.shared.RogueStreams(
numLanes=numLanes, pgp3=pgp3)
# Create arrays to be filled
self._frameGen = [None for lane in range(numLanes)]
# Create the stream interface
for lane in range(numLanes):
# Create the frame generator
self._frameGen[lane] = lcls2_timetool.Piranha4VcsEmu(
'localhost', 7000)
# When a trigger is received, the fake frame generator will be called
self.roguePgp.pgpTriggers[lane].setRecvCb(
self._frameGen[lane].trigCb)
# Resulting frame will be pushed at pgp VC1
self._frameGen[lane] >> self.roguePgp.pgpStreams[lane][1]
if dataCapture:
# Connect the data writer
self >> self.DataWriter.getChannel(0)
# Create arrays to be filled
self._dbg = [DataDebug("DataDebug") for lane in range(numLanes)]
self.unbatchers = [
rogue.protocols.batcher.SplitterV1()
for lane in range(numLanes)
]
# Create the stream interface
for lane in range(numLanes):
self.dmaStreams[lane][1] >> self.DataWriter.getChannel(lane +
1)
# Debug slave
if dataDebug:
self.dmaStreams[lane][1] >> self.unbatchers[
lane] >> self._dbg[lane]
def __init__(
self,
dev=None,
pollEn=True, # Enable automatic polling registers
initRead=True, # Read all registers at start of the system
dataDebug=False,
enableConfig=False,
enVcMask=0x3, # Enable lane mask
**kwargs):
print(f'DevRoot dataDebug {dataDebug}')
# Set local variables
self.dev = dev
self.enableConfig = enableConfig
self.defaultFile = []
# Check for simulation
if dev == 'sim':
kwargs['timeout'] = 100000000 # 100 s
else:
kwargs['timeout'] = 5000000 # 5 s
# Pass custom value to parent via super function
super().__init__(pollEn=pollEn, initRead=initRead, **kwargs)
# Unhide the RemoteVariableDump command
self.RemoteVariableDump.hidden = False
# Create memory interface
self.memMap = axipcie.createAxiPcieMemMap(dev, 'localhost', 8000)
self.memMap.setName('PCIe_Bar0')
# Instantiate the top level Device and pass it the memory map
self.add(xpm.DevPcie(
name='Top',
memBase=self.memMap,
))
# Create empty list
self.dmaStreams = [[None for x in range(4)] for y in range(4)]
self._srp = [None for x in range(4)]
self._dbg = [None for x in range(4)]
self.enVcMask = [False for x in range(4)]
# Create DMA streams
lane = 0
if True:
for vc in range(4):
if enVcMask & (0x1 << vc):
self.enVcMask[vc] = True
if (dev is not 'sim'):
self.dmaStreams[lane][
vc] = rogue.hardware.axi.AxiStreamDma(
dev, (0x100 * lane) + vc, 1)
else:
self.dmaStreams[lane][
vc] = rogue.interfaces.stream.TcpClient(
'localhost',
(8000 + 2) + (512 * lane) + 2 * vc)
if dataDebug:
self._dbg[vc] = DataDebug(name='DataDebug')
# Connect the streams
self.dmaStreams[lane][vc] >> self._dbg[vc]
print(f'enVcMask {enVcMask} {self.enVcMask}')
# Check if not doing simulation
if (dev is not 'sim'):
# Create the stream interface
lane = 0
if True:
# Check if PGP[lane].VC[0] = SRPv3 (register access) is enabled
if self.enVcMask[0]:
# Create the SRPv3
self._srp[lane] = rogue.protocols.srp.SrpV3()
self._srp[lane].setName(f'SRPv3[{lane}]')
# Connect DMA to SRPv3
self.dmaStreams[lane][0] = self._srp[lane]
# Check if PGP[lane].VC[0] = SRPv3 (register access) is enabled
if self.enVcMask[0]:
self.add(
pr.LocalVariable(
name='RunState',
description=
'Run state status, which is controlled by the StopRun() and StartRun() commands',
mode='RO',
value=False,
))