def _translate_push_pop(self, tb, instruction, translate_fn):
# PUSH and POP are equivalent to STM and LDM in FD mode with the SP
# (and write-back) Instructions are modified to adapt it to the
# LDM/STM interface
sp_name = "r13" # TODO: Use self._sp
sp_size = instruction.operands[0].reg_list[0][0].size # Infer it from the registers list
sp_reg = ArmRegisterOperand(sp_name, sp_size)
sp_reg.wb = True
instruction.operands = [sp_reg, instruction.operands[0]]
instruction.ldm_stm_addr_mode = ARM_LDM_STM_FD
translate_fn(self, tb, instruction)
def _translate_push_pop(self, tb, instruction, translate_fn):
# PUSH and POP are equivalent to STM and LDM in FD mode with the SP
# (and write-back) Instructions are modified to adapt it to the
# LDM/STM interface
sp_name = "r13" # TODO: Use self._sp
sp_size = instruction.operands[0].reg_list[0][0].size # Infer it from the registers list
sp_reg = ArmRegisterOperand(sp_name, sp_size)
sp_reg.wb = True
instruction.operands = [sp_reg, instruction.operands[0]]
instruction.ldm_stm_addr_mode = ARM_LDM_STM_FD
translate_fn(self, tb, instruction)
def process_register(tokens):
name = tokens["name"]
if name in arch_info.registers_size:
size = arch_info.registers_size[name]
else:
size = arch_info.architecture_size
oprnd = ArmRegisterOperand(name, size)
return oprnd
def __cs_reg_idx_to_arm_op_reg(self, cs_reg_idx, cs_insn):
name = str(cs_insn.reg_name(cs_reg_idx))
if name in arm_alias_reg_map:
name = arm_alias_reg_map[name]
if name in self._arch_info.registers_size:
size = self._arch_info.registers_size[name]
else:
size = self._arch_info.architecture_size
return ArmRegisterOperand(name, size)