def _translate_bsh(self, oprnd1, oprnd2, oprnd3): """Return a formula representation of a BSH instruction. """ assert oprnd1.size and oprnd2.size and oprnd3.size assert oprnd1.size == oprnd2.size op1_var = self._translate_src_oprnd(oprnd1) op2_var = self._translate_src_oprnd(oprnd2) op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3) if oprnd3.size > oprnd1.size: op1_var_zx = smtfunction.zero_extend(op1_var, oprnd3.size) op2_var_zx = smtfunction.zero_extend(op2_var, oprnd3.size) op2_var_neg_sx = smtfunction.sign_extend(-op2_var, oprnd3.size) shr = smtfunction.extract(op1_var_zx >> op2_var_neg_sx, 0, op3_var.size) shl = smtfunction.extract(op1_var_zx << op2_var_zx, 0, op3_var.size) elif oprnd3.size < oprnd1.size: shr = smtfunction.extract(op1_var >> -op2_var, 0, op3_var.size) shl = smtfunction.extract(op1_var << op2_var, 0, op3_var.size) else: shr = op1_var >> -op2_var shl = op1_var << op2_var result = smtfunction.ite(oprnd3.size, op2_var >= 0, shl, shr) return [op3_var == result] + op3_var_constrs
def _translate_smul(self, oprnd1, oprnd2, oprnd3): """Return a formula representation of an MUL instruction. """ assert oprnd1.size and oprnd2.size and oprnd3.size assert oprnd1.size == oprnd2.size op1_var = self._translate_src_oprnd(oprnd1) op2_var = self._translate_src_oprnd(oprnd2) op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3) if oprnd3.size > oprnd1.size: op1_var_sx = smtfunction.sign_extend(op1_var, oprnd3.size) op2_var_sx = smtfunction.sign_extend(op2_var, oprnd3.size) result = op1_var_sx * op2_var_sx elif oprnd3.size < oprnd1.size: result = smtfunction.extract(op1_var * op2_var, 0, oprnd3.size) else: result = op1_var * op2_var return [op3_var == result] + op3_var_constrs
def _translate_smod(self, oprnd1, oprnd2, oprnd3): """Return a formula representation of an MOD instruction. """ assert oprnd1.size and oprnd2.size and oprnd3.size assert oprnd1.size == oprnd2.size op1_var = self._translate_src_oprnd(oprnd1) op2_var = self._translate_src_oprnd(oprnd2) op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3) if oprnd3.size > oprnd1.size: op1_var_sx = smtfunction.sign_extend(op1_var, oprnd3.size) op2_var_sx = smtfunction.sign_extend(op2_var, oprnd3.size) result = op1_var_sx % op2_var_sx elif oprnd3.size < oprnd1.size: result = smtfunction.extract(op1_var % op2_var, 0, oprnd3.size) else: result = op1_var % op2_var return [op3_var == result] + op3_var_constrs
def _translate_sext(self, oprnd1, oprnd2, oprnd3): """Return a formula representation of a SEXT instruction. """ assert oprnd1.size and oprnd3.size op1_var = self._translate_src_oprnd(oprnd1) op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3) if oprnd3.size > oprnd1.size: result = smtfunction.sign_extend(op1_var, op3_var.size) elif oprnd3.size < oprnd1.size: raise Exception("Operands size mismatch.") else: result = op1_var return [op3_var == result] + op3_var_constrs
def test_sign_extend(self): x = BitVec(32, "x") y = sign_extend(x, 64) self.assertEqual(y.value, "((_ sign_extend 32) x)")