def init_lfsr_14_lut(): """ Generates a 14bit LFSR according to Manual v1.9 page 19 """ lfsr = BitLogic(14) lfsr[7:0] = 0xFF lfsr[13:8] = 63 dummy = 0 for i in range(2**14): _lfsr_14_lut[BitLogic.tovalue(lfsr)] = i dummy = lfsr[13] lfsr[13] = lfsr[12] lfsr[12] = lfsr[11] lfsr[11] = lfsr[10] lfsr[10] = lfsr[9] lfsr[9] = lfsr[8] lfsr[8] = lfsr[7] lfsr[7] = lfsr[6] lfsr[6] = lfsr[5] lfsr[5] = lfsr[4] lfsr[4] = lfsr[3] lfsr[3] = lfsr[2] lfsr[2] = lfsr[1] lfsr[1] = lfsr[0] lfsr[0] = lfsr[2] ^ dummy ^ lfsr[12] ^ lfsr[13] _lfsr_14_lut[2**14 - 1] = 0
def get_value(self, addr, size, offset, **kwargs): '''Reading a value of any arbitrary size (max. unsigned int 64) and offset from a register Parameters ---------- addr : int The register address. size : int Bit size/length of the value. offset : int Offset of the value to be written to the register (in number of bits). Returns ------- reg : int Register value. ''' div_offset, mod_offset = divmod(offset, 8) div_size, mod_size = divmod(size + mod_offset, 8) if mod_size: div_size += 1 ret = self._intf.read(self._base_addr + addr + div_offset, size=div_size) reg = BitLogic() reg.frombytes(tobytes(ret)) return reg[size + mod_offset - 1:mod_offset].tovalue()
def test_endianness_of_string_assignment(self): '''test indexing ''' bl_1 = BitLogic('11001000') bl_2 = BitLogic(8) bl_2[:] = '11001000' self.assertEqual(bl_1, bl_2)
def __init__(self, driver, conf): super(StdRegister, self).__init__(driver, conf) self._size = conf['size'] self._fields = dict() self._bv = None self._fields_conf = dict() if 'fields' in self._conf: for field in self._conf['fields']: if field['offset'] + 1 < field['size']: raise ValueError( "Register " + self._conf['name'] + ":" + field['name'] + ": Invalid offset value. Specify MSB position.") if 'repeat' in field: reg_list = [] for _ in range(field['repeat']): reg = StdRegister(None, field) reg_list.append(reg) self._fields[field['name']] = reg_list else: bv = BitLogic(field['size']) self._fields[field['name']] = bv self._fields_conf[field['name']] = field # set default if "default" in field: self[field['name']] = field['default'] self._bv = BitLogic(self._conf['size'])
def test_pixel_address_functions(self): self.startUp() logging.info("Test pixel address function errors") # Test for errors with self.assertRaises(ValueError): self.chip.xy_to_pixel_address(256, 0) with self.assertRaises(ValueError): self.chip.xy_to_pixel_address(0, 256) with self.assertRaises(ValueError): self.chip.pixel_address_to_x( BitLogic.from_value(0b10000000000000000)) with self.assertRaises(ValueError): self.chip.pixel_address_to_y( BitLogic.from_value(0b10000000000000000)) logging.info("Test pixel address functions") # Test for valid addresses pbar = tqdm(total=256 * 256) for x in range(256): for y in range(256): address = self.chip.xy_to_pixel_address(x, y) self.assertEquals(x, self.chip.pixel_address_to_x(address)) self.assertEquals(y, self.chip.pixel_address_to_y(address)) pbar.update(1) pbar.close()
def get_value(self, addr, size, offset, **kwargs): '''Reading a value of any arbitrary size (max. unsigned int 64) and offset from a register Parameters ---------- addr : int The register address. size : int Bit size/length of the value. offset : int Offset of the value to be written to the register (in number of bits). Returns ------- reg : int Register value. ''' div_offset, mod_offset = divmod(offset, 8) div_size, mod_size = divmod(size + mod_offset, 8) if mod_size: div_size += 1 ret = self._intf.read(self._base_addr + addr + div_offset, size=div_size) reg = BitLogic() reg.frombytes(ret.tostring()) return reg[size + mod_offset - 1:mod_offset].tovalue()
def set_value(self, value, addr, size, offset, **kwargs): '''Writing a value of any arbitrary size (max. unsigned int 64) and offset to a register Parameters ---------- value : int, str The register value (int, long, bit string) to be written. addr : int The register address. size : int Bit size/length of the value to be written to the register. offset : int Offset of the value to be written to the register (in number of bits). Returns ------- nothing ''' div_offset, mod_offset = divmod(offset, 8) div_size, mod_size = divmod(size + mod_offset, 8) if mod_size: div_size += 1 if mod_offset == 0 and mod_size == 0: reg = BitLogic.from_value(0, size=div_size * 8) else: ret = self._intf.read(self._base_addr + addr + div_offset, size=div_size) reg = BitLogic() reg.frombytes(ret.tostring()) reg[size + mod_offset - 1:mod_offset] = value self._intf.write(self._base_addr + addr + div_offset, data=array.array('B', reg.tobytes()))
def set_value(self, value, addr, size, offset, **kwargs): '''Writing a value of any arbitrary size (max. unsigned int 64) and offset to a register Parameters ---------- value : int, str The register value (int, long, bit string) to be written. addr : int The register address. size : int Bit size/length of the value to be written to the register. offset : int Offset of the value to be written to the register (in number of bits). Returns ------- nothing ''' div, mod = divmod(size + offset, 8) if mod: div += 1 ret = self._intf.read(self._base_addr + addr, size=div) reg = BitLogic() reg.frombytes(ret.tostring()) reg[size + offset - 1:offset] = value self._intf.write(self._base_addr + addr, data=array.array('B', reg.tobytes()))
def pretty_print(string_val, bits=32): val = int(string_val) bits = BitLogic(bits) bits[:] = val lst = bits.toByteList(True) lst_hex = map(hex, bits.toByteList(False)) print "Int ", lst print "Hex ", lst_hex print "Binary ", bits
def run_tests(): chip = TPX3() # TODO: some way to not initialize the hardware? chip.init() dac = "Vfbk" dac_bits = chip.dac_valsize_map[dac] # some number larger than the allowed value val_large = 2**(dac_bits + 2) val_allowed = 2**(dac_bits - 1) print dac_bits, val_allowed # Don't want to bother with unittest module for now, so poor man's # "assertraises" try: # check if ValueError is correctly raised chip.set_dac(dac, val_large, write=False) raise Exception except ValueError: pass dac_set = chip.getGlobalSyncHeader() assert (dac_set == [0xAA, 0x00, 0x00, 0x00, 0x00]) # set DAC is command 0x02 dac_set += [0x02] # , 0x00] # val_allowed is last part of returned array from basil.utils.BitLogic import BitLogic bits = BitLogic(16) bits[13:5] = val_allowed bits[4:0] = 0x05 print bits.toByteList() # dac_set += [val_allowed] # Vfkb has DAC code 0x05 # dac_set += [0x05] dac_set += bits.toByteList() print "Return value of set_dac ".ljust(30), chip.set_dac(dac, val_allowed, write=False) print "Value we expect?! ".ljust(30), dac_set assert (chip.set_dac(dac, val_allowed, write=False) == dac_set) dac_read = chip.getGlobalSyncHeader() # read DAC is command 0x03 dac_read += [0x03] # empty byte dac_read += [0x00] # add DAC code of Vfkb, which is 0x05 dac_read += [0x05] print "Return value of read_dac ".ljust(30), chip.read_dac(dac, write=False) print "Value we expect?!".ljust(30), dac_read print "Value we officially expect".ljust(30), chip.read_dac_exp( dac, val_allowed) assert (chip.read_dac(dac, write=False) == dac_read) print("All tests done")
def init_gray_14_lut(): """ Generates a 14bit gray according to Manual v1.9 page 19 """ for j in range(2**14): encoded_value = BitLogic(14) #48 encoded_value[13:0] = j #47 gray_decrypt_v = BitLogic(14) #48 gray_decrypt_v[13] = encoded_value[13] #47 for i in range(12, -1, -1): #46 gray_decrypt_v[i] = gray_decrypt_v[i + 1] ^ encoded_value[i] _gray_14_lut[j] = gray_decrypt_v.tovalue()
def gray_decrypt(value): """ Decrypts a gray encoded 48 bit value according to Manual v1.9 page 19 """ encoded_value = BitLogic(48) encoded_value[47:0] = value gray_decrypt = BitLogic(48) gray_decrypt[47] = encoded_value[47] for i in range(46, -1, -1): gray_decrypt[i] = gray_decrypt[i + 1] ^ encoded_value[i] return gray_decrypt
def init_lfsr_4_lut(): """ Generates a 4bit LFSR according to Manual v1.9 page 19 """ lfsr = BitLogic(4) lfsr[3:0] = 0xF dummy = 0 for i in range(2**4): _lfsr_4_lut[BitLogic.tovalue(lfsr)] = i dummy = lfsr[3] lfsr[3] = lfsr[2] lfsr[2] = lfsr[1] lfsr[1] = lfsr[0] lfsr[0] = lfsr[3] ^ dummy _lfsr_4_lut[2**4 - 1] = 0
def _scan(self, data): self.reg['TMS'] = 0 self._write() # capture self.reg['TMS'] = 0 ret_bit = self._write() # shift ret = [] for dev in range(len(data)): dev_ret = BitLogic(len(data[dev])) for bit in range(len(data[dev])): if dev == len(data) - 1 and bit == len(data[dev]) - 1: self.reg['TMS'] = 1 # exit1 self.reg['TDI'] = data[dev][bit] dev_ret[bit] = ret_bit ret_bit = self._write() ret.append(dev_ret) self.reg['TDI'] = 0 self.reg['TMS'] = 1 self._write() # update self.reg['TMS'] = 0 self._write() # idle return ret
def __init__(self, driver, conf): super(StdRegister, self).__init__(driver, conf) self._size = conf['size'] self._fields = dict() self._bv = None self._fields_conf = dict() if 'fields' in self._conf: for field in self._conf['fields']: if field['offset'] + 1 < field['size']: raise ValueError("Register " + self._conf['name'] + ":" + field['name'] + ": Invalid offset value. Specify MSB position.") if 'repeat' in field: reg_list = [] for _ in range(field['repeat']): reg = StdRegister(None, field) reg_list.append(reg) self._fields[field['name']] = reg_list else: bv = BitLogic(field['size']) self._fields[field['name']] = bv self._fields_conf[field['name']] = field # set default if "default" in field: self[field['name']] = field['default'] self._bv = BitLogic(self._conf['size'])
def test_wrong_size_of_string_assignment(self): '''test assignment of wrong length bit string ''' bl_2 = BitLogic(8) def assign_fails_slice_all(): bl_2[:] = '110010000' def assign_fails_slice_part_1(): bl_2[3:] = '11110' def assign_fails_slice_part_2(): bl_2[:4] = '11110' def assign_fails_slice_part_3(): bl_2[4:2] = '11110' def assign_fails_slice_part_4(): bl_2[4:2] = '1' self.assertRaises(ValueError, assign_fails_slice_all) self.assertRaises(ValueError, assign_fails_slice_part_1) self.assertRaises(ValueError, assign_fails_slice_part_2) self.assertRaises(ValueError, assign_fails_slice_part_3) self.assertRaises(ValueError, assign_fails_slice_part_4)
def _scan(self, data): self.reg['TMS'] = 0 self._write() # capture self.reg['TMS'] = 0 ret_bit = self._write(tdo=True) ret = [] size_dev = len(data) for dev in range(size_dev): dev_ret = BitLogic(len(data[dev])) size = len(data[dev]) for bit in range(size): if dev == len(data) - 1 and bit == len(data[dev]) - 1: self.reg['TMS'] = 1 # exit1 self.reg['TDI'] = data[dev][bit] dev_ret[bit] = ret_bit if bit == size - 1 and dev == size_dev - 1: # last bit self._write() else: ret_bit = self._write(tdo=True) ret.append(dev_ret) self.reg['TDI'] = 0 self.reg['TMS'] = 1 self._write() # update self.reg['TMS'] = 0 self._write() # idle return ret
def test_set_item(self): bl = BitLogic.from_value(8, size=9, fmt='Q') self.assertEqual(bl[3], True) self.assertEqual(bl[2], False) self.assertEqual(bl[4], False) bl[2] = True self.assertEqual(bl[3], True) self.assertEqual(bl[2], True) self.assertEqual(bl[4], False) def assign_index(value): bl[4] = value self.assertRaises(IndexError, lambda val: assign_index(val), []) self.assertRaises(IndexError, lambda val: assign_index(val), [1, 2]) self.assertRaises(IndexError, lambda val: assign_index(val), [True]) self.assertRaises(IndexError, lambda val: assign_index(val), [False]) self.assertRaises(IndexError, lambda val: assign_index(val), [True, False]) def assign_slice(value): bl[2:1] = value self.assertRaises(IndexError, lambda val: assign_slice(val), []) self.assertRaises(IndexError, lambda val: assign_slice(val), [1, 2]) self.assertRaises(IndexError, lambda val: assign_slice(val), [True]) self.assertRaises(IndexError, lambda val: assign_slice(val), [False]) self.assertRaises(IndexError, lambda val: assign_slice(val), [True, False])
def test_get_item_with_slice(self): bl = BitLogic.from_value(12, size=9, fmt='Q') self.assertEqual(bl[3:1], bitarray('011')) self.assertEqual(bl[:], bitarray('001100000')) self.assertEqual(bl[bl.length():], bitarray('001100000')) self.assertEqual(bl[len(bl):], bitarray('001100000')) self.assertEqual(bl[len(bl):0], bitarray('001100000'))
def __init__(self, data_word, chip_flavor, tdc_trig_dist=False, trigger_data_mode=0): self.record_rawdata = int(data_word) self.record_word = BitLogic.from_value(value=self.record_rawdata, size=32) self.record_dict = OrderedDict() if self.record_rawdata & 0x80000000: self.record_type = "TW" if trigger_data_mode == 0: self.record_dict.update([('trigger number', self.record_word[30:0].tovalue())]) elif trigger_data_mode == 1: self.record_dict.update([('trigger timestamp', self.record_word[30:0].tovalue())]) elif trigger_data_mode == 2: self.record_dict.update([('trigger timestamp', self.record_word[30:16].tovalue()), ('trigger number', self.record_word[15:0].tovalue())]) else: raise ValueError("Unknown trigger data mode %d" % trigger_data_mode) elif self.record_rawdata & 0xF0000000 == 0x40000000: self.record_type = "TDC" if tdc_trig_dist: self.record_dict.update([('tdc distance', self.record_word[27:20].tovalue()), ('tdc counter', self.record_word[19:12].tovalue()), ('tdc value', self.record_word[11:0].tovalue())]) else: self.record_dict.update([('tdc counter', self.record_word[27:12].tovalue()), ('tdc value', self.record_word[11:0].tovalue())]) elif not self.record_rawdata & 0xF0000000: # FE data self.record_dict.update([('channel', (self.record_rawdata & 0x0F000000) >> 24)]) self.chip_flavor = chip_flavor if self.chip_flavor not in flavors: raise KeyError('Chip flavor is not of type {}'.format(', '.join('\'' + flav + '\'' for flav in self.chip_flavors))) if is_data_header(self.record_rawdata): self.record_type = "DH" if self.chip_flavor == "fei4a": self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('flag', self.record_word[15:15].tovalue()), ('lvl1id', self.record_word[14:8].tovalue()), ('bcid', self.record_word[7:0].tovalue())]) elif self.chip_flavor == "fei4b": self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('flag', self.record_word[15:15].tovalue()), ('lvl1id', self.record_word[14:10].tovalue()), ('bcid', self.record_word[9:0].tovalue())]) elif is_address_record(self.record_rawdata): self.record_type = "AR" self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('type', self.record_word[15:15].tovalue()), ('address', self.record_word[14:0].tovalue())]) elif is_value_record(self.record_rawdata): self.record_type = "VR" self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('value', self.record_word[15:0].tovalue())]) elif is_service_record(self.record_rawdata): self.record_type = "SR" if self.chip_flavor == "fei4a": self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('counter', self.record_word[9:0].tovalue())]) elif self.chip_flavor == "fei4b": if self.record_word[15:10].tovalue() == 14: self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('lvl1id[11:5]', self.record_word[9:3].tovalue()), ('bcid[12:10]', self.record_word[2:0].tovalue())]) elif self.record_word[15:10].tovalue() == 15: self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('skipped', self.record_word[9:0].tovalue())]) elif self.record_word[15:10].tovalue() == 16: self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('truncation flag', self.record_word[9:9].tovalue()), ('truncation counter', self.record_word[8:4].tovalue()), ('l1req', self.record_word[3:0].tovalue())]) else: self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('counter', self.record_word[9:0].tovalue())]) elif is_data_record(self.record_rawdata): self.record_type = "DR" self.record_dict.update([('column', self.record_word[23:17].tovalue()), ('row', self.record_word[16:8].tovalue()), ('tot1', self.record_word[7:4].tovalue()), ('tot2', self.record_word[3:0].tovalue())]) else: self.record_type = "UNKNOWN FE WORD" self.record_dict.update([('word', self.record_word.tovalue())]) # raise ValueError('Unknown data word: ' + str(self.record_word.tovalue())) else: self.record_type = "UNKNOWN WORD" self.record_dict.update([('unknown', self.record_word[31:0].tovalue())])
def test_set_item(self): bl = BitLogic.from_value(8, size=9, fmt="Q") self.assertEqual(bl[3], True) self.assertEqual(bl[2], False) self.assertEqual(bl[4], False) bl[2] = True self.assertEqual(bl[3], True) self.assertEqual(bl[2], True) self.assertEqual(bl[4], False) def assign_index(value): bl[4] = value self.assertRaises(IndexError, lambda val: assign_index(val), []) self.assertRaises(IndexError, lambda val: assign_index(val), [1, 2]) self.assertRaises(IndexError, lambda val: assign_index(val), [True]) self.assertRaises(IndexError, lambda val: assign_index(val), [False]) self.assertRaises(IndexError, lambda val: assign_index(val), [True, False]) def assign_slice(value): bl[2:1] = value self.assertRaises(IndexError, lambda val: assign_slice(val), []) self.assertRaises(IndexError, lambda val: assign_slice(val), [1, 2]) self.assertRaises(IndexError, lambda val: assign_slice(val), [True]) self.assertRaises(IndexError, lambda val: assign_slice(val), [False]) self.assertRaises(IndexError, lambda val: assign_slice(val), [True, False])
def test_get_item_with_slice(self): bl = BitLogic.from_value(12, size=9, fmt="Q") self.assertEqual(bl[3:1], bitarray("011")) self.assertEqual(bl[:], bitarray("001100000")) self.assertEqual(bl[bl.length() :], bitarray("001100000")) self.assertEqual(bl[len(bl) :], bitarray("001100000")) self.assertEqual(bl[len(bl) : 0], bitarray("001100000"))
def bitword_to_byte_list(data, string=False): """ Given a 32 bit word, convert it to a list of bytes using BitLogic """ result = BitLogic(32) result[31:0] = int(data) result = toByteList(result, string) return result
def test_indexing(self): """test indexing """ bl = BitLogic.from_value(128, size=8, fmt="Q", endian="little") self.assertEqual(bl[7], True) self.assertEqual(bl[7:7], bitarray("1")) self.assertEqual(bl[-1], True) self.assertEqual(bl[0], False) self.assertEqual(bl[0:0], bitarray("0"))
def test_indexing(self): '''test indexing ''' bl = BitLogic.from_value(128, size=8, fmt='Q', endian='little') self.assertEqual(bl[7], True) self.assertEqual(bl[7:7], bitarray('1')) self.assertEqual(bl[-1], True) self.assertEqual(bl[0], False) self.assertEqual(bl[0:0], bitarray('0'))
def _set_power_gpio(self, bit, value): self._set_i2c_mux(self.I2CBUS_DAC) gpio = BitLogic.from_value(self._get_power_gpio(), size=8) gpio[bit] = value self._intf.write(self._base_addr + self.POWER_GPIO_ADD, (self.PCA9554_OUT, gpio.tovalue())) self._set_i2c_mux(self.I2CBUS_DEFAULT)
def test_get_type_slicing_and_indexing(self): bl = BitLogic('01000000') self.assertIsInstance(bl[3:], bitarray) self.assertIsInstance(bl[:3], bitarray) self.assertIsInstance(bl[:], bitarray) self.assertIsInstance(bl[3:1], bitarray) self.assertIsInstance(bl[1:1], bitarray) self.assertIsInstance(bl[2:2], bitarray) self.assertIsInstance(bl[1], bool) self.assertIsInstance(bl[2], bool)
def test_get_item(self): bl = BitLogic.from_value(259, size=9, fmt='Q') self.assertEqual(bl[0], True) self.assertEqual(bl[1], True) self.assertEqual(bl[2], False) self.assertEqual(bl[3], False) self.assertEqual(bl[4], False) self.assertEqual(bl[5], False) self.assertEqual(bl[6], False) self.assertEqual(bl[7], False) self.assertEqual(bl[8], True)
def test_get_item(self): bl = BitLogic.from_value(259, size=9, fmt="Q") self.assertEqual(bl[0], True) self.assertEqual(bl[1], True) self.assertEqual(bl[2], False) self.assertEqual(bl[3], False) self.assertEqual(bl[4], False) self.assertEqual(bl[5], False) self.assertEqual(bl[6], False) self.assertEqual(bl[7], False) self.assertEqual(bl[8], True)
def init_links(self): ''' Initializes the links for communication ''' # Open the link yaml file proj_dir = os.path.dirname(os.path.dirname(os.path.abspath(__file__))) yaml_file = os.path.join(proj_dir, 'tpx3' + os.sep + 'links.yml') if not yaml_file == None: with open(yaml_file) as file: yaml_data = yaml.load(file, Loader=yaml.FullLoader) # Deactivate all fpga links for register in yaml_data['registers']: self.chip[register['name']].ENABLE = 0 self.chip[register['name']].reset() self.chip._outputBlocks["chan_mask"] = 0 ID_List = [] # Iterate over all links for register in yaml_data['registers']: if register['chip-id'] != 0: # Create the chip output channel mask and write the output block self.chip._outputBlocks["chan_mask"] = self.chip._outputBlocks[ "chan_mask"] | (0b1 << register['chip-link']) # Activate the current fpga link and set all its settings self.chip[register['name']].ENABLE = 1 self.chip[register['name']].DATA_DELAY = register['data-delay'] self.chip[register['name']].INVERT = register['data-invert'] self.chip[ register['name']].SAMPLING_EDGE = register['data-edge'] bit_id = BitLogic.from_value(register['chip-id']) # Decode the Chip-ID self.wafer_number = bit_id[19:8].tovalue() self.x_position = chr(ord('a') + bit_id[3:0].tovalue() - 1).upper() self.y_position = bit_id[7:4].tovalue() ID = 'W' + str( self.wafer_number) + '-' + self.x_position + str( self.y_position) # Write new Chip-ID to the list if ID not in ID_List: ID_List.append(ID) self.number_of_chips = len(ID_List) if self.number_of_chips > 1: raise NotImplementedError( 'Handling of multiple chips is not implemented yet')
def test_endianness(self): """changing the bit order of each byte """ bl = BitLogic.from_value(259, size=9, fmt="Q", endian="big") self.assertEqual(bl[0], False) self.assertEqual(bl[1], False) self.assertEqual(bl[2], False) self.assertEqual(bl[3], False) self.assertEqual(bl[5], False) self.assertEqual(bl[6], True) self.assertEqual(bl[7], True) self.assertEqual(bl[8], False)
def test_endianness(self): '''changing the bit order of each byte ''' bl = BitLogic.from_value(259, size=9, fmt='Q', endian='big') self.assertEqual(bl[0], False) self.assertEqual(bl[1], False) self.assertEqual(bl[2], False) self.assertEqual(bl[3], False) self.assertEqual(bl[5], False) self.assertEqual(bl[6], True) self.assertEqual(bl[7], True) self.assertEqual(bl[8], False)
def __init__(self, data_word, chip_flavor, tdc_trig_dist=False): self.record_rawdata = int(data_word) self.record_word = BitLogic.from_value(value=self.record_rawdata, size=32) self.record_dict = OrderedDict() if self.record_rawdata & 0x80000000: self.record_type = "TW" self.record_dict.update([('trigger data', self.record_word[30:0].tovalue())]) elif self.record_rawdata & 0xF0000000 == 0x40000000: self.record_type = "TDC" if tdc_trig_dist: self.record_dict.update([('tdc distance', self.record_word[27:20].tovalue()), ('tdc counter', self.record_word[19:12].tovalue()), ('tdc value', self.record_word[11:0].tovalue())]) else: self.record_dict.update([('tdc counter', self.record_word[27:12].tovalue()), ('tdc value', self.record_word[11:0].tovalue())]) elif not self.record_rawdata & 0xF0000000: # FE data self.record_dict.update([('channel', (self.record_rawdata & 0x0F000000) >> 24)]) self.chip_flavor = chip_flavor if self.chip_flavor not in flavors: raise KeyError('Chip flavor is not of type {}'.format(', '.join('\'' + flav + '\'' for flav in self.chip_flavors))) if is_data_header(self.record_rawdata): self.record_type = "DH" if self.chip_flavor == "fei4a": self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('flag', self.record_word[15:15].tovalue()), ('lvl1id', self.record_word[14:8].tovalue()), ('bcid', self.record_word[7:0].tovalue())]) elif self.chip_flavor == "fei4b": self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('flag', self.record_word[15:15].tovalue()), ('lvl1id', self.record_word[14:10].tovalue()), ('bcid', self.record_word[9:0].tovalue())]) elif is_address_record(self.record_rawdata): self.record_type = "AR" self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('type', self.record_word[15:15].tovalue()), ('address', self.record_word[14:0].tovalue())]) elif is_value_record(self.record_rawdata): self.record_type = "VR" self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('value', self.record_word[15:0].tovalue())]) elif is_service_record(self.record_rawdata): self.record_type = "SR" if self.chip_flavor == "fei4a": self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('counter', self.record_word[9:0].tovalue())]) elif self.chip_flavor == "fei4b": if self.record_word[15:10].tovalue() == 14: self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('lvl1id[11:5]', self.record_word[9:3].tovalue()), ('bcid[12:10]', self.record_word[2:0].tovalue())]) elif self.record_word[15:10].tovalue() == 15: self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('skipped', self.record_word[9:0].tovalue())]) elif self.record_word[15:10].tovalue() == 16: self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('truncation flag', self.record_word[9:9].tovalue()), ('truncation counter', self.record_word[8:4].tovalue()), ('l1req', self.record_word[3:0].tovalue())]) else: self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('counter', self.record_word[9:0].tovalue())]) elif is_data_record(self.record_rawdata): self.record_type = "DR" self.record_dict.update([('column', self.record_word[23:17].tovalue()), ('row', self.record_word[16:8].tovalue()), ('tot1', self.record_word[7:4].tovalue()), ('tot2', self.record_word[3:0].tovalue())]) else: self.record_type = "UNKNOWN FE WORD" self.record_dict.update([('word', self.record_word.tovalue())]) # raise ValueError('Unknown data word: ' + str(self.record_word.tovalue())) else: self.record_type = "UNKNOWN WORD" self.record_dict.update([('unknown', self.record_word[31:0].tovalue())])
def __init__(self, driver, conf): super(StdRegister, self).__init__(driver, conf) self._size = conf['size'] self._fields = dict() if 'fields' in self._conf: for field in self._conf['fields']: if 'repeat' in field: reg_list = [] for _ in range(field['repeat']): reg = StdRegister(None, field) reg_list.append(reg) self._fields[field['name']] = reg_list else: bv = BitLogic(field['size']) self._fields[field['name']] = bv self._fields_conf[field['name']] = field # set default if "default" in field: self[field['name']] = field['default'] self._bv = BitLogic(self._conf['size'])
def test_from_value_long_long(self): if struct.calcsize("P") == 4: # 32-bit self.assertRaises(struct.error, BitLogic.from_value, 57857885568556688222588556, fmt='Q') else: bl = BitLogic.from_value(4772894553230993930 * 2, fmt='Q') self.assertEqual( bl, bitarray( '1000010001111001011101001001110111010111011101011101010000010100'[:: -1] ))
def deactivate_column(self, disable_columns): ''' Deactivate specific columns of Mimosa26. MSB: plane 6, LSB: plane 1 ''' self.dut['JTAG'].reset() # Convert binary string to array in order to modify it dis_discri_all_old = np.array(map(int, self.dut['DIS_DISCRI_ALL'][:])) dis_discri_all = np.logical_or(dis_discri_all_old, disable_columns).astype(int) # Set configuration self.dut['DIS_DISCRI_ALL'][:] = ''.join(map(str, dis_discri_all[::-1])) # Write register self.dut['JTAG'].scan_ir([BitLogic('10001')] * 6) self.dut['JTAG'].scan_dr([self.dut['DIS_DISCRI_ALL'][:]])[0]
def init_lfsr_10_lut(): """ Generates a 10bit LFSR according to Manual v1.9 page 19 """ lfsr = BitLogic(10) lfsr[7:0] = 0xFF lfsr[9:8] = 0b11 dummy = 0 for i in range(2**10): _lfsr_10_lut[BitLogic.tovalue(lfsr)] = i dummy = lfsr[9] lfsr[9] = lfsr[8] lfsr[8] = lfsr[7] lfsr[7] = lfsr[6] lfsr[6] = lfsr[5] lfsr[5] = lfsr[4] lfsr[4] = lfsr[3] lfsr[3] = lfsr[2] lfsr[2] = lfsr[1] lfsr[1] = lfsr[0] lfsr[0] = lfsr[7] ^ dummy _lfsr_10_lut[2**10 - 1] = 0
def test_get_slicing_and_indexing(self): bl = BitLogic('10000110') self.assertFalse(bl[0]) self.assertTrue(bl[1]) self.assertTrue(bl[2]) self.assertFalse(bl[3]) self.assertFalse(bl[4]) self.assertFalse(bl[5]) self.assertFalse(bl[6]) self.assertTrue(bl[7]) self.assertEqual(bl[3:0], bitarray('0110')) self.assertEqual(bl[3:0], bitarray('0110')) self.assertEqual(bl[3:], bitarray('0110')) self.assertEqual(bl[:3], bitarray('00001')) self.assertEqual(bl[:], bitarray('01100001'))
def test_set_item(self): bl = BitLogic.from_value(8, size=9, fmt='Q') self.assertEqual(bl[3], True) self.assertEqual(bl[2], False) self.assertEqual(bl[4], False) bl[2] = True self.assertEqual(bl[3], True) self.assertEqual(bl[2], True) self.assertEqual(bl[4], False) bl[4] = [] self.assertEqual(bl[3], True) self.assertEqual(bl[2], True) self.assertEqual(bl[4], False) bl[4] = [1, 2, 3] self.assertEqual(bl[3], True) self.assertEqual(bl[2], True) self.assertEqual(bl[4], True)
def test_set_item_with_slice(self): ba = bitarray("001100000") ba[1:3] = bitarray("11") self.assertEqual(ba[:], bitarray("011100000")) bl = BitLogic.from_value(12, size=9, fmt="Q") self.assertEqual(bl[:], bitarray("001100000")) bl[2:1] = bitarray("10") self.assertEqual(bl[:], bitarray("010100000")) bl[2:1] = bitarray("01") self.assertEqual(bl[:], bitarray("001100000")) bl[:] = 5 self.assertEqual(bl[:], bitarray("101000000")) bl[5:3] = 7 self.assertEqual(bl[:], bitarray("101111000")) bl[5:3] = 0 self.assertEqual(bl[:], bitarray("101000000")) bl[4:4] = bitarray("1") self.assertEqual(bl[:], bitarray("101010000")) bl[4:4] = 0 self.assertEqual(bl[:], bitarray("101000000")) bl[8:8] = 1 self.assertEqual(bl[:], bitarray("101000001")) bl[0:0] = 0 self.assertEqual(bl[:], bitarray("001000001")) bl[3:] = "1111" self.assertEqual(bl[:], bitarray("111100001")) bl[:4] = "11111" self.assertEqual(bl[:], bitarray("111111111")) bl[2:1] = "00" self.assertEqual(bl[:], bitarray("100111111")) bl[4:] = 0x0 self.assertEqual(bl[:], bitarray("000001111")) bl[:] = 2 ** 8 self.assertEqual(bl[:], bitarray("000000001")) bl[7] = True self.assertEqual(bl[:], bitarray("000000011")) bl[8] = False self.assertEqual(bl[:], bitarray("000000010")) bl[8:8] = True self.assertEqual(bl[:], bitarray("000000011")) bl[0:0] = True self.assertEqual(bl[:], bitarray("100000011"))
def frombytes(self, value): bl_value = BitLogic() bl_value.frombytes(array.array('B', value)[::-1].tostring()) self._deconstruct_reg(bl_value[self._conf['size']:])
class StdRegister(RegisterLayer): _bv = None _fields_conf = dict() def __init__(self, driver, conf): super(StdRegister, self).__init__(driver, conf) self._size = conf['size'] self._fields = dict() if 'fields' in self._conf: for field in self._conf['fields']: if 'repeat' in field: reg_list = [] for _ in range(field['repeat']): reg = StdRegister(None, field) reg_list.append(reg) self._fields[field['name']] = reg_list else: bv = BitLogic(field['size']) self._fields[field['name']] = bv self._fields_conf[field['name']] = field # set default if "default" in field: self[field['name']] = field['default'] self._bv = BitLogic(self._conf['size']) # TODO: check if offsets sizes are right! def __getitem__(self, items): if isinstance(items, str): return self._fields[items] elif isinstance(items, slice): reg = self._construct_reg() return reg.__getitem__(items) else: raise TypeError("Invalid argument type.") def __setitem__(self, key, value): if isinstance(key, slice): reg = self._construct_reg() reg[key.start:key.stop] = value self._deconstruct_reg(reg) elif isinstance(key, str): self._fields[key][len(self._fields[key]) - 1:0] = value if 'bit_order' in self._get_filed_config(key): new_val = BitLogic(len(self._fields[key])) for i, bit in enumerate(self._get_filed_config(key)['bit_order']): new_val[len(self._fields[key]) - 1 - i] = self._fields[key][bit] self._fields[key] = new_val elif isinstance(key, (int, long)): reg = self._construct_reg() reg[key] = value self._deconstruct_reg(reg) else: raise TypeError("Invalid argument type.") def __len__(self): return self._conf['size'] def __str__(self): fields = dict() full = dict() reg = self._construct_reg() full[self._conf['name']] = str(len(reg)) + 'b' + reg.to01() for field in self._fields: if 'repeat' in self._get_filed_config(field): for i, sub_reg in enumerate(self._fields[field]): fields[str(field) + '[' + str(i) + ']'] = str(sub_reg) else: fields[field] = str(len(self._fields[field])) + 'b' + self._fields[field].to01() if self._fields: return str([full, fields]) else: return str(full) def set(self, value): self[:] = value def write(self, size=None): """ to call start() automatically, set yaml file as follows: registers: - name : CCPD_PCB type : StdRegister hw_driver : CCPD_PCB_SPI size : 32 auto_start : True <------ add this fields: ...... """ if size is None: self._drv.set_data(self.tobytes()) else: self._drv.set_data(self.tobytes()[:size]) if "auto_start" in self._conf: if self._conf["auto_start"]: self._drv.start() def read(self): raise NotImplementedError("Not implemented") # return self._drv.get_data() def _construct_reg(self): for field in self._fields: offs = self._fields_conf[field]['offset'] if 'repeat' in self._fields_conf[field]: for i, sub_filed in enumerate(self._fields[field]): bvstart = offs - i * self._get_filed_config(field)['size'] bvstop = bvstart - len(sub_filed._construct_reg()) + 1 # self._bv[bvstart:bvstop] = sub_filed._construct_reg() self._bv.set_slice_ba(bvstart, bvstop, sub_filed._construct_reg()) else: bvsize = len(self._fields[field]) bvstart = offs bvstop = offs - bvsize + 1 # self._bv[bvstart:bvstop] = self._fields[field] self._bv.set_slice_ba(bvstart, bvstop, self._fields[field]) return self._bv def _deconstruct_reg(self, reg): for field in self._fields: offs = self._get_filed_config(field)['offset'] bvsize = len(self._fields[field]) bvstart = offs bvstop = offs - bvsize + 1 if 'repeat' in self._get_filed_config(field): raise NotImplementedError("Not implemented") else: self._fields[field] = reg[bvstart:bvstop] def _get_filed_config(self, field): return self._fields_conf[field] def tobytes(self): reg = self._construct_reg() return utils.bitarray_to_byte_array(reg) def setall(self, value): reg = self._construct_reg() reg.setall(value) self._deconstruct_reg(reg)
def test_from_value_with_size_bigger(self): bl = BitLogic.from_value(2232744712, size=70, fmt="Q") self.assertEqual(bl, bitarray("10000101000101001111101100001000"[::-1] + "0" * 38))
def test_from_value_long_long(self): if struct.calcsize("P") == 4: # 32-bit self.assertRaises(struct.error, BitLogic.from_value, 57857885568556688222588556, fmt="Q") else: bl = BitLogic.from_value(4772894553230993930 * 2, fmt="Q") self.assertEqual(bl, bitarray("1000010001111001011101001001110111010111011101011101010000010100"[::-1]))
def test_from_value_format(self): bl = BitLogic.from_value(2232744712, fmt="I") self.assertEqual(bl, bitarray("10000101000101001111101100001000"[::-1]))
def test_gpio(self): ID_CODE = BitLogic('0010') BYPASS = BitLogic('1111') DEBUG = BitLogic('1000') ret_ir = BitLogic('0101') # TEST REG INIT dev1ret = StdRegister(driver=None, conf=yaml.load(gpio_yaml)) dev1ret.init() dev1ret['F1'] = 0x1 dev1ret['F2'] = 0x2f dev1ret['F3'] = 0x2 dev1ret['F4'] = 0x17cf4 self.assertEqual(dev1ret[:], self.chip['DEV1'][:]) self.chip['DEV1']['F2'] = 0 self.assertFalse(dev1ret[:] == self.chip['DEV1'][:]) self.chip.set_configuration(init_yaml) self.assertEqual(dev1ret[:], self.chip['DEV1'][:]) self.chip['jtag'].reset() # IR CODE ret = self.chip['jtag'].scan_ir([ID_CODE] * 2) self.assertEqual(ret, [ret_ir] * 2) # ID CODE id_code = BitLogic.from_value(0x149B51C3, fmt='I') ret = self.chip['jtag'].scan_dr(['0' * 32] * 2) self.assertEqual(ret, [id_code] * 2) # BYPASS + ID CODE bypass_code = BitLogic('0') ret = self.chip['jtag'].scan_ir([ID_CODE, BYPASS]) self.assertEqual(ret, [ret_ir] * 2) ret = self.chip['jtag'].scan_dr(['0' * 32, '1']) self.assertEqual(ret, [id_code, bypass_code]) ret = self.chip['jtag'].scan_ir([BYPASS, ID_CODE]) self.assertEqual(ret, [ret_ir] * 2) ret = self.chip['jtag'].scan_dr(['1', '0' * 32]) self.assertEqual(ret, [bypass_code, id_code]) # DEBUG ret = self.chip['jtag'].scan_ir([DEBUG, DEBUG]) self.assertEqual(ret, [ret_ir] * 2) self.chip['jtag'].scan_dr(['1' * 32, '0' * 1 + '1' * 30 + '0' * 1]) ret = self.chip['jtag'].scan_dr(['0' * 32, '1' * 32]) self.assertEqual(ret, [BitLogic('1' * 32), BitLogic('0' * 1 + '1' * 30 + '0' * 1)]) ret = self.chip['jtag'].scan_dr(['0' * 32, '0' * 32]) self.assertEqual(ret, [BitLogic('0' * 32), BitLogic('1' * 32)]) # SHIT IN DEV REG/DEBUG self.chip['jtag'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]]) # GPIO RETURN dev1ret.frombytes(self.chip['gpio_dev1'].get_data()) self.assertEqual(dev1ret[:], self.chip['DEV1'][:]) self.assertFalse(dev1ret[:] == self.chip['DEV2'][:]) dev1ret.frombytes(self.chip['gpio_dev2'].get_data()) self.assertEqual(dev1ret[:], self.chip['DEV2'][:]) # JTAG RETURN ret = self.chip['jtag'].scan_dr(['0' * 32, '0' * 32]) dev1ret.set(ret[0]) self.assertEqual(dev1ret[:], self.chip['DEV1'][:]) dev1ret.set(ret[1]) self.assertEqual(dev1ret[:], self.chip['DEV2'][:]) # REPEATING REGISTER self.chip['jtag'].scan_dr([self.chip['DEV'][:]]) ret1 = self.chip['jtag'].scan_dr([self.chip['DEV'][:]]) self.chip['jtag'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]]) ret2 = self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]]) ret3 = self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]]) self.assertEqual(ret1[:], ret2[:]) self.assertEqual(ret2[:], ret3[:]) # REPEATING SETTING self.chip['jtag'].scan_dr(['1' * 32 + '0' * 32]) ret = self.chip['jtag'].scan_dr(['0' * 32 + '0' * 32]) self.chip['DEV'].set(ret[0]) self.assertEqual(self.chip['DEV'][:], BitLogic('0' * 32 + '1' * 32)) self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]]) ret = self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]]) self.chip['DEV'].set(ret[0]) self.assertEqual(self.chip['DEV'][:], self.chip['DEV1'][:] + self.chip['DEV2'][:])
def test_to_value(self): value = 12 bl = BitLogic.from_value(value, size=16, fmt="I") ret_val = bl.tovalue() self.assertEqual(ret_val, value)
class StdRegister(RegisterLayer): def __init__(self, driver, conf): super(StdRegister, self).__init__(driver, conf) self._size = conf['size'] self._fields = dict() self._bv = None self._fields_conf = dict() if 'fields' in self._conf: for field in self._conf['fields']: if field['offset'] + 1 < field['size']: raise ValueError("Register " + self._conf['name'] + ":" + field['name'] + ": Invalid offset value. Specify MSB position.") if 'repeat' in field: reg_list = [] for _ in range(field['repeat']): reg = StdRegister(None, field) reg_list.append(reg) self._fields[field['name']] = reg_list else: bv = BitLogic(field['size']) self._fields[field['name']] = bv self._fields_conf[field['name']] = field # set default if "default" in field: self[field['name']] = field['default'] self._bv = BitLogic(self._conf['size']) def init(self): super(StdRegister, self).init() self.set_configuration(self._init) def __getitem__(self, items): if isinstance(items, str): return self._fields[items] elif isinstance(items, slice): reg = self._construct_reg() return reg.__getitem__(items) else: raise TypeError("Invalid argument type.") def __setitem__(self, key, value): if isinstance(key, slice): reg = self._construct_reg() reg[key.start:key.stop] = value self._deconstruct_reg(reg) elif isinstance(key, str): self._fields[key][len(self._fields[key]) - 1:0] = value if 'bit_order' in self._get_filed_config(key): new_val = BitLogic(len(self._fields[key])) for i, bit in enumerate(self._get_filed_config(key)['bit_order']): new_val[len(self._fields[key]) - 1 - i] = self._fields[key][bit] self._fields[key] = new_val elif isinstance(key, (int, long)): reg = self._construct_reg() reg[key] = value self._deconstruct_reg(reg) else: raise TypeError("Invalid argument type.") def __len__(self): return self._conf['size'] def __str__(self): fields = dict() full = dict() reg = self._construct_reg() full[self._conf['name']] = str(len(reg)) + 'b' + str(reg[:]) for field in self._fields: if 'repeat' in self._get_filed_config(field): for i, sub_reg in enumerate(self._fields[field]): fields[str(field) + '[' + str(i) + ']'] = str(sub_reg) else: fields[field] = str(len(self._fields[field])) + 'b' + str(self._fields[field][:]) if self._fields: return str([full, fields]) else: return str(full) def set(self, value): self[:] = value def write(self, size=None): """ to call start() automatically, set yaml file as follows: registers: - name : CCPD_PCB type : StdRegister hw_driver : CCPD_PCB_SPI size : 32 auto_start : True <------ add this fields: ...... """ if size is None: self._drv.set_data(self.tobytes()) else: self._drv.set_data(self.tobytes()[:size]) if "auto_start" in self._conf: if self._conf["auto_start"]: self._drv.start() def read(self): raise NotImplementedError("Not implemented") # return self._drv.get_data() def _construct_reg(self): for field in self._fields: offs = self._fields_conf[field]['offset'] if 'repeat' in self._fields_conf[field]: for i, sub_filed in enumerate(self._fields[field]): bvstart = offs - i * self._get_filed_config(field)['size'] bvstop = bvstart - len(sub_filed._construct_reg()) + 1 # self._bv[bvstart:bvstop] = sub_filed._construct_reg() self._bv.set_slice_ba(bvstart, bvstop, sub_filed._construct_reg()) else: bvsize = len(self._fields[field]) bvstart = offs bvstop = offs - bvsize + 1 # self._bv[bvstart:bvstop] = self._fields[field] self._bv.set_slice_ba(bvstart, bvstop, self._fields[field]) return self._bv def _deconstruct_reg(self, reg): for field in self._fields: offs = self._get_filed_config(field)['offset'] bvsize = self._get_filed_config(field)['size'] bvstart = offs bvstop = offs - bvsize + 1 if 'repeat' in self._get_filed_config(field): size = self._get_filed_config(field)['size'] for i, ifield in enumerate(self._fields[field]): ifield.set(reg[bvstart - size * i:bvstop - size * i]) else: self._fields[field] = reg[bvstart:bvstop] def _get_filed_config(self, field): return self._fields_conf[field] def tobytes(self): reg = self._construct_reg() return utils.bitarray_to_byte_array(reg) def setall(self, value): reg = self._construct_reg() reg.setall(value) self._deconstruct_reg(reg) def frombytes(self, value): bl_value = BitLogic() bl_value.frombytes(array.array('B', value)[::-1].tostring()) self._deconstruct_reg(bl_value[self._conf['size']:]) def get_configuration(self): fields = dict() reg = self._construct_reg() for field in self._fields: if 'repeat' in self._get_filed_config(field): rep_field = [] for sub_reg in self._fields[field]: rep_field.append(sub_reg.get_configuration()) fields[field] = rep_field else: fields[field] = str(self._fields[field][:]) if self._fields: return fields else: return str(reg[:]) def set_configuration(self, conf): for name, value in conf.iteritems(): if name in self._fields: if 'repeat' in self._fields_conf[name]: for i, rep_val_dict in enumerate(value): for rep_name, rep_value in rep_val_dict.iteritems(): self[name][i][rep_name] = rep_value else: self[name] = value else: raise ValueError("Filed " + name + " does not exist.")
def test_from_value_with_size_smaller(self): bl = BitLogic.from_value(259, size=9, fmt="Q") self.assertEqual(bl, bitarray("100000011"[::-1]))