def __init__(self, clock): super().__init__(clock) self.ins['control'] = Bint(0) self.ins['in_1'] = Bint(0) self.ins['in_2'] = Bint(0) self.outs['zero'] = Bint(0) self.outs['out'] = Bint(0)
def __init__(self): Component.__init__(self) self.ins['addr'] = Bint(0) self.ins['write'] = Bint(0) self.ins['write_cont'] = Bint(0) self.ins['read_cont'] = Bint(0) self.outs['read'] = Bint(0) # TODO: change to out for consistency
def tick(self): super().tick() funct = self.ins['funct']() aluop = self.ins['ALUOp']() aluop0 = aluop[-1] aluop1 = aluop[-2] if not aluop: self.outs['ALUOp'] = Bint(0b0010, pad=4) elif aluop0 == '1': self.outs['ALUOp'] = Bint(0b0110, pad=4) elif aluop1 == '1': # r-type if funct == '100000': self.outs['ALUOp'] = Bint(0b0010, pad=4) elif funct == '100010': self.outs['ALUOp'] = Bint(0b0110, pad=4) elif funct == '100100': self.outs['ALUOp'] = Bint(0b0000, pad=4) elif funct == '100101': self.outs['ALUOp'] = Bint(0b0001, pad=4) elif funct == '101010': self.outs['ALUOp'] = Bint(0b0111, pad=4) elif funct == '000000': self.outs['ALUOp'] = Bint(0, pad=4) else: raise ValueError(f'Bad funct value, {funct}') else: raise ValueError(f'Bad ALUOp, {aluop}')
def tick(self): super().tick() do_write = self.ins['RegWrite']() read1 = self.ins['read_reg_1']() read2 = self.ins['read_reg_2']() writedata = self.ins['write_data']() write = self.ins['write_reg']() self.outs['read_data_1'] = Bint(self.regs[str(read1)].val) self.outs['read_data_2'] = Bint(self.regs[str(read2)].val) if do_write and write != 0: # ignore zero register writes assert str( write) in self.regs, '{} not a valid register num'.format( write) self.regs[str(write)].val = writedata
def setouts(self, RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch, ALUOp, Jump): self.outs['RegDst'] = Bint(RegDst) self.outs['ALUSrc'] = Bint(ALUSrc) self.outs['MemtoReg'] = Bint(MemtoReg) self.outs['RegWrite'] = Bint(RegWrite) self.outs['MemRead'] = Bint(MemRead) self.outs['MemWrite'] = Bint(MemWrite) self.outs['Branch'] = Bint(Branch) self.outs['ALUOp'] = Bint(ALUOp) # 2 bits self.outs['Jump'] = Bint(Jump)
def tick(self): super().tick() cont = self.ins['control']() a = self.ins['in_1']() b = self.ins['in_2']() if cont == '0000': # and self.outs['out'] = a & b elif cont == '0001': # or self.outs['out'] = a | b elif cont == '0010': # add self.outs['out'] = a + b elif cont == '0110': # sub self.outs['out'] = a - b elif cont == '0111': # slt self.outs['out'] = Bint(1) if a < b else Bint(0) self.outs['zero'] = Bint(1) if not self.outs['out'] else Bint(0)
def __init__(self): super().__init__() self.regs = makeregispile() self.ins['RegWrite'] = Bint(0) # Control->RegWrite self.ins['read_reg_1'] = Bint(0) self.ins['read_reg_2'] = Bint(0) self.ins['write_reg'] = Bint(0) # which register to write to self.ins['write_data'] = Bint(0) # data to write to write register self.outs['read_data_1'] = Bint(0) self.outs['read_data_2'] = Bint(0)
def __getitem__(self, loc): # words loc = Bint(loc) item = '' # TODO: use Bint.append() item += str(dict.get(self, loc, Bint(0, pad=8))) item += str(dict.get(self, loc + 1, Bint(0, pad=8))) item += str(dict.get(self, loc + 2, Bint(0, pad=8))) item += str(dict.get(self, loc + 3, Bint(0, pad=8))) return Bint(item)
def makeregispile(): regs = [] for r in range(0,32): write = True # special registers if r in (0,26,27): write = False regs.append(Regis(Bint(0), writable=write)) # NOTE: could use an ordered dict for some structual compression aliases = { '0' : regs[0], 'zero' : regs[0], '00000' : regs[0], '1' : regs[1], 'at' : regs[1], '00001' : regs[1], '2' : regs[2], 'v0' : regs[2], '00010' : regs[2], '3' : regs[3], 'v1' : regs[3], '00011' : regs[3], '4' : regs[4], 'a0' : regs[4], '00100' : regs[4], '5' : regs[5], 'a1' : regs[5], '00101' : regs[5], '6' : regs[6], 'a2' : regs[6], '00110' : regs[6], '7' : regs[7], 'a3' : regs[7], '00111' : regs[7], '8' : regs[8], 't0' : regs[8], '01000' : regs[8], '9' : regs[9], 't1' : regs[9], '01001' : regs[9], '10' : regs[10], 't2' : regs[10], '01010' : regs[10], '11' : regs[11], 't3' : regs[11], '01011' : regs[11], '12' : regs[12], 't4' : regs[12], '01100' : regs[12], '13' : regs[13], 't5' : regs[13], '01101' : regs[13], '14' : regs[14], 't6' : regs[14], '01110' : regs[14], '15' : regs[15], 't7' : regs[15], '01111' : regs[15], '16' : regs[16], 's0' : regs[16], '10000' : regs[16], '17' : regs[17], 's1' : regs[17], '10001' : regs[17], '18' : regs[18], 's2' : regs[18], '10010' : regs[18], '19' : regs[19], 's3' : regs[19], '10011' : regs[19], '20' : regs[20], 's4' : regs[20], '10100' : regs[20], '21' : regs[21], 's5' : regs[21], '10101' : regs[21], '22' : regs[22], 's6' : regs[22], '10110' : regs[22], '23' : regs[23], 's7' : regs[23], '10111' : regs[23], '24' : regs[24], 't8' : regs[24], '11000' : regs[24], '25' : regs[25], 't9' : regs[25], '11001' : regs[25], '26' : regs[26], 'k0' : regs[26], '11010' : regs[26], '27' : regs[27], 'k1' : regs[27], '11011' : regs[27], '28' : regs[28], 'gp' : regs[28], '11100' : regs[28], '29' : regs[29], 'sp' : regs[29], '11101' : regs[29], '30' : regs[30], 'fp' : regs[30], '11110' : regs[30], '31' : regs[31], 'ra' : regs[31], '11111' : regs[31] } return aliases
def cb(): res = Bint(0) if comp.outs[_out] is not None: res = Bint(comp.outs[_out][i:j], pad=j - i) return res
def __init__(self, initval, clock): super().__init__(clock) self.ins['in'] = Bint(initval) self.outs['out'] = Bint(initval) self.reg = Regis(Bint(initval))
def tick(self): super().tick() # self.outs['clock'] = Bint(not self.outs['clock']) self.outs['clock'] = Bint(1)
def __init__(self, inittime=time()): super().__init__() self.inittime = inittime self.period = 0.1 # in seconds self.outs['clock'] = Bint(1)
def __init__(self): super().__init__() self.ins['in_1'] = Bint(0) self.ins['in_2'] = Bint(0) self.outs['out'] = Bint(0)
def tick(self): super().tick() in1 = self.ins['in_1']() in2 = self.ins['in_2']() self.outs['out'] = Bint(in1 & in2)
def tick(self): super().tick() in_ = self.ins['in']() self.outs['out'] = Bint(in_.val * 4, pad=in_.pad + 2)
def tick(self): super().tick() in_ = self.ins['in']() self.outs['out'] = Bint(in_ + 4)
def __setitem__(self, loc, val): # words loc = Bint(loc) dict.__setitem__(self, loc, val[0:8]) dict.__setitem__(self, loc + 1, val[8:16]) dict.__setitem__(self, loc + 2, val[16:24]) dict.__setitem__(self, loc + 3, val[24:32])
def __init__(self, val=Bint(0), writable=True): self._val = val self.write = writable self.lock = False
def OLD_tick(self): super().tick() per = self.period self.outs['clock'] = Bint((self.inittime - time()) % per >= per / 2)
def __init__(self): super().__init__() self.ins['ALUOp'] = Bint(0) # TODO:rename to in for consistency self.ins['funct'] = Bint(0) self.outs['ALUOp'] = Bint(0)
def __init__(self): super().__init__() self.ins['in'] = Bint(0) self.setouts(0, 0, 0, 0, 0, 0, 0, 0, 0)