def generate_pex(self, test_module, path):
tempspice = path + test_module.name+".sp"
tempgds = path + test_module.name+".gds"
test_module.sp_write(tempspice)
test_module.gds_write(tempgds)
assert(calibre.run_drc(test_module.name,
tempgds)==0)
assert(calibre.run_lvs(test_module.name,
tempgds,
tempspice)==0)
pex_file = test_module.name+"_pex.sp"
#pex_file = "temp_pex.sp"
assert(calibre.run_pex(test_module.name,
tempgds,
tempspice,
output=path + pex_file)==0)
return path + pex_file
# Output the files for the resulting SRAM
spname = OPTS.out_path + s.name + ".sp"
print "SP: Writing to {0}".format(spname)
s.sp_write(spname)
gdsname = OPTS.out_path + s.name + ".gds"
print "GDS: Writing to {0}".format(gdsname)
s.gds_write(gdsname)
# Run Characterizer on the design
sram_file = spname
if OPTS.run_pex:
sram_file = OPTS.out_path + "temp_pex.sp"
calibre.run_pex(s.name, gdsname, spname, output=sram_file)
# geenrate verilog
import verilog
vname = OPTS.out_path + s.name + ".v"
print "Verilog: Writing to {0}".format(vname)
verilog.verilog(vname, s)
# generate LEF
import lef
lefname = OPTS.out_path + s.name + ".lef"
print "LEF: Writing to {0}".format(lefname)
lef.lef(gdsname, lefname, s)
# generate lib
import lib
def func_test(self, bank_num):
import sram
import tech
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
OPTS.check_lvsdrc = False
OPTS.use_pex = True
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="test_sram1")
OPTS.check_lvsdrc = True
OPTS.use_pex = False
tempspice = OPTS.openram_temp + "temp.sp"
tempgds = OPTS.openram_temp + "temp.gds"
s.sp_write(tempspice)
s.gds_write(tempgds)
self.assertFalse(calibre.run_drc(s.name, tempgds))
self.assertFalse(calibre.run_lvs(s.name, tempgds, tempspice))
self.assertFalse(calibre.run_pex(s.name, tempgds,
tempspice, output=OPTS.openram_temp + "temp_pex.sp"))
import sp_file
stimulus_file = OPTS.openram_temp + "stimulus.sp"
a_stimulus = sp_file.sp_file(stimulus_file)
self.write_stimulus(a_stimulus)
simulator_file = OPTS.openram_temp + "simulator.sp"
a_simulator = sp_file.sp_file(simulator_file)
self.write_simulator(a_simulator)
result_file = OPTS.openram_temp + "result"
import os
if OPTS.spice_version == "hspice":
cmd = "hspice -mt 36 -i {0} > {1} ".format(
simulator_file, result_file)
else:
cmd = "ngspice -b -i {0} > {1} ".format(
simulator_file, result_file)
os.system(cmd)
import re
sp_result = open(result_file, "r")
contents = sp_result.read()
key = "vr1"
val = re.search(
r"{0}(\s*)=(\s*)(\d*(.).*)(\s*)(from)".format(key), contents)
val = val.group(3)
value1 = float(self.convert_voltage_unit(val))
key = "vr2"
val = re.search(
r"{0}(\s*)=(\s*)(\d*(.).*)(\s*)(from)".format(key), contents)
val = val.group(3)
value2 = float(self.convert_voltage_unit(val))
self.assertTrue(round(value1) > 0.5 * tech.spice["supply_voltage"])
self.assertTrue(round(value2) < 0.5 * tech.spice["supply_voltage"])
OPTS.check_lvsdrc = True