def addAlias(row, col, srcname, destname):
gsrcname = chipdb.wire2global(row, col, db, srcname)
gdestname = chipdb.wire2global(row, col, db, destname)
pipname = f"R{row}C{col}_{srcname}_{destname}"
##print("alias", pipname)
ctx.addAlias(
name=pipname, type=destname, srcWire=gsrcname, dstWire=gdestname,
delay=ctx.getDelayFromNS(0.01))
def addAlias(row, col, srcname, destname):
gsrcname = chipdb.wire2global(row, col, db, srcname)
gdestname = chipdb.wire2global(row, col, db, destname)
pipname = f"R{row}C{col}_{srcname}_{destname}"
#print("alias", pipname)
#I don't think these are physical wires with extra delay
ctx.addAlias(name=pipname,
type=destname,
srcWire=gsrcname,
dstWire=gdestname,
delay=ctx.getDelayFromNS(0.01))
def addPip(row, col, srcname, destname):
gsrcname = chipdb.wire2global(row, col, db, srcname)
gdestname = chipdb.wire2global(row, col, db, destname)
pipname = f"R{row}C{col}_{srcname}_{destname}"
#print("pip", pipname, srcname, gsrcname, destname, gdestname)
try:
ctx.addPip(
name=pipname, type=destname, srcWire=gsrcname, dstWire=gdestname,
delay=ctx.getDelayFromNS(0.05), loc=Loc(col, row, 0))
except IndexError:
pass
#print("Wire not found", gsrcname, gdestname)
except AssertionError:
pass
def addWire(row, col, wire):
gname = chipdb.wire2global(row, col, db, wire)
#print("wire", gname)
try:
ctx.addWire(name=gname, type=wire, y=row, x=col)
except AssertionError:
pass
def addWire(row, col, wire):
gname = chipdb.wire2global(row, col, db, wire)
#print("wire", gname)
if gname in added_wires:
# print(f"Duplicate wire {gname}")
return
else:
added_wires.append(gname)
ctx.addWire(name=gname, type=wire, y=row, x=col)
def addPip(row, col, srcname, destname):
gsrcname = chipdb.wire2global(row, col, db, srcname)
gdestname = chipdb.wire2global(row, col, db, destname)
pipname = f"R{row}C{col}_{srcname}_{destname}"
#print("pip", pipname, srcname, gsrcname, destname, gdestname)
try:
# delay is crude fudge from vendor critical path
ctx.addPip(name=pipname,
type=destname,
srcWire=gsrcname,
dstWire=gdestname,
delay=wiredelay(destname),
loc=Loc(col, row, 0))
except IndexError:
pass
#print("Wire not found", gsrcname, gdestname)
except AssertionError:
pass
def tile2verilog(dbrow, dbcol, bels, pips, mod, db):
# db is 0-based, floorplanner is 1-based
row = dbrow + 1
col = dbcol + 1
aliases = db.grid[dbrow][dbcol].aliases
for dest, src in chain(pips.items(), aliases.items()):
srcg = chipdb.wire2global(row, col, db, src)
destg = chipdb.wire2global(row, col, db, dest)
mod.wires.update({srcg, destg})
mod.assigns.append((destg, srcg))
belre = re.compile(r"(IOB|LUT|DFF|BANK|CFG)(\w*)")
for bel, flags in bels.items():
typ, idx = belre.match(bel).groups()
if typ == "LUT":
val = sum(1 << f for f in flags)
name = f"R{row}C{col}_LUT4_{idx}"
lut = codegen.Primitive("LUT4", name)
lut.params["INIT"] = f"16'b{val:016b}"
lut.portmap['F'] = f"R{row}C{col}_F{idx}"
lut.portmap['I0'] = f"R{row}C{col}_A{idx}"
lut.portmap['I1'] = f"R{row}C{col}_B{idx}"
lut.portmap['I2'] = f"R{row}C{col}_C{idx}"
lut.portmap['I3'] = f"R{row}C{col}_D{idx}"
mod.wires.update(lut.portmap.values())
mod.primitives[name] = lut
elif typ == "DFF":
kind, = flags # DFF only have one flag
idx = int(idx)
port = dffmap[kind]
name = f"R{row}C{col}_{typ}E_{idx}"
dff = codegen.Primitive(kind + "E", name)
dff.portmap['CLK'] = f"R{row}C{col}_CLK{idx//2}"
dff.portmap['D'] = f"R{row}C{col}_F{idx}"
dff.portmap['Q'] = f"R{row}C{col}_Q{idx}"
dff.portmap['CE'] = f"R{row}C{col}_CE{idx//2}"
if port:
dff.portmap[port] = f"R{row}C{col}_LSR{idx//2}"
mod.wires.update(dff.portmap.values())
mod.primitives[name] = dff
elif typ == "IOB":
try:
kind, = flags.intersection(iobmap.keys())
except ValueError:
continue
portmap = db.grid[dbrow][dbcol].bels[bel].portmap
name = f"R{row}C{col}_{kind}_{idx}"
wires = set(iobmap[kind]['wires'])
ports = set(chain.from_iterable(iobmap[kind].values())) - wires
iob = codegen.Primitive(kind, name)
for port in wires:
wname = portmap[port]
iob.portmap[port] = f"R{row}C{col}_{wname}"
for port in ports:
iob.portmap[port] = f"R{row}C{col}_{port}{idx}"
for wires in iobmap[kind]['wires']:
wnames = [f"R{row}C{col}_{portmap[w]}" for w in wires]
mod.wires.update(wnames)
for direction in ['inputs', 'outputs', 'inouts']:
for wires in iobmap[kind].get(direction, []):
wnames = [f"R{row}C{col}_{w}{idx}" for w in wires]
getattr(mod, direction).update(wnames)
mod.primitives[name] = iob
gnd = codegen.Primitive("GND", "mygnd")
gnd.portmap["G"] = "VSS"
mod.primitives["mygnd"] = gnd
vcc = codegen.Primitive("VCC", "myvcc")
vcc.portmap["V"] = "VCC"
mod.primitives["myvcc"] = vcc