Python loadFrmFirmware Exemples

Exemple #1

Fichier : cosmic_fccd_auto_start.py Projet : ihumphrey/fastccd_support_ioc

import cin_register_map
import cin_functions
import time

# Power Cycle CIN to clear stale configurations
cin_functions.CINPowerDown()
cin_functions.CINPowerUp()

import getCfgFPGAStatus

cin_binary_dir = '/home/rp/PycharmProjects/fastccd_support_ioc/fastccd_support_ioc/utils/cin_binary/'
config_dir = '/home/rp/PycharmProjects/fastccd_support_ioc/fastccd_support_ioc/utils/config/'

# Configure Frame FPGA
# jj-changed to lastest fw 05/02/17 In EuXFEL bin location
cin_functions.loadFrmFirmware(cin_binary_dir + "FPGAConfig.bit")

import getFrmFPGAStatus
import setFClk125M
# import setFClk200M
import getFClkStatus

# Load Camera Timing File for 125MHz System Clock
cin_functions.loadCameraConfigFile(config_dir + "TimingConfig.txt")

print
"\nSet Trigger Mux to accept external triggers on FP Trigger Input 1 Only"
import setTrigger0  # Maps to Front Panel Trigger Input 1

# import setTriggerSW

Exemple #2

Fichier : auto_start_script.py Projet : ihumphrey/fastccd_support_ioc

#! /usr/bin/python
# -*- coding: utf-8 -*-

import cin_constants
import cin_register_map
import cin_functions
import time

cin_functions.CINPowerDown()
cin_functions.CINPowerUp()

import getCfgFPGAStatus

cin_functions.loadFrmFirmware(
    "/home/user/CVSSandbox/BINARY/CIN_1kFSCCD/top_frame_fpga.bit")

import getFrmFPGAStatus
# import setFClk "200"
# import setFClk125M
import getFClkStatus

import setFPPowerOn

time.sleep(2)  # Wait to allow visual check
import getPowerStatus

print(" ")
input("(Press Enter Key to Exit)")

Exemple #3

# Check voltages with +-.2 V ranges from getCameraPower.py

# Power Cycle CIN to clear stale configurations
from fastccd_support_ioc.utils.protection_checks import check_FOPS, check_camera_power

cin_functions.CINPowerDown()
cin_functions.CINPowerUp()

import getCfgFPGAStatus

cin_binary_dir = '/home/rp/PycharmProjects/fastccd_support_ioc/fastccd_support_ioc/utils/cin_binary/'
config_dir = '/home/rp/PycharmProjects/fastccd_support_ioc/fastccd_support_ioc/utils/config/'

# Configure Frame FPGA
# jj-changed to lastest fw 05/02/17 In EuXFEL bin location
cin_functions.loadFrmFirmware(cin_binary_dir + "FPGAConfig.bit")  # TODO: symlink to 302D

import getFrmFPGAStatus
import setFClk125M
# import setFClk200M
import getFClkStatus

# Load Camera Timing File for 125MHz System Clock
cin_functions.loadCameraConfigFile(config_dir + "TimingConfig.txt")

print("\nSet Trigger Mux to accept external triggers on FP Trigger Input 1 Only")
import setTrigger0  # Maps to Front Panel Trigger Input 1

# import setTriggerSW

# Set Exposure Time to 1ms

Exemple #4

import cin_register_map
import cin_functions
import time

# Power Cycle CIN to clear stale configurations
cin_functions.CINPowerDown()
cin_functions.CINPowerUp()

import getCfgFPGAStatus

cin_binary_dir = '/home/rp/PycharmProjects/fastccd_support_ioc/fastccd_support_ioc/utils/cin_binary/'
config_dir = '/home/rp/PycharmProjects/fastccd_support_ioc/fastccd_support_ioc/utils/config/'

# Configure Frame FPGA
# jj-changed to lastest fw 05/02/17 In EuXFEL bin location
cin_functions.loadFrmFirmware(cin_binary_dir + "top_frame_fpga.bit")

import getFrmFPGAStatus
import setFClk125M
# import setFClk200M
import getFClkStatus

# Load Camera Timing File for 125MHz System Clock
cin_functions.loadCameraConfigFile(config_dir +
                                   "20170525_125MHz_fCCD_Timing_xper.txt")

# print "\nSet Trigger Mux to accept external triggers on FP Trigger Input 1 Only"
# import setTrigger0   # Maps to Front Panel Trigger Input 1
import setTriggerSW

# Set Exposure Time to 1ms