def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if cocotb.SIM_NAME:
for test in [
run_test_mem,
run_test_dma,
run_test_dma_errors,
run_test_msi,
run_test_msix,
]:
factory = TestFactory(test)
factory.add_option(("idle_inserter", "backpressure_inserter"),
[(None, None), (cycle_pause, cycle_pause)])
factory.generate_tests()
factory = TestFactory(run_test_fifos)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
def create_matrix(func, rows, cols):
return [func(DATA_WIDTH) for row in range(rows) for col in range(cols)]
def create_a(func):
return create_matrix(func, A_ROWS, A_COLUMNS_B_ROWS)
def create_b(func):
return create_matrix(func, A_COLUMNS_B_ROWS, B_COLUMNS)
def gen_a(num_samples=NUM_SAMPLES, func=getrandbits):
"""Generate random matrix data for A"""
for _ in range(num_samples):
yield create_a(func)
def gen_b(num_samples=NUM_SAMPLES, func=getrandbits):
"""Generate random matrix data for B"""
for _ in range(num_samples):
yield create_b(func)
factory = TestFactory(test_multiply)
factory.add_option('a_data', [gen_a])
factory.add_option('b_data', [gen_b])
factory.generate_tests()
assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa'
cur_tag = (cur_tag + 1) % tag_count
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if cocotb.SIM_NAME:
factory = TestFactory(run_test_write)
factory.add_option(("idle_inserter", "backpressure_inserter"), [(None, None), (cycle_pause, cycle_pause)])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
@pytest.mark.parametrize("pcie_offset", list(range(4))+list(range(4096-4, 4096)))
@pytest.mark.parametrize("axis_pcie_data_width", [64, 128, 256, 512])
def test_pcie_us_axi_dma_wr(request, axis_pcie_data_width, pcie_offset):
dut = "pcie_us_axi_dma_wr"
module = os.path.splitext(os.path.basename(__file__))[0]
os.makedirs(out + '/illegal/hex')
if not os.path.isdir(out + '/corpus'):
os.makedirs(out + '/corpus')
date = datetime.today().strftime('%Y%m%d')
cov_log = out + '/cov_log_{}.txt'.format(date)
if (multicore or record) and not os.path.isfile(cov_log):
save_file(cov_log, 'w',
'{:<10}\t{:<10}\t{:<10}\n'.format('time', 'iter', 'coverage'))
start_time = time.time()
if not multicore:
if minimize:
factory = TestFactory(Minimize)
factory.add_option('toplevel', [toplevel])
factory.add_option('template', [template])
factory.add_option('out', [out])
factory.add_option('debug', [debug])
else:
factory = TestFactory(Run)
parser.register_option(factory)
factory.add_option('cov_log', [cov_log])
factory.add_option('start_time', [start_time])
factory.generate_tests()
else:
manager = procManager(multicore, out, date)
def size_list():
return list(range(60, 128)) + [512, 1514, 9214] + [60] * 10
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
def cycle_en():
return itertools.cycle([0, 0, 0, 1])
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("ifg", [12])
factory.add_option("enable_dic", [True, False])
factory.add_option("force_offset_start", [False, True])
factory.generate_tests()
factory = TestFactory(run_test_alignment)
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("ifg", [12])
factory.add_option("enable_dic", [True, False])
factory.add_option("force_offset_start", [False, True])
factory.generate_tests()
# cocotb-test
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = len(cocotb.top.m_axis_tdata)
byte_width = data_width // 8
return list(range(1, byte_width * 4 + 1)) + [512] + [1] * 64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
for test in [run_test_tuser_assert]:
factory = TestFactory(test)
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
@cocotb.coroutine
def run_test_single(dut, input_data):
tb = NormalizeTestbench(dut)
yield tb.initialize()
op = input_data
x, y, z = op
result = normalize_vector_operation(pack_vector(x, y, z))
yield tb.clock_input(op)
yield tb.flush_pipeline()
yield tb.clock_assert_result(unpack_vector(result))
tests = TestFactory(run_test_single)
tests.add_option('input_data', inputs)
generate_tests_for(tests)
@cocotb.test()
def pipeline_test(dut):
tb = NormalizeTestbench(dut)
yield tb.initialize()
for i in range(min(fixed_w, len(inputs))):
yield tb.clock_input(inputs[i])
yield tb.flush_pipeline()
for i in range(min(fixed_w, len(inputs))):
import operator
from cocotb.regression import TestFactory
from spinal.RiscvTester.RiscvTester import isaTestsMemory, isaTestsMulDiv, isaTestsBase, testIsa
from cocotblib.misc import cocotbXHack
from functools import reduce
cocotbXHack()
factory = TestFactory(testIsa)
factory.add_option("iHexPath", [
"../" + x for x in reduce(operator.add, [["../Pinsec/hex/dhrystone.hex"]])
])
factory.generate_tests()
return list(range(60, 128)) + [512, 1514, 9214] + [60] * 10
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
def cycle_en():
return itertools.cycle([0, 0, 0, 1])
if cocotb.SIM_NAME:
for test in [run_test_rx, run_test_tx]:
factory = TestFactory(test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("ifg", [12, 0])
factory.generate_tests()
factory = TestFactory(run_test_tx_alignment)
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("ifg", [12])
factory.generate_tests()
factory = TestFactory(run_test_rx_frame_sync)
factory.generate_tests()
# cocotb-test
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
return list(range(1, 129))
def incrementing_payload(length):
return bytes(itertools.islice(itertools.cycle(range(1, 256)), length))
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.generate_tests()
factory = TestFactory(run_test_pad)
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
try:
# Override the driver's ARLEN value, forcing a wrong one
await RisingEdge(dut.clk)
arlen = burst_length - 1 + length_delta
getattr(dut, AXI_PREFIX + '_ARLEN').value = arlen
await axim.read(address, burst_length)
raise TestFailure("Mismatch between ARLEN value ({}) and number "
"of read words ({}), but the driver did not "
"raise an exception".format(arlen, burst_length))
except AXIReadBurstLengthMismatch:
pass
single_beat = TestFactory(test_single_beat)
single_beat.add_option('driver', (AXI4Master, AXI4LiteMaster))
single_beat.add_option('address_latency', (0, ))
single_beat.add_option('data_latency', (0, ))
single_beat.generate_tests()
single_beat_with_latency = TestFactory(test_single_beat)
single_beat_with_latency.add_option('driver', (AXI4Master, ))
single_beat_with_latency.add_option('address_latency', (0, 5))
single_beat_with_latency.add_option('data_latency', (1, 10))
single_beat_with_latency.generate_tests(postfix="_latency")
incr_burst = TestFactory(test_incr_burst)
incr_burst.add_option('return_rresp', (True, False))
incr_burst.add_option('size', (None, ))
incr_burst.generate_tests()
@cocotb.coroutine
def mux2_basic_test(dut, inputs=(1, 0, 0)):
"""Test for MUX2 options."""
yield Timer(2)
I0, I1, S0 = inputs
dut.I0 = I0
dut.I1 = I1
dut.S0 = S0
if S0:
expected = I1
else:
expected = I0
yield Timer(2)
if dut.O != expected:
raise TestFailure(
'Result is incorrect for I0(%d) I1(%d) S0(%d): %s(O) != %s (expected)'\
% (I0, I1, S0, dut.O, expected))
else:
dut._log.info('I0(%d) I1(%d) S0(%d) output(%d) Ok!' %
(I0, I1, S0, dut.O))
factory = TestFactory(mux2_basic_test)
input_permutations = [(x, y, z) for x in [0, 1] for y in [0, 1]
for z in [0, 1]]
factory.add_option("inputs", input_permutations)
factory.generate_tests()
dut.update <= 0
dut.AH <= create_hash(lambda x: 0)
dut.sha_type <= sha_type
# Reset DUT
dut.reset <= 1
for _ in range(3):
await RisingEdge(dut.clk)
dut.reset <= 0
dut._log.info(f'Sha Type in main = {dut.sha_type.value}')
dut._log.info("Test update hash module")
# Feed registers
for i, h in enumerate(H_in()):
dut.AH <= h
if i == sha_iterations(sha_type) - 1:
dut.update <= 1
else:
dut.update <= 0
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
factory = TestFactory(test_hash_update)
factory.add_option('sha_type', [0,1,2,3])
factory.add_option('H_in', [random_hash_stream])
factory.generate_tests()
for k in range(QUEUE_SIZE - 1, -1, -1):
assert q.get_nowait() == k
else:
for k in range(QUEUE_SIZE):
assert q.get_nowait() == k
assert q.qsize() == 0
assert q.empty()
assert not q.full()
# underflow
with pytest.raises(QueueEmpty):
q.get_nowait()
factory = TestFactory(run_queue_nonblocking_test)
factory.add_option("queue_type", [Queue, PriorityQueue, LifoQueue])
factory.generate_tests()
@cocotb.test()
async def test_queue_contention(dut):
NUM_PUTTERS = 20
QUEUE_SIZE = 10
q = Queue(maxsize=QUEUE_SIZE)
async def putter(lst, item):
await q.put(item)
lst.append(item)
#fact.add_option("write_setup", [0, clk_t / 2])
#fact.add_option("write_hold", [clk_t / 2, clk_t])
#fact.add_option("read_setup", [clk_t, 3 * clk_t / 2])
#fact.add_option("read_hold", [clk_t / 2, clk_t])
#fact.generate_tests()
#
#fact = TestFactory(tmr_test_count)
#fact.add_option("setup", [0, clk_t / 4])
#fact.add_option("hold", [clk_t / 4, 3 * clk_t / 4])
#fact.generate_tests(prefix="partial_")
#
#fact = TestFactory(tmr_test_count)
#fact.add_option("setup", [0])
#fact.add_option("hold", [clk_t])
#fact.generate_tests(prefix="continuous_")
#fact = TestFactory(tmr_test_lapse)
#fact.add_option("write_setup", [0, clk_t / 2])
#fact.add_option("write_hold", [clk_t / 2, clk_t])
#fact.add_option("read_setup", [clk_t, 3 * clk_t / 2])
#fact.add_option("read_hold", [clk_t / 2, clk_t])
#fact.generate_tests()
fact = TestFactory(tmr_test_alarm)
#fact.add_option("setup", [0, clk_t / 2])
#fact.add_option("hold", [clk_t / 2, clk_t])
fact.add_option("lapse", [4])
fact.add_option("setup", [0])
fact.add_option("hold", [clk_t])
fact.generate_tests()
def incrementing_payload(length):
return bytes(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
# for test in [run_test, run_test_offsets]:
# factory = TestFactory(run_test)
# factory.add_option("payload_lengths", [size_list])
# factory.add_option("payload_data", [incrementing_payload])
# factory.add_option("idle_inserter", [None, cycle_pause])
# factory.add_option("backpressure_inserter", [None, cycle_pause])
# factory.generate_tests()
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
factory = TestFactory(run_test_offsets)
factory.add_option("payload_lengths", [size_list2])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
#Overwriting debug (original) with the one from env
debug = os.getenv('COCOTB_DEBUG') # None/1
driver = ImageDriver(dut)
monitor = JpegMonitor(dut)
if debug: # pragma: no cover
driver.log.setLevel(logging.DEBUG)
monitor.log.setLevel(logging.DEBUG)
stimulus = Image.open(filename)
yield driver.send(stimulus)
output = yield monitor.wait_for_recv()
if debug: # pragma: no cover
output.save(filename + "_process.jpg")
difference = compare(stimulus, output)
dut.log.info("Compressed image differs to original by %f%%" % (difference))
if difference > threshold: # pragma: no cover
raise TestFailure("Resulting image file was too different (%f > %f)" %
(difference, threshold))
tf = TestFactory(process_image)
tf.add_option(
"filename",
[os.path.join('test_images', f) for f in os.listdir('test_images')])
tf.generate_tests()
import cocotb
from cocotb.regression import TestFactory
testfactory_test_names = set()
testfactory_test_args = set()
prefix = "".join(random.choices(string.ascii_letters, k=4))
postfix = "".join(random.choices(string.ascii_letters, k=4))
async def run_testfactory_test(dut, arg1, arg2, arg3):
testfactory_test_names.add(cocotb.regression_manager._test.__qualname__)
testfactory_test_args.add((arg1, arg2, arg3))
factory = TestFactory(run_testfactory_test)
factory.add_option("arg1", ["a1v1", "a1v2"])
factory.add_option(("arg2", "arg3"), [("a2v1", "a3v1"), ("a2v2", "a3v2")])
factory.generate_tests(prefix=prefix, postfix=postfix)
@cocotb.test()
async def test_testfactory_verify_args(dut):
assert testfactory_test_args == {
("a1v1", "a2v1", "a3v1"),
("a1v2", "a2v1", "a3v1"),
("a1v1", "a2v2", "a3v2"),
("a1v2", "a2v2", "a3v2"),
}
assert testfactory_test_names == {
f"{prefix}run_testfactory_test{postfix}_{i:03}"
await ep.msi_cap.issue_msi_interrupt(k)
event = tb.rc.msi_get_event(ep.pcie_id, k)
event.clear()
await event.wait()
if cocotb.SIM_NAME:
for test in [
run_test_rc_mem,
run_test_config,
run_test_enumerate,
]:
factory = TestFactory(test)
factory.generate_tests()
factory = TestFactory(run_test_ep_mem)
factory.add_option("ep_index", range(4))
factory.generate_tests()
factory = TestFactory(run_test_p2p_dma)
factory.add_option("ep1_index", [0, 1])
factory.add_option("ep2_index", [2, 3])
factory.generate_tests()
factory = TestFactory(run_test_dma)
factory.add_option("ep_index", range(4))
factory.generate_tests()
return list(range(60, 128)) + [512, 1514] + [60]*10
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
def cycle_en():
return itertools.cycle([0, 0, 0, 1])
if cocotb.SIM_NAME:
for test in [run_test_rx, run_test_tx]:
factory = TestFactory(test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("ifg", [12])
factory.add_option("speed", [100e6, 10e6])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
((~A) & 0b11111, dut.C))
@add_doc('OP Code = 1 A-B')
@cocotb.coroutine
def subtraction(dut, A, B):
dut.OP = 1
dut.A = A
dut.B = B
yield Timer(1)
if (dut.C != ((A - B) & 0b11111)):
raise TestFailure("expected: 0x%08x acutal:0x%08x" %
(((A - B) & 0b11111), dut.C))
@add_doc('OP Code = 0 A+B')
@cocotb.coroutine
def addition(dut, A, B):
dut.OP = 0
dut.A = A
dut.B = B
yield Timer(1)
if (dut.C != A + B):
raise TestFailure("expected: 0x%08x acutal:0x%08x" % (A + B, dut.C))
factory = TestFactory(my_first_test)
factory.add_option("operation",
[addition, subtraction, invert, reduction, mix])
factory.generate_tests()
def size_list():
return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
def cycle_en():
return itertools.cycle([0, 0, 0, 1])
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("ifg", [12, 0])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
def test_axis_xgmii_rx_32(request):
output[-1][-1][signal] = output[-1][-2][signal]
for output_word in output[-1]:
# Flip TDATA and TUSER
output_word["TDATA"] ^= 2**tdata_width - 1
output_word["TUSER"] ^= 2**tuser_width - 1
scoreboard = Scoreboard(dut)
scoreboard.add_interface(axis_monitor, output)
# Write the input packets
for packet in input:
await axis_m.write(packet)
# Wait until output_tdata is empty (so, all the packets have been received)
while output:
await RisingEdge(dut.aclk)
tdata_test_factory = TestFactory(test_tdata)
tdata_test_factory.add_option('delay', (0, 1, lambda dut: randint(2, 10)))
tdata_test_factory.add_option('consecutive_transfers',
(0, 1, 5, lambda dut: randint(1, 5)))
tdata_test_factory.generate_tests()
aux_test_factory = TestFactory(test_aux)
aux_test_factory.add_option('delay', (0, 1, lambda dut: randint(2, 10)))
aux_test_factory.add_option('consecutive_transfers',
(0, 1, 5, lambda dut: randint(1, 5)))
aux_test_factory.generate_tests()
assert read_data.tdata == test_data
assert read_data.tid == cur_tag
cur_tag = (cur_tag + 1) % tag_count
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if cocotb.SIM_NAME:
factory = TestFactory(run_test_read)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
@pytest.mark.parametrize("unaligned", [0, 1])
@pytest.mark.parametrize("axi_data_width", [8, 16, 32])
def test_axi_dma_rd(request, axi_data_width, unaligned):
dut = "axi_dma_rd"
module = os.path.splitext(os.path.basename(__file__))[0]
tb = Axi4lSlaveTB(dut, exit_on_fail)
yield tb.start(clk_t)
for t in range(0, xact_nr - 1):
yield tb.rdxact(14, 0, random.getrandbits(32), 3, 0)
for e in range(0, post_cycles):
yield RisingEdge(dut.aclk)
random.seed(time.time())
clk_t = 2000
xact_nr = 3
exit_on_fail = True
fact = TestFactory(axi4ls_test_reset)
fact.add_option("clk_delay", [clk_t / 2, clk_t, 3 * clk_t / 2])
fact.add_option("reset_hold", [clk_t / 4, clk_t / 2, clk_t / 3, clk_t])
fact.add_option("post_delay", [clk_t / 4, clk_t / 2, clk_t / 3, clk_t])
fact.generate_tests()
fact = TestFactory(axi4ls_test_wrxact)
fact.add_option("addr", [0, 1, 4, 6, 8, 11])
fact.add_option("addr_delay", [0, clk_t / 2, 3 * clk_t / 4, 5 * clk_t / 4])
fact.add_option("data_delay", [0, clk_t / 2, 3 * clk_t / 4, 5 * clk_t / 4])
fact.add_option("resp_delay", [0, clk_t / 2, 3 * clk_t / 4, 5 * clk_t / 4])
fact.add_option("resp", [0])
fact.add_option("post_cycles", [0, 1, 4])
fact.generate_tests("valid_")
fact = TestFactory(axi4ls_test_wrxact)
