def testAll(dut):
""" test with eth+IPv4+TCP+Payload"""
fork(Clock(dut.clk, 6.4, 'ns').start())
dut._log.info("Running test")
dut.reset_n <= 0
dut.ethBus <= 0
dut.IPv4Bus <= 0
dut.payload_in_data <= 0
dut.tcpBus <= 0
yield ClockCycles(dut.clk, 10)
dut.reset_n <= 1
dut._log.info("end Rst")
dut.ethBus <= int.from_bytes(
raw(
Ether(src="aa:aa:aa:aa:aa:aa",
dst='11:11:11:11:11:11',
type="IPv4")), 'little')
dut.IPv4Bus <= int.from_bytes(
raw(IP(src="192.168.1.1", dst="192.168.1.2")), 'little')
dut.tcpBus <= int.from_bytes(raw(TCP(sport=80, dport=12000)), 'little')
dut.payload_in_data <= int(0xDEADBEEFDEADBEEF)
yield ClockCycles(dut.clk, 15)
yield ClockCycles(dut.clk, 1)
yield ClockCycles(dut.clk, 15)
dut._log.info("end Test")
def test_event_merger(dut):
"""Test to make sure that event_merger module is working properly.
"""
# start HW sim clock
cocotb.fork(Clock(dut.axis_aclk, PERIOD).start())
yield reset_dut(dut)
yield ClockCycles(dut.axis_aclk, START_DELAY)
# read the pkts and rank values
pkts_in, meta_in = make_pkts_meta_in()
# Attach an AXI4Stream Master to the input pkt interface
pkt_master = AXI4StreamMaster(dut, 's_axis', dut.axis_aclk)
# # Attach an AXI4StreamSlave to the output pkt interface
# pkt_slave = AXI4StreamSlave(dut, 'm_axis', dut.axis_aclk, tready_delay=BP_COUNT, idle_timeout=IDLE_TIMEOUT)
# # start reading for pkts
# pkt_slave_thread = cocotb.fork(pkt_slave.read_n_pkts(len(pkts_in), log_raw=True))
# Send pkts and metadata in the HW sim
rate = 1.0 * INGRESS_LINK_RATE * 5 / 8.0 # bytes/cycle
pkt_master_thread = cocotb.fork(
pkt_master.write_pkts(pkts_in, meta_in, rate=rate))
yield pkt_master_thread.join()
# # Wait for the pkt_slave to finish (or timeout)
# yield pkt_slave_thread.join()
# pkts_out = pkt_slave.pkts
# meta_out = pkt_slave.metadata
yield ClockCycles(dut.axis_aclk, 100)
def _receive_data(self):
while True:
# Wait for a high TVALID, if not already high
if not self.bus.TVALID.value:
yield RisingEdge(self.bus.TVALID)
# Wait either for the required number of clock cycles or for a low
# TVALID. By AXI4-Stream standard, the master should not de-assert
# TVALID until at least one transfer has been performed but, if it
# does it anyways, just re-start the wait.
if callable(self.tready_delay):
tready_high_delay = ClockCycles(self.clock,
self.tready_delay(self.bus))
else:
tready_high_delay = ClockCycles(self.clock, self.tready_delay)
trigger = yield [tready_high_delay, FallingEdge(self.bus.TVALID)]
if trigger is tready_high_delay:
self.bus.TREADY <= 1
if callable(self.consecutive_transfers):
num_cycles = self.consecutive_transfers(self.bus)
else:
num_cycles = self.consecutive_transfers
if num_cycles != 0:
yield [ClockCycles(self.clock, num_cycles),
FallingEdge(self.bus.TVALID)]
else:
yield FallingEdge(self.bus.TVALID)
self.bus.TREADY <= 0
def _monitor_recv(self):
# this coroutine's responsibility is to sample at the points
# where it's interesting in your testbench to know what the input was,
# presumably because it'll have an effect on expected output.
# sometimes that's just every clockcycle, but for uarts, it's often
# once per baud period, when you know you're receiving / transmitting
yield Timer(1)
while True:
if self.receiving == False:
# if we're not receiving, we need to check for receiving every reset cycle
yield RisingEdge(self.clock)
vec = self.rx
self.log.debug("value of rx is %s while not receiving" % vec)
if self.reset_n is not None and self.reset_n == 0:
self._recv({"vec": vec, "reset": True})
#if presumably receiving a character
elif vec == 0:
self.receiving = True
self.count = 0
#start us out sampling once per period, with a half period delay
yield ClockCycles(self.clock, self.baud / 2)
#we want to sample here to verify it wasn't a glitch falling edge
self._recv({"vec": vec, "reset": False})
else:
# wait another period, putting us into actual character bits
yield ClockCycles(self.clock, self.baud)
vec = self.rx
self.log.debug("value of rx is %s while receiving" % vec)
self._recv({"vec": vec, "reset": False})
self.count = self.count + 1
if self.count == 9: #is a magic number necessary?
self.receiving = False
def test_free_list_fifo(dut):
"""Test free_list_fifo module
"""
cocotb.fork(Clock(dut.clk, PERIOD).start())
# Pulse reset
cocotb.log.info("Resetting DUT")
dut.reset = 1
yield ClockCycles(dut.clk, 10)
dut.reset = 0
cocotb.log.info("Out of reset")
dut.din = 0
dut.wr_en = 0
dut.rd_en = 0
# wait for reset to complete
while dut.reset_done == 0:
yield FallingEdge(dut.clk)
# print values in FIFO
cocotb.log.info("-----------------------")
cocotb.log.info("depth = {}".format(dut.fifo.fifo.depth.value.integer))
cocotb.log.info("-----------------------")
dut.rd_en = 1
# wait for empty to be asserted
yield RisingEdge(dut.empty)
dut.rd_en = 0
yield ClockCycles(dut.clk, 10)
def readyChange(dut):
tb = deparser_TB(dut)
yield tb.async_rst()
dut._log.info("Running test")
pkt = []
pkt.append(Ether(src="aa:aa:aa:aa:aa:aa",
dst='11:11:11:11:11:11',
type="IPv4") / IP(
src="192.168.1.1",
dst="192.168.1.2") / TCP(
sport=80,
dport=12000))
pkt.append(Ether(src="aa:aa:aa:ba:aa:aa",
dst='11:11:11:21:11:11',
type="IPv4") / IP(
src="192.188.1.1",
dst="192.158.1.2") / TCP(
sport=5,
dport=7))
for p in pkt:
tb.set_PHV(p)
nbCycle = int(len(raw(p))/(len(dut.packet_out_tdata)/8))
dut.packet_out_tready.value =1
yield ClockCycles(dut.clk, 1)
dut.en_deparser.value =1
yield ClockCycles(dut.clk, 1)
dut.en_deparser.value =0
for i in range(nbCycle * 2 + 8):
dut.packet_out_tready.value =1
yield ClockCycles(dut.clk, 1)
dut.packet_out_tready.value =0
yield ClockCycles(dut.clk, 1)
def test_axis_pkt_generator(dut):
"""Test to make sure that axis_pkt_generator module is working properly.
"""
# start HW sim clock
cocotb.fork(Clock(dut.axis_aclk, PERIOD).start())
yield reset_dut(dut)
yield ClockCycles(dut.axis_aclk, START_DELAY)
# Attach an AXI4StreamSlave to the output pkt interface
pkt_slave = AXI4StreamSlave(dut,
'm_axis',
dut.axis_aclk,
tready_delay=BP_COUNT,
idle_timeout=IDLE_TIMEOUT)
# start reading for pkts
pkt_slave_thread = cocotb.fork(
pkt_slave.read_n_pkts(NUM_PKTS, log_raw=True))
dut.gen_packet <= 1
yield ClockCycles(dut.axis_aclk, NUM_PKTS)
dut.gen_packet <= 0
# Wait for the pkt_slave to finish (or timeout)
yield pkt_slave_thread.join()
pkts_out = pkt_slave.pkts
meta_out = pkt_slave.metadata
yield ClockCycles(dut.axis_aclk, 20)
print 'len(pkts_out) = {}'.format(len(pkts_out))
def tst_1insert_1read_alternate3C(dut):
cocotb.fork(Clock(dut.clk, 6.4, 'ns').start())
tb = axistream_fifo_TB(dut)
yield tb.async_rst()
dut.stream_out_tready <= 1
for i in range(4):
tb.stream_in.append(456+i)
yield ClockCycles(dut.clk, 3)
yield ClockCycles(dut.clk, 25)
def back_preassure_manager(dut, timeout):
count = 0
print "In back preassure manager"
yield ClockCycles(dut.clk, timeout)
print "Go High!"
dut.back_preassure <= 1
yield ClockCycles(dut.clk, 10)
print "Go Low"
dut.back_preassure <= 0
def reset(dut):
"""
Resets the testbench, having reset active LOW.
"""
dut.reset_n <= 1
yield ClockCycles(dut.clock, 10)
dut.reset_n <= 0
yield ClockCycles(dut.clock, 10)
dut.reset_n <= 1
def reset(dut):
"""
Resets the testbench, assuming reset is active LOW
"""
dut.reset_n <= 1
yield ClockCycles(dut.clock, 10)
dut.reset_n <= 0
yield ClockCycles(dut.clock, 10)
dut.reset_n <= 1
def reset(self):
"""Reset DUT."""
self.dut.reset = 1
self.dut.usb_d_p = 1
self.dut.usb_d_n = 0
self.address = 0
yield ClockCycles(self.dut.clk48_host, 50, rising=True)
self.dut.reset = 0
yield ClockCycles(self.dut.clk48_host, 50, rising=True)
def tst_AXI4STDriver(dut):
cocotb.fork(Clock(dut.clk, 6.4, 'ns').start())
tb = axistream_fifo_TB(dut)
yield tb.async_rst()
yield ClockCycles(dut.clk, 1)
# data setup
dut._log.setLevel(logging.INFO)
tb.insertContinuousBatch(700, 5)
tb.stream_in.append(895, tlast=1)
# test
dut.stream_out_tready <= 1
yield RisingEdge(dut.stream_out_tvalid)
yield ClockCycles(dut.clk, 1)
dut.stream_out_tready <= 0
yield ClockCycles(dut.clk, 150)
dut.stream_out_tready <= 1
yield ClockCycles(dut.clk, 4)
dut.stream_out_tready <= 0
yield ClockCycles(dut.clk, 2)
dut.stream_out_tready <= 1
result = yield tb.stream_out.wait_for_recv()
dut._log.debug("valeur recu : {}".format(result.integer))
yield ClockCycles(dut.clk, 1)
dut.stream_out_tready <= 0
yield ClockCycles(dut.clk, 3)
dut.stream_out_tready <= 1
while dut.stream_out_tlast == 0:
result = yield tb.stream_out.wait_for_recv()
dut._log.debug("valeur recu : {}".format(result.integer))
yield ClockCycles(dut.clk, 1)
yield ClockCycles(dut.clk, 10)
def tst_AXI4STScoreboard(dut):
"""
test of scoreboard
"""
cocotb.fork(Clock(dut.clk, 6.4, 'ns').start())
tb = axistream_fifo_TB(dut)
yield tb.async_rst()
tb.stream_in.append(5)
dut.stream_out_tready <= 0
yield ClockCycles(dut.clk, 20)
dut.stream_out_tready <= 1
yield ClockCycles(dut.clk, 10)
def tst_1packet(dut):
cocotb.fork(Clock(dut.clk, 6.4, 'ns').start())
tb = axistream_fifo_TB(dut)
yield tb.async_rst()
pkt = Ether(src="aa:aa:aa:aa:aa:aa", dst='11:22:33:44:55:66',
type="IPv4") / IP(src="192.168.1.1", dst="192.168.1.2") / TCP(
sport=80, dport=12000) / "DEADBEEFHHHH"
tb.send(pkt)
dut.stream_out_tready <= 0
yield ClockCycles(dut.clk, 10)
dut.stream_out_tready <= 1
yield ClockCycles(dut.clk, 80)
def test_input_arbiter(dut):
"""Test to make sure that input_arbiter module is working properly.
"""
# start HW sim clock
cocotb.fork(Clock(dut.axis_aclk, PERIOD).start())
yield reset_dut(dut)
yield ClockCycles(dut.axis_aclk, START_DELAY)
# create the pkts and metadata
pkts_in_0, meta_in_0 = make_pkts_meta_in(0)
pkts_in_1, meta_in_1 = make_pkts_meta_in(1)
pkts_in_2, meta_in_2 = make_pkts_meta_in(2)
# Attach an AXI4Stream Master to the input pkt interface
pkt_master_0 = AXI4StreamMaster(dut, 's_axis_0', dut.axis_aclk)
pkt_master_1 = AXI4StreamMaster(dut, 's_axis_1', dut.axis_aclk)
pkt_master_2 = AXI4StreamMaster(dut, 's_axis_2', dut.axis_aclk)
# Attach an AXI4StreamSlave to the output pkt interface
pkt_slave = AXI4StreamSlave(dut,
'm_axis',
dut.axis_aclk,
tready_delay=BP_COUNT,
idle_timeout=IDLE_TIMEOUT)
# start reading for pkts
pkt_slave_thread = cocotb.fork(
pkt_slave.read_n_pkts(3 * len(pkts_in_0), log_raw=True))
# Send pkts and metadata in the HW sim
rate = 1.0 * INGRESS_LINK_RATE * 5 / 8.0 # bytes/cycle
pkt_master_thread_0 = cocotb.fork(
pkt_master_0.write_pkts(pkts_in_0, meta_in_0, rate=rate))
pkt_master_thread_1 = cocotb.fork(
pkt_master_1.write_pkts(pkts_in_1, meta_in_1, rate=rate))
pkt_master_thread_2 = cocotb.fork(
pkt_master_2.write_pkts(pkts_in_2, meta_in_2, rate=rate))
yield pkt_master_thread_0.join()
yield pkt_master_thread_1.join()
yield pkt_master_thread_2.join()
# Wait for the pkt_slave to finish (or timeout)
yield pkt_slave_thread.join()
pkts_out = pkt_slave.pkts
meta_out = pkt_slave.metadata
yield ClockCycles(dut.axis_aclk, 20)
print 'len(pkts_out) = {}'.format(len(pkts_out))
def tst_insert_read(dut):
""" expected output : 5 6 7 8 9 895
"""
cocotb.fork(Clock(dut.clk, 6.4, 'ns').start())
tb = axistream_fifo_TB(dut)
yield tb.async_rst()
tb.insertContinuousBatch(5, 5)
tb.stream_in.append(895, tlast=1)
dut.stream_out_tready <= 0
yield ClockCycles(dut.clk, 20)
dut.stream_out_tready <= 1
while dut.stream_out_tlast == 0:
yield ClockCycles(dut.clk, 1)
yield ClockCycles(dut.clk, 10)
def WrongPackets(dut):
tb = deparser_TB(dut)
yield tb.async_rst()
dut._log.info("Running test")
pkt = []
pkt.append(IPv6())
for p in pkt:
tb.set_PHV(p)
nbCycle = int(len(raw(p)) / (len(dut.packet_out_tdata) / 8))
dut.packet_out_tready <= 1
yield ClockCycles(dut.clk, 1)
dut.en_deparser <= 1
yield ClockCycles(dut.clk, 1)
dut.en_deparser <= 0
yield ClockCycles(dut.clk, nbCycle + 5)
def tst_insert_read_instant(dut):
cocotb.fork(Clock(dut.clk, 6.4, 'ns').start())
tb = axistream_fifo_TB(dut)
yield tb.async_rst()
tb.insertContinuousBatch(25, 90)
dut.stream_out_tready <= 1
yield ClockCycles(dut.clk, 50)
def reset_dut(dut):
# Reset the DUT
dut._log.debug("Resetting DUT")
dut.axis_resetn <= 0
yield ClockCycles(dut.axis_aclk, 10)
dut.axis_resetn <= 1
dut._log.debug("Out of reset")
def tst_1hugeInteger_1read(dut):
cocotb.fork(Clock(dut.clk, 6.4, 'ns').start())
tb = axistream_fifo_TB(dut)
yield tb.async_rst()
tb.stream_in.append(456789745647989)
dut.stream_out_tready <= 1
yield ClockCycles(dut.clk, 10)
def Wavedrom_test(dut):
# Setting up clocks
clk_100MHz = Clock(dut.clk, c_CLK_PERIOD, units='ns')
cocotb.fork(clk_100MHz.start(start_high=False))
axi_aclk_100MHz = Clock(dut.axi_aclk, c_CLK_PERIOD, units='ns')
cocotb.fork(axi_aclk_100MHz.start(start_high=False))
# AXI-Lite Master object
axil_m = AXI4LiteMaster(dut, "s_axi", dut.axi_aclk)
# Setting init values
dut.reset <= 1
dut.Zybo_Example_sw_in <= 4
dut.Zybo_Example_bt_in <= 0
dut.axi_aresetn <= 0
# Wait one cycle and deactivate resets
yield Timer(c_CLK_PERIOD, units='ns')
dut.reset <= 0
dut.axi_aresetn <= 1
yield Timer(c_CLK_PERIOD, units='ns')
# AXI-Lite write
yield axil_m.write(c_BASEADDRESS+c_COUNT_OFFSET, 0x00000001)
yield Timer(c_CLK_PERIOD, units='ns')
# Wavedrom
args = [dut.Zybo_Example_sw_in, dut.Zybo_Example_leds_out, dut.Zybo_Example_leds_rgb_out]
with trace(*args, clk=dut.clk) as waves:
yield ClockCycles(dut.clk, 12)
dut._log.info(waves.dumpj(header = {'text':'WaveDrom example', 'tick':0}))
waves.write('wavedrom.json', header = {'tick':0}, config = {'hscale':3})
def tst_1insert_1read(dut):
cocotb.fork(Clock(dut.clk, 6.4, 'ns').start())
tb = axistream_fifo_TB(dut)
yield tb.async_rst()
tb.stream_in.append(456)
dut.stream_out_tready <= 1
yield ClockCycles(dut.clk, 10)
def tst_1LongPacket(dut):
cocotb.fork(Clock(dut.clk, 6.4, 'ns').start())
tb = axistream_fifo_TB(dut)
yield tb.async_rst()
pkt = Ether(src="aa:aa:aa:aa:aa:aa", dst='11:22:33:44:55:66',
type="IPv4") / IP(src="192.168.1.1", dst="192.168.1.2") / TCP(
sport=80, dport=12000) / """DEADBEEF Packet vraiment long
pour remplir une fifo cela est très intéressant et
devrais permettre de tester le bon fonctionnement
d'une transaction. On envoie plusieurs fois ce paquet pour
remplir la FIFO"""
for i in range(45):
tb.stream_in.append(pkt)
dut.stream_out_tready <= 0
yield ClockCycles(dut.clk, 1024)
dut.stream_out_tready <= 1
yield ClockCycles(dut.clk, 2048)
def disconnect(self):
"""Simulate device disconnect, both lines pulled low."""
# Detached - pulldowns on host side
self.dut.usb_d_p = 0
self.dut.usb_d_n = 0
yield ClockCycles(self.dut.clk48_host, 10)
# Device address should have reset
self.address = 0
def rcv_char(self, char):
shift = (ord(char) * 2) + 2**9
self.dut._log.info("receiving char %s (%x) as %x" %
(char, ord(char), shift))
yield RisingEdge(self.dut.clk)
for i in range(10):
self.dut.i_rx <= shift % 2
shift = shift >> 1
yield ClockCycles(self.dut.clk, int(self.dut.BAUD))
def tst_empty(dut):
""" This function test the comportement of the FIFO when we empty it
"""
cocotb.fork(Clock(dut.clk, 6.4, 'ns').start())
yield async_rst(dut)
yield ClockCycles(dut.clk, 10)
dut.stream_in_tvalid <= 1
for i in range(512):
dut.stream_in_tdata <= 5+i
yield ClockCycles(dut.clk, 1)
dut.stream_in_tvalid <= 0
yield ClockCycles(dut.clk, 1)
dut._log.info("debut test lecture")
dut.stream_out_tready <= 1
for i in range(600):
yield ClockCycles(dut.clk, 1)
dut.stream_out_tready <= 0
yield ClockCycles(dut.clk, 15)
def reset_dut(dut):
# Reset the DUT
dut._log.debug("Resetting DUT")
dut.axis_resetn <= 0
yield ClockCycles(dut.axis_aclk, 10)
dut.axis_resetn <= 1
dut.m_axis_tready <= 0
dut.gen_packet <= 0
dut._log.debug("Out of reset")
def tst_insert(dut):
""" Only write into the fifo
"""
cocotb.fork(Clock(dut.clk, 6.4, 'ns').start())
tb = axistream_fifo_TB(dut)
yield tb.async_rst()
tb.insertContinuousBatch(5, 5)
tb.stream_in.append(895, tlast=1)
dut.stream_out_tready <= 0
yield ClockCycles(dut.clk, 10)
def payload(dut):
tb = deparser_TB(dut)
yield tb.async_rst()
dut._log.info("Running test")
pkt = []
pkt.append((Ether(src="aa:aa:aa:aa:aa:aa",
dst='11:11:11:11:11:11',
type="IPv4") / IP(
src="192.168.1.1",
dst="192.168.1.2") / TCP(
sport=80,
dport=12000) / "PAYLOAD TEST",
"PAYLOAD TEST"))
pkt.append((Ether(src="aa:aa:aa:aa:aa:aa",
dst='11:11:11:11:11:11',
type="IPv4") / IP(
src="192.168.1.1",
dst="192.168.1.2") / TCP(
sport=80,
dport=12000) / "PAYLOAD TEST FUL",
"PAYLOAD TEST FUL"))
pkt.append((Ether(src="aa:aa:aa:aa:aa:aa",
dst='11:11:11:11:11:11',
type="IPv4") / IP(
src="192.168.1.1",
dst="192.168.1.2") / TCP(
sport=80,
dport=12000) / "PAYLOAD2 TEST FULL",
"PAYLOAD2 TEST FULL"))
for pt in pkt:
p = pt[0]
tb.set_PHV(p, BinaryValue(bytes("PAYLOAD TEST", 'utf-8')))
tb.payload_in.append(pt[1])
nbCycle = int(len(raw(p))/(len(dut.packet_out_tdata)/8))
dut.packet_out_tready.value =1
yield ClockCycles(dut.clk, 1)
dut.en_deparser.value =1
yield ClockCycles(dut.clk, 1)
dut.en_deparser.value =0
yield [RisingEdge(dut.packet_out_tlast),
ClockCycles(dut.clk, nbCycle + 10)]
yield ClockCycles(dut.clk, 10)
