def _read(self, address, length=1, mem_device=False): yield (self.comm_lock.acquire()) #print "_Read Acquire Lock" data_index = 0 self.dut.in_ready <= 0 self.dut.out_ready <= 0 self.response = Array('B') yield (self.wait_clocks(10)) if (mem_device): self.dut.in_command <= 0x00010002 else: self.dut.in_command <= 0x00000002 self.dut.in_data_count <= length self.dut.in_address <= address self.dut.in_data <= 0 yield (self.wait_clocks(1)) self.dut.in_ready <= 1 yield FallingEdge(self.dut.master_ready) yield (self.wait_clocks(1)) self.dut.in_ready <= 0 yield (self.wait_clocks(1)) self.dut.out_ready <= 1 while data_index < length: #self.dut.log.info("Waiting for master to assert out enable") yield RisingEdge(self.dut.out_en) yield (self.wait_clocks(1)) self.dut.out_ready <= 0 timeout_count = 0 data_index += 1 value = self.dut.out_data.value.get_value() self.response.append(0xFF & (value >> 24)) self.response.append(0xFF & (value >> 16)) self.response.append(0xFF & (value >> 8)) self.response.append(0xFF & value) yield (self.wait_clocks(1)) self.dut.out_ready <= 1 if self.dut.master_ready.value.get_value() == 0: yield RisingEdge(self.dut.master_ready) yield (self.wait_clocks(10)) self.comm_lock.release() raise ReturnValue(self.response)
async def ConfigChainTestFull(dut): # = = = = = = = Get Design Variable = = = = = = = = = = = = = = = = = PConf = getConfig() clk = getFromPinAlias(dut, "clk") prog_clk = getFromPinAlias(dut, "prog_clk") test_en = getFromPinAlias(dut, "test_en") ccff_head = getFromPinAlias(dut, "ccff_head") ccff_tail = getFromPinAlias(dut, "ccff_tail") PCLK_PERIOD = 10 # in nanoseconds # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = clk <= 0 # Disable prog clock pclock = Clock(prog_clk, PCLK_PERIOD * 0.5, units="ns") cocotb.fork(pclock.start()) # Start the clock # Clock Preamble Ticks 2 await ClockCycles(prog_clk, 2) # Pass 1 bit logic to CCFF chain ccff_head <= 1 await FallingEdge(prog_clk) ccff_head <= 0 # Check CCFF_tail of each module in sequence CCFFChain = filter(lambda x: not "grid_io" in x, CreateCCFFChain()) try: start_ccff_time = get_sim_time(units='ns') for ModuleName in CCFFChain: InstPtr = eval(f"dut.fpga_core_uut.{ModuleName}.ccff_tail") # Wait for tick start_time_ns = get_sim_time(units='ns') await with_timeout(FallingEdge(InstPtr), 200 * PCLK_PERIOD, 'ns') edge_time_ns = get_sim_time(units='ns') # Verify CLKTick = math.ceil((edge_time_ns - start_time_ns) / PCLK_PERIOD) dut._log.info(f"Signal received at {ModuleName} at {CLKTick}") if (CLKTick != 8): TestFailure( f"Expected 8 ticks on module {ModuleName} received {CLKTick}" ) end_ccff_time = get_sim_time(units='ns') await ClockCycles(prog_clk, 10) TotalClock = math.ceil((end_ccff_time - start_ccff_time) / PCLK_PERIOD) dut._log.info(f"Simulation Finished in clocks {TotalClock}") except SimTimeoutError: raise TestFailure(f"Failed to receive signal on {ModuleName}")
def simple_test(dut): cnpt = ChisNesPadTest(dut) yield cnpt.reset() yield Timer(1, units="us") dut.io_data_ready <= 1 yield RisingEdge(dut.io_data_valid) vread = int(dut.io_data_bits) if vread != cnpt.reg_init_value: msg = ("Wrong value read {:04X}, should be {:04X}".format( vread, cnpt.reg_init_value)) dut.log.error(msg) raise TestError(msg) cnpt.log.info("Value read {:04X}".format(vread)) yield FallingEdge(dut.io_data_valid) dut.io_data_ready <= 0 yield Timer(1, units="us")
def send_cmd(self, cmd): """ Transmit a command, we will calculate the CRC and append it """ crc7 = sdio_utils.crc7_gen(number=cmd[47:8].integer) cmd[7:1] = BinaryValue(value=crc7, bits=7, bigEndian=False).integer self.log.debug("SDIO host sending CMD%d: 'b%s" % (cmd[45:40].integer, cmd.binstr)) self.bus.cmd_coco_dir <= 1 for x in range(47, -1, -1): # Now shift this out bit by bit, host sends on falling edge yield FallingEdge(self.clock) self.bus.cmd_coco_out <= cmd[x].integer if x == 0: # Deassert the output enable onto the bus on the final bit self.bus.cmd_coco_dir <= 0
def arbitration(self): while True: yield FallingEdge(self.dut.clk) if self.nextPort == -1: if self.previousPort < 1 and int( self.dut.arbiterRoundRobinInputs_1_valid) == 1: self.nextPort = 1 elif self.previousPort < 2 and int( self.dut.arbiterRoundRobinInputs_2_valid) == 1: self.nextPort = 2 elif int(self.dut.arbiterRoundRobinInputs_0_valid) == 1: self.nextPort = 0 elif int(self.dut.arbiterRoundRobinInputs_1_valid) == 1: self.nextPort = 1 elif int(self.dut.arbiterRoundRobinInputs_2_valid) == 1: self.nextPort = 2
def write_fifo_prog(dut, clk, prog_full, max_delay=5, write_random_data=False): """ Write to a FIFO to validate the programmable full flag. Before writing wait between 0 and max_delay cycles. """ fifo_wrcnt = 0 prog_cnt = 0 while True: # insert random wait before the next write wr_delay = random.randint(0, max_delay) dut._log.debug("WRITE: Wait for %d clock cycles" % (wr_delay)) for _ in range(wr_delay): yield RisingEdge(clk) # make sure that the full signal is stable before checking for it yield FallingEdge(clk) # return once the FIFO has been filled if dut.full.value: dut._log.info("WRITE: FIFO full. %d words written. prog_cnt: %d" % (fifo_wrcnt, prog_cnt)) # check if prog_full works correctly if prog_cnt > prog_full: raise TestFailure("Number of words written after prog_full: %d, prog_full set to: %d" % (prog_cnt, prog_full)) return else: # generate and write data, keep track of it for checking if write_random_data: data = random.getrandbits(dut.WIDTH.value.integer) else: data = fifo_wrcnt % (2 ** dut.WIDTH.value.integer) dut.din <= data _fifo_data.append(data) dut.wr_en <= 1 # count number of words written after prog_full has been raised if dut.prog_full.value: prog_cnt += 1 yield RisingEdge(clk) dut.wr_en <= 0 fifo_wrcnt += 1 dut._log.debug("WRITE: Wrote word %d to FIFO, value 0x%x" % (fifo_wrcnt, data))
def id_stage_test(dut): """ID_STAGE TEST""" for i in range(0, 31): sim_rf.append(0) cocotb.fork(Clock(dut.clk, 10).start()) pc = 0 for i in range(0, iterations): random.seed(13) ex_data = random.randint(0, 0x7FFFFFFF) mem_data = random.randint(0, 0x7FFFFFFF) wb_data = random.randint(0, 0x7FFFFFFF) bypass_s = random.randint(0, 3) bypass_t = random.randint(0, 3) fb_addr = random.randint(1, 31) fb_data = random.randint(0, 0x7FFFFFFF) sim_rf[fb_addr] = fb_data pc += 4 inst = 0 rs = random.randint(0, 31) # RS rt = random.randint(0, 31) # RT rd = random.randint(0, 31) # RD inst = rs inst = (inst << 5) + rt inst = (inst << 5) + rd inst <<= 5 # funct inst <<= 6 # funct dut.reset = 0 dut.stage_reset = 0 dut.we = 1 dut.ctrl_rs = bypass_s dut.ctrl_rt = bypass_t dut.ex_data = ex_data dut.mem_data = mem_data dut.wb_data = wb_data dut.instruction = 0 dut.pc_next = pc dut.reg_addr = fb_addr dut.reg_data = fb_data yield Timer(6) yield FallingEdge(dut.clk) real_s = {0: sim_rf[rs], 1: ex_data, 2: mem_data, 3: wb_data} real_d = {0: sim_rf[rt], 1: ex_data, 2: mem_data, 3: wb_data} if real_s[bypass_s] != dut.data_s: print bypass_s, real_s[ bypass_s], dut.data_s #, dut.wb_data, dut.ctrl_rs raise TestFailure("Wrong s readport")
def write(self, address, data=None, mem_device=False): yield (self.comm_lock.acquire()) # print "Write Acquired Lock" data_count = len(data) / 4 #print "data count: %d" % data_count yield (self.wait_clocks(1)) if data_count == 0: raise NysaCommError("Length of data to write is 0!") data_index = 0 timeout_count = 0 #self.dut.log.info("Writing data") self.dut.in_address <= address if (mem_device): self.dut.in_command <= 0x00010001 else: self.dut.in_command <= 0x00000001 self.dut.in_data_count <= data_count while data_index < data_count: self.dut.in_data <= (data[data_index ] << 24) | \ (data[data_index + 1] << 16) | \ (data[data_index + 2] << 8 ) | \ (data[data_index + 3] ) self.dut.in_ready <= 1 #self.dut.log.info("Waiting for master to deassert ready") yield FallingEdge(self.dut.master_ready) yield (self.wait_clocks(1)) data_index += 1 timeout_count = 0 #self.dut.log.info("Waiting for master to be ready") self.dut.in_ready <= 0 yield RisingEdge(self.dut.master_ready) yield (self.wait_clocks(1)) self.response = Array('B') value = self.dut.out_data.value.get_value() self.response.append(0xFF & (value >> 24)) self.response.append(0xFF & (value >> 16)) self.response.append(0xFF & (value >> 8)) self.response.append(0xFF & value) yield (self.wait_clocks(10)) self.comm_lock.release()
def simulator_signal_triggers(dut): """Playing with the Simulator Signals Triggers""" cocotb.fork(Clock(dut.clk_i, 2).start()) yield reset(dut) # for i in range(4): yield RisingEdge(dut.clk_i) print_fired(dut, "RisingEdge") for i in range(4): yield FallingEdge(dut.clk_i) print_fired(dut, "FallingEdge") for i in range(4): yield Edge(dut.clk_i) print_fired(dut, "Edge") for i in range(4): yield ClockCycles(dut.clk_i, 3) print_fired(dut, "ClockCycle")
def send_data(self, out_clk_rate=2, end_zeros=10, offset=0): """ Actions: - Send (drive) the data from input flow - Control in/out strobes - Monitor the output flow - Return the results from input and output in ndarrays as self.data_in and self.data_out Args: - out_clk_rate: rate between clock frequency and stb_out frequency. The greater this variable the slower the simulation. - end_zeros: number of zeros to be sent after sending the actual data in order to retrieve the remaining data - offset: offset to start the output data added in order to get a proportional length between input and output """ dut = self.dut params = self.params in_clk_rate = out_clk_rate * params.rate input_index = 0 data_out = [] data_in = [] data = self.quantizer(params.data, params.WIDTH).tolist() len_data = len(data) for i in range((len_data + end_zeros) * params.rate * out_clk_rate): yield FallingEdge(dut.clk) dut.stb_in = i % in_clk_rate == 0 dut.stb_out = i % out_clk_rate == 0 if dut.stb_out == 1: data_out.append(dut.data_out.value.signed_integer) if dut.stb_in == 1: if input_index < len_data: dut.data_in.value = self.set_data(data[input_index]) else: dut.data_in = self.set_data(0) input_index += 1 data_in.append(dut.data_in.value.signed_integer) self.data_in = np.array(data_in[:len_data]) self.data_out = np.array(data_out[offset:params.rate * len_data + offset])
def ex_stage_branch(dut): """EX_STAGE BRANCH OPERATION""" cocotb.fork(Clock(dut.clk, 10).start()) for i in range(0, iterations): immediate = random.randint(-10000, +10000) pc_next = random.randint(0, 0x0FFFFFFF) branchtype = random.randint(4, 5) # BEQ, BNE data_s = random.randint(0, 0x7FFFFFFF) data_t = random.randint(0, 0x7FFFFFFF) dut.we = 1 dut.reset = 0 dut.alu_s = 0 dut.alu_t = 0 dut.alu_op = 1 dut.dst_reg = 0 dut.is_link = 0 dut.is_jump = 0 dut.dst_jump = 0 dut.pc_jump = 0 dut.pc_next = pc_next dut.data_s = data_s dut.data_t = data_t dut.data_c0 = 0 dut.opcode = branchtype dut.funct = 0 dut.reg_s = 0 dut.reg_t = 0 dut.reg_d = 0 dut.is_branch = 1 dut.mem_read = 0 dut.mem_write = 0 dut.mem_type = 0 dut.mem_to_reg = 0 dut.reg_write = 0 dut.immediate = immediate yield Timer(6) yield FallingEdge(dut.clk) branch = pc_next + (immediate << 2) if branch & 0xFFFFFFFF != int(dut.pc_branch): raise TestFailure("pc_branch: %d, Wrong pc_branch: %d" % (branch, int(dut.pc_branch))) simulz = (data_s - data_t) == 0 simulz = not simulz if branchtype == 5 else simulz if simulz != int(dut.alu_zero): raise TestFailure("Wrong branch alu_zero")
def _monitor_recv(self): """Watch the pins and reconstruct transactions. We monitor on falling edge to support post synthesis simulations """ # Avoid spurious object creation by recycling clkedge = RisingEdge(self.clock) falledge = FallingEdge(self.clock) rdonly = ReadOnly() def valid(): if hasattr(self.bus, "tready"): return self.bus.tvalid.value and self.bus.tready.value return self.bus.tvalid.value # NB could yield on valid here more efficiently? while True: yield falledge yield rdonly isValid = valid() self.log.debug("validity : {}".format(isValid)) if isValid: vec = BinaryValue() data = self.bus.tdata.value self.log.debug("received data : {}".format(data.binstr)) if hasattr(self.bus, "tkeep"): keep = self.bus.tkeep.value if 'U' in keep.binstr: self.log.warning( "received keep contains U value :{}, data : {}" .format(keep.binstr, data.binstr)) self.log.debug("received keep : {}".format(keep.binstr)) if keep == 0: self.log.warning( "received empty keep :{}, data : {}, returning 0" .format(keep.binstr, data.binstr)) vec = BinaryValue(0, 0) else: for i, v in enumerate(keep.binstr[::-1]): if v in '1U': vec.buff += bytes((data.buff[::-1][i],)) self.log.debug("recomposed data : {}".format(vec.binstr)) else: vec = data self._recv(vec)
def saxi_rd_run(self): self.log.info ("SAXIRdSim(%s).saxi_wr_run"%(self.name)) while True: # if not self.bus.rd_valid.value: # break #exit while True: yield FallingEdge(self.clock) if self.bus.rd_ready.value: break self.bus.rd_valid <= 1 # yield RisingEdge(self.clock) #Here write data try: address = self.bus.rd_address.value.integer except: self.log.warning ("SAXIRdSim() tried to write to unknown memory address") adress = None if address & ((1 << self._address_lsb) - 1): self.log.warning ("SAXIRdSim() Write memory address is not aligned to %d-byte words"%(self._data_bytes)) address = (address >> self._address_lsb) << self._address_lsb; self._memfile.seek(address) rresp=0 try: rs = self._memfile.read(self._data_bytes) except: self.log.warning ("SAXIRdSim() failed reading %d bytes form 0x%08x"%(self._data_bytes, address)) rs = None if not rs is None: try: data = struct.unpack(self._fmt,rs) except: self.log.warning ("SAXIRdSim():Can not unpack memory data @ address 0x%08x"%(address)) data=None if (not address is None) and (not data is None): self.bus.rd_resp <= 0 self.bus.rd_data <= data else: self.bus.rd_resp <= 2 # error _float_signals((self.bus.rd_data,)) self.bus.rd_valid <= 1 yield RisingEdge(self.clock) self.bus.rd_valid <= 0 _float_signals((self.bus.rd_data,self.bus.rd_resp))
async def peripheral_monitor(self): cs_n_edge = Edge( self.io['cs_n']) if self.io['cs_n'] is not None else None sdi_binstr = "" if self.io[ 'cs_n'] is not None: # some 2-wire point-to-points do not have cs await FallingEdge(self.io['cs_n']) capture_edge = FallingEdge(self.io['sclk']) if self.mode in [0, 3]: capture_edge = RisingEdge(self.io['sclk']) while len(sdi_binstr) < self.size: edge = await capture_edge if edge == cs_n_edge: break elif edge == capture_edge: sdi_binstr = sdi_binstr + self.io['sdi'].value.binstr if self.lsb_first: sdi_binstr = sdi_binstr[::-1] return sdi_binstr
async def peripheral_return_response(self, sdo_binstr): cs_n_edge = Edge( self.io['cs_n']) if self.io['cs_n'] is not None else None if self.io[ 'cs_n'] is not None: # some 2-wire point-to-points do not have cs await FallingEdge(self.io['cs_n']) if self.lsb_first: sdo_binstr = sdo_binstr[::-1] # data bits sent from left to right send_edge = FallingEdge(self.io['sclk']) if self.mode in [0, 2]: send_edge = RisingEdge(self.io['sclk']) self.io['sdo'] <= int(sdo_binstr[0], 2) # drive before 1st clock sdo_binstr = sdo_binstr[1:] # remove bit 0 (left-most bit) while sdo_binstr != "": edge = await First(cs_n_edge, send_edge) if edge == cs_n_edge: break self.io['sdo'] <= int(sdo_binstr[0], 2) sdo_binstr = sdo_binstr[1:] # remove bit 0 (left-most bit)
def start(self): while not self.finish: yield FallingEdge(self.clock) if 0 in range(self.num_queues): # measure size of queue 0 q_size_0 = self.dut.simple_tm_inst.q_size_0.value.integer self.q_sizes[0].append(q_size_0) if 1 in range(self.num_queues): # measure size of queue 1 q_size_1 = self.dut.simple_tm_inst.q_size_1.value.integer self.q_sizes[1].append(q_size_1) if 2 in range(self.num_queues): # measure size of queue 2 q_size_2 = self.dut.simple_tm_inst.q_size_2.value.integer self.q_sizes[2].append(q_size_2) if 3 in range(self.num_queues): # measure size of queue 3 q_size_3 = self.dut.simple_tm_inst.q_size_3.value.integer self.q_sizes[3].append(q_size_3)
def _register(self): while True: try: dlatch = int(self._dut.io_dlatch) except ValueError: dlatch = 1 if dlatch != 0: yield FallingEdge(self._dut.io_dlatch) self._reg = self.reg_init_value self._reg_count = self._reg_len sdata_bit = (self.reg_init_value & (0x1<<(self._reg_len-1))) >> (self._reg_len - 1) self._dut.io_sdata <= sdata_bit else: sdata_bit = self._reg & (0x1<<(self._reg_len-1)) self._dut.io_sdata <= (sdata_bit != 0) if self._reg_count != 0: self._reg = (self._reg << 1) yield [RisingEdge(self._dut.io_dclock), RisingEdge(self._dut.io_dlatch)]
def _cr_stim(self): if self._generator is None: raise Exception("No generator provided for Bin2BcdDriver!") edge = RisingEdge(self._clk) val = self._generator() while True: data = next(val) self._data <= data self._start <= 1 for _ in range(3): yield edge self._start <= 0 yield FallingEdge(self._busy) if self._callback is not None: self._callback(data)
def write_fifo(dut, clk, max_delay=5, write_items=10000, write_random_data=False): """ Write to a FIFO Before writing wait between 0 and max_delay cycles. """ fifo_wrcnt = 0 while True: # insert random wait before the next write wr_delay = random.randint(0, max_delay) dut._log.debug("WRITE: Wait for %d clock cycles" % (wr_delay)) for _ in range(wr_delay): yield RisingEdge(clk) # make sure that the full signal is stable before checking for it yield FallingEdge(clk) if dut.full.value: dut._log.debug("WRITE: FIFO full, not writing") else: # generate and write data, keep track of it for checking if write_random_data: data = random.getrandbits(dut.WIDTH.value.integer) else: data = fifo_wrcnt % (2**dut.WIDTH.value.integer) dut.din <= data _fifo_data.append(data) dut.wr_en <= 1 yield RisingEdge(clk) dut.wr_en <= 0 fifo_wrcnt += 1 dut._log.debug("WRITE: Wrote word %d to FIFO, value 0x%x" % (fifo_wrcnt, data)) if fifo_wrcnt >= write_items: return
def mult_basic_test(dut): """Test basic multiplication""" A = 5 B = 10 # initialize dut inputs dut.start = 0 dut.x1 = 0 dut.y = 0 # sequentially do reset yield reset_dut(dut, 200) dut._log.debug("After reset") # Fork parallel clock thread cocotb.fork(Clock(dut.clk, 10, units='ns').start()) for val in gen_sin(): dut.start = 1 dut.x1 = 1 dut.y = int(2**15 * val) #yield RisingEdge(dut.clk) #yield FallingEdge(dut.clk) yield Timer(20, units='ns') dut.start = 0 yield RisingEdge(dut.valid) if multiplier_model(1, int(2**15 * val)) != translate_res(dut.z1): #if int(dut.z) != multiplier_model(A, B): raise TestFailure("For val = " + str(val) + "Multiplier result is incorrect: " + str(multiplier_model(1, int(2**15 * val))) + " != " + str(translate_res(dut.z))) else: # these last two lines are not strictly necessary dut._log.info("Ok! For val = " + str(val) + "Multiplier result is correct: " + str(multiplier_model(1, int(2**15 * val))) + " = " + str(translate_res(dut.z))) yield FallingEdge(dut.valid)
def __init__(self, dut, dclk_freq_mhz, rio_phy_freq_mhz): self.dut = dut self.clk_period_ps = int(1.0 / dclk_freq_mhz * 1e6) self.rio_period_ps = int(1.0 / rio_phy_freq_mhz * 1e6) self.re = RisingEdge(dut.dclk_p) self.fe = FallingEdge(dut.dclk_p) self.channel_csr = [ RtLinkCSR(definition_file_path= "sim_build/rtlinkcsr_tdc_gpx_channel_phy.txt", rio_phy_clock=self.dut.rio_phy_clk, stb_i=getattr(self.dut, "rtlink{}_stb_i".format(i)), data_i=getattr(self.dut, "rtlink{}_data_i".format(i)), address_i=getattr(self.dut, "rtlink{}_address_i".format(i)), stb_o=getattr(self.dut, "rtlink{}_stb_o".format(i)), data_o=getattr(self.dut, "rtlink{}_data_o".format(i))) for i in range(4) ]
def _monitor_recv(self): while True: yield FallingEdge(self.clk) self.ready <= 1 while True: yield RisingEdge(self.clk) try: if self.valid == 1: if isinstance(self.data, dict): transaction = [] for name, signal in self.data: transaction[name] = signal else: transaction = self.data self._recv(transaction) break except ValueError: pass
async def wishbone_write(dut, address, data): assert dut.wbs_ack_o == 0 await RisingEdge(dut.wb_clk_i) dut.wbs_stb_i <= 1 dut.wbs_cyc_i <= 1 dut.wbs_we_i <= 1 # write dut.wbs_sel_i <= 0b1111 # select all bytes, // which byte to read/write dut.wbs_dat_i <= data dut.wbs_adr_i <= address await with_timeout(RisingEdge(dut.wbs_ack_o), 100, 'us') await RisingEdge(dut.wb_clk_i) dut.wbs_cyc_i <= 0 dut.wbs_stb_i <= 0 dut.wbs_sel_i <= 0 dut.wbs_dat_i <= 0 dut.wbs_adr_i <= 0 await with_timeout(FallingEdge(dut.wbs_ack_o), 100, 'us')
async def test_ram_random(dut): dv = dv_test(dut, "Fail", 4) clk = Clock(dut.clk, 10, units="ns") # Create a 10us period clock on port clk cocotb.fork(clk.start()) # Start the clock tick = FallingEdge(dut.clk) expect_ram = {} await tick # Synchronize with the clock for i in range(5000): i_we = random.randint(0, 1) dut.i_we = i_we i_dat = random.randint(0, 2**16 - 1) dut.i_dat <= i_dat i_addr = random.randint(0, 2**8 - 1) dut.i_addr = i_addr rdata_exp = expect_ram.get(i_addr) if i_we == 1: expect_ram.update({i_addr: i_dat}) await tick if i_we == 0: dv.eq(dut.o_dat, rdata_exp, "ram[" + str(i_addr) + "]") for i in range(256): dut.i_we = 0 dut.i_addr = i if force_fail: if i >= 250: expect_ram[i] = 0 await tick dv.eq(dut.o_dat, expect_ram.get(i), "ram[" + str(i) + "]") dv.done()
def i2cSlaveThread(cmdBus, rspBus, cmds, rsps, clk): rspBus.valid <= False while cmds: yield FallingEdge(clk) rspBus.valid <= False if str(cmdBus.kind) == "xxx" or cmdBus.kind == NONE: continue expected = cmds.pop(0) # log.debug(expected) if expected == "start": assert cmdBus.kind == START elif expected == "restart": assert cmdBus.kind == RESTART elif expected == "stop": assert cmdBus.kind == STOP elif expected == "drop": assert cmdBus.kind == DROP elif expected == "drive": assert cmdBus.kind == DRIVE if random.uniform(0, 1) < 1.0 / (2500000/100000) * 2: rsp = rsps.pop(0) if rsp == "Z": rspBus.valid <= True rspBus.enable <= False rspBus.data <= randInt(0, 1) elif isinstance(rsp, bool): rspBus.valid <= True rspBus.enable <= True rspBus.data <= rsp else: raise Exception(rsp) else: cmds.insert(0,expected) elif isinstance(expected, bool): assert cmdBus.kind == READ assert cmdBus.data == expected else: raise Exception("???")
def basic_test(dut): cocotb.fork(setDiffClk(dut.extclk_p, dut.extclk_n, 3.333)) dut.rst = 0 yield Timer(30 * TIMESCALE) yield issueReset(dut.extrst, 1050) shadow = SataHostDriver(dut, "", dut.clk) yield FallingEdge(dut.rst) # set random data to shadow registers yield RisingEdge(dut.clk) cocotb.fork(shadow.setReg(1, 0xe)) cocotb.fork(shadow.setReg(4, 0xdead)) cocotb.fork(shadow.setReg(5, 0xbee1)) yield Timer(100 * TIMESCALE) # write registers to a device yield RisingEdge(dut.clk) # cocotb.fork(shadow.setCmd(cmd_type = 1, cmd_port = 0, cmd_val = 1)) yield Timer(40000 * TIMESCALE)
def rx_driver(self): while True: if (len(self.rx_fifo) > 0): self.dut.rxf_245 <= 0 if (self.dut.rx_245.value.integer == 1): yield FallingEdge(self.dut.rx_245) yield nsTimer(RD_TO_DATA) #self.dut.in_out_245 <= 0 aux = self.rx_fifo.pop(0) self.dut.in_out_245 <= aux #self.rx_fifo.pop(0) #print "-----------------------------------------------" #print "AUX = " + repr(aux) yield Timer(1, units='ps') #print "FDTI RX: " + repr(self.dut.in_out_245.value.integer) #print "-----------------------------------------------" if (self.dut.rx_245.value.integer == 0): yield RisingEdge(self.dut.rx_245) #self.dut.in_out_245 <= 0 yield nsTimer(14) self.dut.rxf_245 <= 1 yield nsTimer(RFX_INACTIVE)
def _monitor_recv(self): """Capture all DUT to Host IRQ requests""" irq = self.dut.reg_host_irq # Wait for the logic to be reset yield ReadOnly() yield RisingEdge(self.dut.reset_n) while True: # Wait on the regfile to assert the IRQ while irq.value.integer != 1: yield RisingEdge(irq) # Signal any subscribers that the IRQ has fired self._recv({'time': get_sim_time('ns')}) # Wait for the interrupt(s) to be cleared while irq.value.integer == 1: yield FallingEdge(irq)
def _monitor_recv(self): while True: data = 0 if self.config.flow_control == UARTFlowControl.HARDWARE: self.ctsn <= 0 # Wait for start of character yield FallingEdge(self.rx) # Sample on the center of the start bit yield Timer(self.duration / 2) # Malformed start bit if self.rx != 0: raise TestError("start bit error") # Sample all bits for b in range(self.config.bits): yield Timer(self.duration) if self.rx == 1: data = data | (1 << b) # Parity if self.config.parity != UARTParity.NONE: yield Timer(self.duration) if self.rx != parity(data, self.config.bits, self.config.parity): raise TestError("parity error") # Stopbit(s) for b in range(self.config.stopbits): yield Timer(self.duration) if self.rx != 1: raise TestError("stop bit error") if self.config.flow_control == UARTFlowControl.HARDWARE: self.ctsn <= 1 self._recv(data)
def ex_stage_jump(dut): """EX_STAGE JUMP OPERATION""" cocotb.fork(Clock(dut.clk, 10).start()) for i in range(0, iterations): pc_jump = random.randint(0, 0xFFFFFFFF) data_s = random.randint(0, 0xFFFFFFFF) jmp_d_r = random.randint(0, 1) dut.we = 1 dut.reset = 0 dut.alu_s = 0 dut.alu_t = 0 dut.alu_op = 0 dut.dst_reg = 0 dut.is_link = 0 dut.is_jump = 1 dut.dst_jump = jmp_d_r dut.pc_jump = pc_jump dut.pc_next = 0 dut.data_s = data_s dut.data_t = 0 dut.data_c0 = 0 dut.opcode = 0 dut.funct = 0 dut.reg_s = 0 dut.reg_t = 0 dut.reg_d = 0 dut.is_branch = 0 dut.mem_read = 0 dut.mem_write = 0 dut.mem_type = 0 dut.mem_to_reg = 0 dut.reg_write = 0 dut.immediate = 0 yield Timer(6) yield FallingEdge(dut.clk) jump = data_s if jmp_d_r else pc_jump if jump != int(dut.pc_jump_out): print jump, data_s, pc_jump raise TestFailure("pc_jump: %d, Wrong pc_jump: %d" % (jump, int(dut.pc_jump_out)))