def test_adder_vhdl():
DATA_WIDTH = 5
for i in range(2, DATA_WIDTH):
run(verilog_sources=["../../../hdl/adder.v"],
toplevel="adder",
module="test_adder",
toplevel_lang="verilog")
def test_processor():
"""Test running verilog testbench."""
run(verilog_sources=[
"./tests/processor/verilog/alu.v", "./tests/processor/verilog/bitgen.v"
"./tests/processor/verilog/btn_debounce.v",
"./tests/processor/verilog/controller.v"
"./tests/processor/verilog/dataPath.v",
"./tests/processor/verilog/exmem.v"
"./tests/processor/verilog/glyphs.v",
"./tests/processor/verilog/instructionRegister.v"
"./tests/processor/verilog/LSFR.v", "./tests/processor/verilog/mux2.v",
"./tests/processor/verilog/mux4.v",
"./tests/processor/verilog/programcounter.v"
"./tests/processor/verilog/regfile.v",
"./tests/processor/verilog/register.v",
"./tests/processor/verilog/shifter.v",
"./tests/processor/verilog/signExtend.v",
"./tests/processor/verilog/statemachine.v",
"./tests/processor/verilog/switch_tester.v",
"./tests/processor/verilog/top.v",
"./tests/processor/verilog/vga_control.v",
"./tests/processor/verilog/vga.v"
],
toplevel="top",
module="tests.processor.processor_cocotb",
sim_build="./tests/processor/verilog/sim_build")
def test_dff_verilog():
run(
verilog_sources=[os.path.join(example_dir, "dff", "hdl", "dff.v")],
toplevel="dff",
python_search=[os.path.join(example_dir, "dff", "tests")],
module="dff_cocotb",
force_compile=True,
)
def test_dff():
"""Test running verilog testbench."""
run(
verilog_sources=["./tests/dff/verilog/dff.v"],
toplevel="dff_test",
module="dff_cocotb",
sim_build="./tests/dff/verilog/sim_build"
)
def test_dpram_vhdl():
run(vhdl_sources=[
"../../sources_1/ipbus/hdl/ipbus_package.vhd",
"../../sources_1/ipbus/firmware/hdl/ipbus_decode_ipbus_example.vhd"
],
toplevel="ipbus_ported_dpram",
module="dpram_tb",
toplevel_lang="vhdl")
def test_adder_vhdl():
DATA_WIDTH = 5
for _ in range(2,DATA_WIDTH):
run(vhdl_sources=["../../../hdl/adder.vhd"],
simulation_args=["--vcd=func.vcd","-gDATA_WIDTH="+str(DATA_WIDTH)],
toplevel="adder",
module="test_adder",
toplevel_lang="vhdl"
)
def test_basic(seed):
extra_env = {"COVERAGE_RESULTS_FILENAME": join(testsd, "sim_build", "config_regs_coverage_seed"+str(seed)+".yaml")}
run(
verilog_sources=rtl_files, # always a list
toplevel="config_regs",
module="tb_config_regs",
compile_args=compile_args,
python_search=[tbd, join(tbd, "config_regs/")],
seed=str(seed),
extra_env=extra_env)
def test_cocotb_35():
run(
verilog_sources=[
os.path.join(tests_dir, "designs", "sample_module",
"sample_module.sv")
],
python_search=[os.path.join(tests_dir, "test_cases", "test_cocotb")],
toplevel="sample_module",
module="test_cocotb_35",
)
def test_endian_swapper_verilog():
run(
verilog_sources=[
os.path.join(example_dir, "endian_swapper", "hdl",
"endian_swapper.sv")
],
toplevel="endian_swapper_sv",
python_search=[os.path.join(example_dir, "endian_swapper", "tests")],
module="test_endian_swapper",
)
def test_endian_swapper_vhdl():
run(
vhdl_sources=[
os.path.join(example_dir, "endian_swapper", "hdl",
"endian_swapper.vhdl")
],
toplevel="endian_swapper_vhdl",
python_search=[os.path.join(example_dir, "endian_swapper", "tests")],
module="test_endian_swapper",
toplevel_lang="vhdl",
)
def test_adder_verilog():
run(
verilog_sources=[os.path.join(example_dir, "adder", "hdl", "adder.v")],
toplevel="adder",
python_search=[
os.path.join(example_dir, "adder", "tests"),
os.path.join(example_dir, "adder", "model")
],
module="test_adder",
force_compile=True,
)
def test_Zybo_Example():
run(
vhdl_sources=["$(PWD)/../../../../src/Zybo_Example/Zybo_Example_regs_pkg.vhd",
"$(PWD)/../../../../src/Zybo_Example/Zybo_Example_regs.vhd",
"$(PWD)/../../../../src/Zybo_Example/Zybo_Example_pkg.vhd",
"$(PWD)/../../../../src/Zybo_Example/Zybo_Example.vhd",],
simulation_args=["--wave=wave.ghw"],
toplevel="zybo_example",
module="Zybo_Example_tb",
toplevel_lang="vhdl"
)
def test_ping_tun_tap():
if os.name != "posix" or os.geteuid() != 0:
pytest.skip("This test works only on a POSIX OS with admin rights")
run(
verilog_sources=[
os.path.join(example_dir, "ping_tun_tap", "hdl", "icmp_reply.sv")
],
toplevel="icmp_reply",
python_search=[os.path.join(example_dir, "ping_tun_tap", "tests")],
module="test_icmp_reply",
)
def test_mean():
run(
vhdl_sources=[
os.path.join(example_dir, "mean", "hdl", "mean_pkg.vhd"),
os.path.join(example_dir, "mean", "hdl", "mean.vhd")
],
verilog_sources=[
os.path.join(example_dir, "mean", "hdl", "mean_sv.sv")
],
toplevel="mean_sv",
python_search=[os.path.join(example_dir, "mean", "tests")],
module="test_mean",
force_compile=True,
)
def test_axi_lite_slave():
run(
verilog_sources=[
os.path.join(example_dir, "axi_lite_slave", "hdl",
"axi_lite_slave.v"),
os.path.join(example_dir, "axi_lite_slave", "hdl",
"axi_lite_demo.v"),
os.path.join(example_dir, "axi_lite_slave", "hdl",
"tb_axi_lite_slave.v"),
],
toplevel="tb_axi_lite_slave",
includes=[os.path.join(example_dir, "axi_lite_slave", "hdl")],
python_search=[os.path.join(example_dir, "axi_lite_slave", "tests")],
module="test_axi_lite_slave",
)
def test_mixed_top_verilog():
run(
vhdl_sources=[
os.path.join(example_dir, "endian_swapper", "hdl",
"endian_swapper.vhdl")
],
verilog_sources=[
os.path.join(example_dir, "endian_swapper", "hdl",
"endian_swapper.sv"),
os.path.join(example_dir, "mixed_language", "hdl", "toplevel.sv"),
],
toplevel="endian_swapper_mixed",
python_search=[os.path.join(example_dir, "mixed_language", "tests")],
module="test_mixed_language",
force_compile=True,
)
def test_verilog_access():
run(
verilog_sources=[
os.path.join(tests_dir, "designs", "uart2bus", "verilog", file)
for file in [
"baud_gen.v",
"uart_parser.v",
"uart_rx.v",
"uart_tx.v",
"uart_top.v",
"uart2bus_top.v",
]
] + [
os.path.join(tests_dir, "designs", "uart2bus", "top",
"verilog_toplevel.sv")
],
vhdl_sources=[
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"uart2BusTop_pkg.vhd"),
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"baudGen.vhd"),
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"uartParser.vhd"),
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"uartRx.vhd"),
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"uartTx.vhd"),
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"uartTop.vhd"),
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"uart2BusTop.vhd"),
],
python_search=[
os.path.join(tests_dir, "test_cases", "test_verilog_access")
],
toplevel="verilog_toplevel",
module="test_verilog_access",
)
def launch_cocotb_test(test: Test):
build_dir = os.path.join(os.getcwd(), BUILD)
if os.path.isdir(build_dir):
shutil.rmtree(build_dir)
os.environ["SIM"], language, source_arg = {
SimulatorNames.GHDL.value: ("ghdl", "vhdl", "vhdl_sources"),
SimulatorNames.ICARUS.value: ("icarus", "verilog", "verilog_sources"),
}.get(test.tool.name)
src_list, module_list = separate_src_and_modules(test.files.all())
modules = ""
for module in module_list:
modules += generate_relative_imports(test.working_dir, module) + ','
modules = modules[:-1]
simulator_args = []
for sarg in test.tool_options.all():
text = sarg.group
if sarg.argument:
text += "=" + sarg.argument
simulator_args.append(text)
args = {
source_arg: src_list,
"toplevel": test.top_level,
"module": modules,
"toplevel_lang": language,
"run_dir": test.working_dir,
"simulation_args": simulator_args
}
try:
sim_result = run(**args)
except Exception:
sim_result = search_for_file_by_ext(build_dir, RESULT_EXT)
test.result = XmlParser().coco_xml(
sim_result, search_for_file_by_ext(build_dir, WAVE_EXT))
def test_dff_vhdl():
run(vhdl_sources=["dff.vhdl"],
toplevel="dff_test_vhdl",
module="dff_cocotb",
toplevel_lang="vhdl")
def test_adder_vhdl():
run(vhdl_sources=["./example_0.vhd"],
simulation_args=["--vcd=func.vcd"],
toplevel="arith_counter_gray",
module="cocotb",
toplevel_lang="vhdl")
def test_plus_args():
run(
verilog_sources=["plus_args.v"],
toplevel="plus_args",
plus_args=["+USER_MODE", "+TEST=ARB_TEST"],
)
def test_plus_args_fail():
run(verilog_sources=["plus_args.v"], toplevel="plus_args")
def test_plus_args_test_wrong():
run(
verilog_sources=["plus_args.v"], toplevel="plus_args", plus_args=["+XUSER_MODE"]
)
def test_dff_custom_ius():
run(simulator=IusCustom, toplevel="dff", python_search=["."], module="dff_cocotb", defsfile="ius_defines.f") # extra custom argument
def test_dff_verilog():
run(verilog_sources=["dff.v"], toplevel="dff_test", module="dff_cocotb"
) # sources # top level HDL # name of cocotb test module
def gamma_test():
run(vhdl_sources=["../src/gamma.vhd"],
simulation_args=["--vcd=func.vcd"],
toplevel="gamma",
module="gamma_testAlive",
toplevel_lang="vhdl")
def test_dff_no_workdir():
run(verilog_sources=["../../dff.v"], toplevel="dff_test", module="dff_cocotb") # sources # top level HDL # name of cocotb test module
def test_adder_vhdl():
run(vhdl_sources=["../../../hdl/axi.vhd", "../../../hdl/axi_pkg.vhd"],
simulation_args=["--vcd=func.vcd"],
toplevel="axi",
module="test_axi",
toplevel_lang="vhdl")
