async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) if os.getenv("PCIE_OFFSET") is None: pcie_offsets = list(range(4))+list(range(4096-4, 4096)) else: pcie_offsets = [int(os.getenv("PCIE_OFFSET"))] byte_width = tb.axi_ram.byte_width tag_count = 2**len(tb.write_desc_source.bus.tag) cur_tag = 1 tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) await FallingEdge(dut.rst) await Timer(100, 'ns') await tb.rc.enumerate(enable_bus_mastering=True) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) tb.dut.enable <= 1 for length in list(range(1, byte_width+3))+list(range(128-4, 128+4))+[1024]: for pcie_offset in pcie_offsets: for axi_offset in list(range(byte_width+1))+list(range(4096-byte_width, 4096)): tb.log.info("length %d, pcie_offset %d, axi_offset %d", length, pcie_offset, axi_offset) pcie_addr = pcie_offset+0x1000 axi_addr = axi_offset+0x1000 test_data = bytearray([x % 256 for x in range(length)]) tb.axi_ram.write(axi_addr & 0xffff80, b'\x55'*(len(test_data)+256)) mem_data[pcie_addr-128:pcie_addr-128+len(test_data)+256] = b'\xaa'*(len(test_data)+256) tb.axi_ram.write(axi_addr, test_data) tb.log.debug("%s", tb.axi_ram.hexdump_str((axi_addr & ~0xf)-16, (((axi_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI ")) desc = DescTransaction(pcie_addr=mem_base+pcie_addr, axi_addr=axi_addr, len=len(test_data), tag=cur_tag) await tb.write_desc_source.send(desc) status = await tb.write_desc_status_sink.recv() await Timer(100 + (length // byte_width), 'ns') tb.log.info("status: %s", status) assert int(status.tag) == cur_tag tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe ")) assert mem_data[pcie_addr-1:pcie_addr+len(test_data)+1] == b'\xaa'+test_data+b'\xaa' cur_tag = (cur_tag + 1) % tag_count await RisingEdge(dut.clk) await RisingEdge(dut.clk)
async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) if os.getenv("PCIE_OFFSET") is None: pcie_offsets = list(range(4))+list(range(4096-4, 4096)) else: pcie_offsets = [int(os.getenv("PCIE_OFFSET"))] byte_lanes = tb.dma_ram.byte_lanes tag_count = 2**len(tb.read_desc_source.bus.tag) cur_tag = 1 tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) await FallingEdge(dut.rst) await Timer(100, 'ns') await tb.rc.enumerate(enable_bus_mastering=True) mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) tb.dut.enable <= 1 for length in list(range(1, byte_lanes+3))+list(range(128-4, 128+4))+[1024]: for pcie_offset in pcie_offsets: for ram_offset in range(byte_lanes+1): tb.log.info("length %d, pcie_offset %d, ram_offset %d", length, pcie_offset, ram_offset) pcie_addr = pcie_offset+0x1000 ram_addr = ram_offset+0x1000 test_data = bytearray([x % 256 for x in range(length)]) mem_data[pcie_addr:pcie_addr+len(test_data)] = test_data tb.log.debug("%s", hexdump_str(mem_data, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe ")) tb.dma_ram.write(ram_addr-256, b'\xaa'*(len(test_data)+512)) desc = DescTransaction(pcie_addr=mem_base+pcie_addr, ram_addr=ram_addr, ram_sel=0, len=len(test_data), tag=cur_tag) await tb.read_desc_source.send(desc) status = await tb.read_desc_status_sink.recv() tb.log.info("status: %s", status) assert int(status.tag) == cur_tag tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48, prefix="RAM ")) assert tb.dma_ram.read(ram_addr-8, len(test_data)+16) == b'\xaa'*8+test_data+b'\xaa'*8 cur_tag = (cur_tag + 1) % tag_count await RisingEdge(dut.clk) await RisingEdge(dut.clk)
async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) byte_lanes = tb.axi_ram.write_if.byte_lanes tag_count = 2**len(tb.read_desc_source.bus.tag) cur_tag = 1 tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) await FallingEdge(dut.rst) await Timer(100, 'ns') await tb.rc.enumerate(enable_bus_mastering=True) mem = tb.rc.mem_pool.alloc_region(16*1024*1024) mem_base = mem.get_absolute_address(0) tb.dut.read_enable.value = 1 for length in list(range(0, byte_lanes+3))+list(range(128-4, 128+4))+[1024]: for pcie_offset in list(range(4))+list(range(4096-4, 4096)): for axi_offset in range(1): tb.log.info("length %d, pcie_offset %d, axi_offset %d", length, pcie_offset, axi_offset) pcie_addr = pcie_offset+0x1000 axi_addr = axi_offset+0x1000 test_data = bytearray([x % 256 for x in range(length)]) mem[pcie_addr:pcie_addr+len(test_data)] = test_data tb.log.debug("%s", hexdump_str(mem, (pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="PCIe ")) tb.axi_ram.write(axi_addr-256, b'\xaa'*(len(test_data)+512)) desc = DescTransaction(pcie_addr=mem_base+pcie_addr, axi_addr=axi_addr, len=len(test_data), tag=cur_tag) await tb.read_desc_source.send(desc) status = await tb.read_desc_status_sink.recv() tb.log.info("status: %s", status) assert int(status.tag) == cur_tag assert int(status.error) == 0 tb.log.debug("%s", tb.axi_ram.hexdump_str((axi_addr & ~0xf)-16, (((axi_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI ")) assert tb.axi_ram.read(axi_addr-8, len(test_data)+16) == b'\xaa'*8+test_data+b'\xaa'*8 cur_tag = (cur_tag + 1) % tag_count await RisingEdge(dut.clk) await RisingEdge(dut.clk)
async def run_test(dut): tb = TB(dut) await tb.init() mem_base, mem_data = tb.rc.alloc_region(16*1024*1024) dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2] tb.log.info("Test memory write to BAR 2") await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44') await Timer(100, 'ns') tb.log.info("Test memory read from BAR 2") val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000) tb.log.info("Read data: %s", val) assert val == b'\x11\x22\x33\x44' tb.log.info("Test DMA") # write packet data mem_data[0:1024] = bytearray([x % 256 for x in range(1024)]) # enable DMA await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1) # write pcie read descriptor await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff) await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff) await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff) await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff) await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400) await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA) await Timer(2000, 'ns') # read status val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118) tb.log.info("Status: 0x%x", val) assert val == 0xAA # write pcie write descriptor await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff) await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff) await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff) await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff) await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400) await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55) await Timer(2000, 'ns') # read status val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218) tb.log.info("Status: 0x%x", val) assert val == 0x55 tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64)) assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024] await RisingEdge(dut.clk) await RisingEdge(dut.clk)
async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None): tb = TB(dut) if os.getenv("PCIE_OFFSET") is None: pcie_offsets = list(range(4)) + list(range(4096 - 4, 4096)) else: pcie_offsets = [int(os.getenv("PCIE_OFFSET"))] byte_lanes = tb.dma_ram.byte_lanes tag_count = 2**len(tb.write_desc_source.bus.tag) cur_tag = 1 tb.set_idle_generator(idle_inserter) tb.set_backpressure_generator(backpressure_inserter) await FallingEdge(dut.rst) await Timer(100, 'ns') await tb.rc.enumerate() dev = tb.rc.find_device(tb.dev.functions[0].pcie_id) await dev.enable_device() await dev.set_master() mem = tb.rc.mem_pool.alloc_region(16 * 1024 * 1024) mem_base = mem.get_absolute_address(0) tb.dut.enable.value = 1 for length in list(range(0, byte_lanes + 3)) + list(range( 128 - 4, 128 + 4)) + [1024]: for pcie_offset in pcie_offsets: for ram_offset in range(byte_lanes + 1): tb.log.info("length %d, pcie_offset %d, ram_offset %d", length, pcie_offset, ram_offset) pcie_addr = pcie_offset + 0x1000 ram_addr = ram_offset + 0x1000 test_data = bytearray([x % 256 for x in range(length)]) tb.dma_ram.write(ram_addr & 0xffff80, b'\x55' * (len(test_data) + 256)) mem[pcie_addr - 128:pcie_addr - 128 + len(test_data) + 256] = b'\xaa' * (len(test_data) + 256) tb.dma_ram.write(ram_addr, test_data) tb.log.debug( "%s", tb.dma_ram.hexdump_str( (ram_addr & ~0xf) - 16, (((ram_addr & 0xf) + length - 1) & ~0xf) + 48, prefix="RAM ")) desc = DescTransaction(pcie_addr=mem_base + pcie_addr, ram_addr=ram_addr, ram_sel=0, len=len(test_data), tag=cur_tag) await tb.write_desc_source.send(desc) status = await tb.write_desc_status_sink.recv() await Timer(100 + (length // byte_lanes), 'ns') tb.log.info("status: %s", status) assert int(status.tag) == cur_tag assert int(status.error) == 0 tb.log.debug( "%s", hexdump_str(mem, (pcie_addr & ~0xf) - 16, (((pcie_addr & 0xf) + length - 1) & ~0xf) + 48, prefix="PCIe ")) assert mem[pcie_addr - 1:pcie_addr + len(test_data) + 1] == b'\xaa' + test_data + b'\xaa' cur_tag = (cur_tag + 1) % tag_count await RisingEdge(dut.clk) await RisingEdge(dut.clk)