def genWriteRsp(self):
if len(self.writeCmds) != 0:
if not self.writeRspIdleRand.get():
return None
cmd = self.writeCmds[0]
beatCount = cmd.len + 1
if len(self.writeDatas) >= beatCount:
datas = self.writeDatas[0:beatCount - 1]
#Check it
masterWrite = next(write
for write in self.idToWrites[cmd.hid & 0xF]
if write.addr >> 10 == self.hid)
assertEquals(cmd.addr, masterWrite.addr, "write cmd missmatch")
assertEquals(cmd.len, masterWrite.len, "write cmd missmatch")
for data, dataRef in zip(datas, masterWrite.linkedDatas):
assertEquals(data.data, dataRef.data,
"write data missmatch")
#Clean
self.writeCmds = self.writeCmds[1:]
self.writeDatas = self.writeDatas[beatCount:]
self.idToWrites[cmd.hid & 0xF].remove(masterWrite)
#Answer
trans = Transaction()
trans.hid = cmd.hid
trans.resp = 0
return trans
return None
def onWriteCmd(self,cmd):
for i in xrange(cmd.len + 1):
writeData = Transaction()
writeData.data = cmd.addr + i
writeData.strb = (cmd.addr + i) & 0xF
writeData.last = 1 if i == cmd.len else 0
self.dataScoreboard.refPush(writeData)
def onWriteCmd(self,cmd):
for i in range(cmd.len + 1):
writeData = Transaction()
writeData.data = cmd.addr + i
writeData.strb = (cmd.addr + i) & 0xF
writeData.last = 1 if i == cmd.len else 0
self.dataScoreboard.refPush(writeData)
def genCmdB(self):
if self.getPhase() != PHASE_SIM:
return None
if self.memInitDone and random.random() < 0.5:
trans = Transaction()
trans.itself = randBits(32)
return trans
def onWriteCmd(self, cmd):
rsp = Transaction()
rsp.hid = cmd.hid
if cmd.addr < (1 << 14):
rsp.resp = 0
else:
rsp.resp = 3
self.writeRspScoreboard.refPush(rsp, cmd.hid)
def genRsp(self):
if not self.cmdA.empty() and not self.cmdB.empty():
cmdA = self.cmdA.get()
cmdB = self.cmdB.get()
rsp = Transaction()
rsp.itself = self.mem[cmdA.itself] ^ cmdB.itself
self.scoreboard.refPush(rsp)
def onWriteCmd(self,cmd):
rsp = Transaction()
rsp.hid = cmd.hid
if cmd.addr < (1 << 14):
rsp.resp = 0
else:
rsp.resp = 3
self.writeRspScoreboard.refPush(rsp, cmd.hid)
def read(self, address, rsp):
ar = Transaction()
ar.addr = address
ar.prot = 0
self.arQueue.put(ar)
while True:
yield RisingEdge(self.clk)
if self.axiLite.r.valid == True and self.axiLite.r.ready == True:
rsp[0] = int(self.axiLite.r.payload.data)
break
def managePendingWrites(self):
if len(self.writeCmds) != 0:
cmd = self.writeCmds[0]
beatCount = cmd.len + 1
if len(self.writeDatas) >= beatCount:
datas = self.writeDatas[0:beatCount - 1]
# Clean
self.writeCmds = self.writeCmds[1:]
self.writeDatas = self.writeDatas[beatCount:]
# Rsp
rsp = Transaction()
rsp.hid = cmd.hid
rsp.resp = 0
queue = self.writeRspQueues[cmd.hid]
if queue.empty():
self.nonEmptyWriteRspQueues.append(queue)
queue.put(rsp)
def onReadCmd(self, cmd):
for i in xrange(cmd.len + 1):
rsp = Transaction()
rsp.hid = cmd.hid
if cmd.addr < (1 << 14):
rsp.data = cmd.addr + i
rsp.resp = 0
else:
rsp.data = 0
rsp.resp = 3
rsp.last = 1 if i == cmd.len else 0
self.readRspScoreboard.refPush(rsp, cmd.hid)
def managePendingWrites(self):
if len(self.writeCmds) != 0:
cmd = self.writeCmds[0]
beatCount = cmd.len + 1
if len(self.writeDatas) >= beatCount:
datas = self.writeDatas[0:beatCount - 1]
# Clean
self.writeCmds = self.writeCmds[1:]
self.writeDatas = self.writeDatas[beatCount:]
# Rsp
rsp = Transaction()
rsp.hid = cmd.hid
rsp.resp = 0
queue = self.writeRspQueues[cmd.hid]
if queue.empty():
self.nonEmptyWriteRspQueues.append(queue)
queue.put(rsp)
def write(self, address, data):
aw = Transaction()
aw.addr = address
aw.prot = 0
self.awQueue.put(aw)
w = Transaction()
w.data = data
w.strb = 0xF
self.wQueue.put(w)
while True:
yield RisingEdge(self.clk)
if self.axiLite.b.valid == True and self.axiLite.b.ready == True:
break
def rxThread(self):
while True:
data, addr = self.sock.recvfrom(2048)
print "received message:", data, addr
cmdTrans = Transaction()
ipSplit = addr[0].split(".")
cmdTrans.ip = 0
for i in range(4):
cmdTrans.ip |= int(ipSplit[i]) << (i * 8)
cmdTrans.srcPort = addr[1]
cmdTrans.dstPort = SERVER_PORT
cmdTrans.length = len(data)
self.rxCmdQueue.put(cmdTrans)
for i in range(len(data)):
dataTrans = Transaction()
dataTrans.last = (i == len(data) - 1)
dataTrans.fragment = ord(data[i])
self.rxDataQueue.put(dataTrans)
self.clkTocken[0] += 1000
def onReadCmd(self,cmd):
for i in xrange(cmd.len + 1):
rsp = Transaction()
rsp.hid = cmd.hid
if cmd.addr < (1 << 14):
rsp.data = cmd.addr + i
rsp.resp = 0
else:
rsp.data = 0
rsp.resp = 3
rsp.last = 1 if i == cmd.len else 0
self.readRspScoreboard.refPush(rsp, cmd.hid)
def genReadRsp(self):
tasksQueue = self.getRandTaskList()
if tasksQueue:
if self.readRspIdleRand.get():
task = tasksQueue.queue[0]
trans = Transaction()
trans.data = task.addr + task.progress
trans.resp = 0
trans.hid = task.hid
task.progress += 1
if task.progress == task.len + 1:
trans.last = 1
tasksQueue.get()
else:
trans.last = 0
return trans
def onReadCmd(self, trans):
if trans.addr < self.base or trans.addr >= self.base + self.size:
raise TestFailure("WRONG ADDRESS addr=%d base=%d size=%d" %
(trans.addr, self.base, self.size))
for i in range(trans.len + 1):
rsp = Transaction()
rsp.data = trans.addr + i
rsp.resp = 0
rsp.hid = trans.hid
if i == trans.len:
rsp.last = 1
else:
rsp.last = 0
queue = self.readRspQueues[trans.hid]
if queue.empty():
self.nonEmptyReadRspQueues.append(queue)
queue.put(rsp)
def onReadCmd(self,trans):
if trans.addr < self.base or trans.addr >= self.base + self.size:
raise TestFailure("WRONG ADDRESS addr=%d base=%d size=%d" %(trans.addr,self.base,self.size))
for i in xrange(trans.len+1):
rsp = Transaction()
rsp.data = trans.addr + i
rsp.resp = 0
rsp.hid = trans.hid
if i == trans.len:
rsp.last = 1
else:
rsp.last = 0
queue = self.readRspQueues[trans.hid]
if queue.empty():
self.nonEmptyReadRspQueues.append(queue)
queue.put(rsp)
def genReadCmd(self):
if self.doFinish:
return None
if not self.readCmdIdleRand.get():
return None
idOffset = randBits(2)
trans = Transaction()
trans.addr = self.genRandomAddress()
if random.random() < 0.1: # Random assertion of decoding error
trans.addr = 1 << 12
trans.hid = self.hid * 4 + idOffset #Each master can use 4 id
trans.region = randBits(4)
trans.len = randBits(4)
trans.size = randBits(3)
trans.burst = randBits(2)
trans.lock = randBits(1)
trans.cache = randBits(4)
trans.qos = randBits(4)
trans.prot = randBits(3)
trans.progress = 0
self.readMonitorQueues[idOffset].put(trans)
# print("Master START %d %x" % (trans.hid, trans.addr))
return trans
def genWrite(self):
idOffset = randBits(2)
writeCmd = Transaction()
writeCmd.addr = self.genRandomAddress()
if random.random() < 0.1: # Random assertion of decoding error
writeCmd.addr = 1 << 12
writeCmd.hid = self.hid * 4 + idOffset #Each master can use 4 id
writeCmd.region = randBits(4)
writeCmd.len = randBits(4)
writeCmd.size = randBits(3)
writeCmd.burst = randBits(2)
writeCmd.lock = randBits(1)
writeCmd.cache = randBits(4)
writeCmd.qos = randBits(4)
writeCmd.prot = randBits(3)
self.writeCmdQueue.put(writeCmd)
writeCmd.linkedDatas = []
for i in range(writeCmd.len + 1):
writeData = Transaction()
writeData.data = randBits(32)
writeData.strb = randBits(4)
writeData.last = 1 if i == writeCmd.len else 0
self.writeDataQueue.put(writeData)
writeCmd.linkedDatas.append(writeData)
self.idToWrites[writeCmd.hid].append(writeCmd)
def genCmd(self):
if self.closeIt or not self.cmdRandomizer.get():
return None
trans = Transaction()
if not self.burstRandomizer.get():
trans.address = randBits(9+2+2)
else:
trans.address = self.lastAddr + 1
trans.address = trans.address & ((1 << 13)-1)
trans.write = self.writeRandomizer.get() and self.writeRandomizer.get()
trans.mask = randBits(2)
trans.data = randBits(16)
trans.context = randBits(8)
self.lastAddr = trans.address
if trans.write == 0:
rsp = Transaction()
rsp.data = self.ram[trans.address*2] + (self.ram[trans.address*2+1] << 8)
rsp.context = trans.context
self.scorboard.refPush(rsp)
if rsp.data != 0:
self.nonZeroRspCounter += 1
if self.nonZeroRspCounter % 50 == 0:
print("self.nonZeroRspCounter=" + str(self.nonZeroRspCounter))
else:
for i in xrange(2):
if (trans.mask >> i) & 1 == 1:
self.ram[trans.address * 2 + i] = (trans.data >> (i*8)) & 0xFF
return trans
def genNewCmd(self):
cmd = Transaction()
cmd.hid = randBits(self.idWidth) # Each master can use 4 id
cmd.region = randBits(4)
cmd.len = randBits(4)
cmd.size = random.randint(0, self.maxDataBytes)
cmd.burst = random.randint(0, 2)
if cmd.burst == 2:
cmd.len = random.choice([2, 4, 8, 16]) - 1
else:
cmd.len = randBits(4) + (16 if random.random() < 0.1 else
0) + (32 if random.random() < 0.02 else 0)
cmd.lock = randBits(1)
cmd.cache = randBits(4)
cmd.qos = randBits(4)
cmd.prot = randBits(3)
byteCount = (1 << cmd.size) * (cmd.len + 1)
while (True):
cmd.addr = self.genRandomeAddress() & ~((1 << cmd.size) - 1)
if cmd.burst == 1:
if cmd.addr + byteCount >= (1 << self.addressWidth):
continue
if cmd.burst == 0:
start = cmd.addr
end = start + cmd.size
if cmd.burst == 1:
start = cmd.addr
end = start + byteCount
if cmd.burst == 2:
start = cmd.addr & ~(byteCount - 1)
end = start + byteCount
if self.isAddressRangeBusy(start, end):
continue
break
if self.readWriteRand.get():
cmd.write = 1
beatAddr = cmd.addr
for i in range(cmd.len + 1):
dataTrans = Transaction()
dataTrans.data = randBits(self.dataWidth)
dataTrans.strb = randBits(self.maxDataBytes)
dataTrans.last = 1 if cmd.len == i else 0
self.writeTasks.put(dataTrans)
for s in range(self.maxDataBytes):
if (dataTrans.strb >> s) & 1 == 1:
self.ram[(beatAddr & ~(self.maxDataBytes - 1)) +
s] = (dataTrans.data >> (s * 8)) & 0xFF
beatAddr = Axi4AddrIncr(beatAddr, cmd.burst, cmd.len, cmd.size)
writeRsp = Transaction()
writeRsp.resp = 0
writeRsp.hid = cmd.hid
self.reservedAddresses[writeRsp] = [start, end]
self.writeRspScoreboard.refPush(writeRsp, writeRsp.hid)
else:
cmd.write = 0
beatAddr = cmd.addr
for s in range(cmd.len + 1):
readRsp = Transaction()
addrBase = beatAddr & ~(self.maxDataBytes - 1)
readRsp.data = 0
for i in range(self.maxDataBytes):
readRsp.data |= self.ram[addrBase + i] << (i * 8)
readRsp.resp = 0
readRsp.last = 1 if cmd.len == s else 0
readRsp.hid = cmd.hid
if readRsp.last == 1:
self.reservedAddresses[readRsp] = [start, end]
self.readRspScoreboard.refPush(readRsp, readRsp.hid)
beatAddr = Axi4AddrIncr(beatAddr, cmd.burst, cmd.len, cmd.size)
self.cmdTasks.put(cmd)
def __init__(self,name,parent,dut):
Infrastructure.__init__(self,name,parent)
self.txCmdScordboard = ScorboardInOrder("txCmdScordboard",self)
self.txDataScordboard = ScorboardInOrder("txDataScordboard",self)
StreamMonitor(Stream(dut,"io_tx_cmd"), self.txCmdScordboard.uutPush, dut.clk, dut.reset)
StreamMonitor(Stream(dut, "io_tx_data"), self.txDataScordboard.uutPush, dut.clk, dut.reset)
cmd = Transaction()
cmd.ip = 0x33445566
cmd.dstPort = 0x3456
cmd.srcPort = 37984
cmd.length = 1+8
self.txCmdScordboard.refPush(cmd)
cmd = Transaction()
cmd.ip = 0x44556677
cmd.dstPort = 0x4567
cmd.srcPort = 37984
cmd.length = 1+8
self.txCmdScordboard.refPush(cmd)
for i in range(2):
data = Transaction()
data.fragment = 0x22
data.last = 0
self.txDataScordboard.refPush(data)
message = "test1234"
for f in range(len(message)):
data = Transaction()
data.fragment = ord(message[f])
data.last = (f == len(message)-1)
self.txDataScordboard.refPush(data)
def genNewCmd():
length = random.randint(1, (lengthMax // lengthMin)) * lengthMin
if self.doWriteInit:
address = self.writeInitAddress
self.writeInitAddress += length
else:
address = (random.randint(
0, addressRange // lengthMaxAll // len(self.bmbs) - 1) *
len(self.bmbs) + bmbId) * lengthMaxAll
write = random.random() < 0.5 or self.doWriteInit
beatCount = (length + bytePerBeat - 1) // bytePerBeat
context = randBits(len(bmb.cmd.payload.fragment_context))
print("* " + str(context) + " " + str(length) + " " +
str(bytePerBeat) + " " + str(beatCount))
source = 0
if not write:
cmd = Transaction()
cmd.last = True
cmd.fragment_source = source
cmd.fragment_opcode = 0
cmd.fragment_address = address
cmd.fragment_length = length - 1
cmd.fragment_data = randBits(len(
bmb.cmd.payload.fragment_data))
cmd.fragment_mask = randBits(len(
bmb.cmd.payload.fragment_mask))
cmd.fragment_context = context
cmdTasks.put(cmd)
# print("*** R" + str(bmbId) + " " + hex(cmd.fragment_context))
for beat in range(beatCount):
rsp = Transaction()
rsp.last = beat == beatCount - 1
rsp.fragment_source = source
rsp.fragment_context = context
rsp.fragment_opcode = 0
rsp.fragment_data = self.ram.read(
address + beat * bytePerBeat, bytePerBeat)
# print("*** " + str(bmbId) + " " + hex(rsp.fragment_context))
rspTasks.put(rsp)
else:
rsp = Transaction()
rsp.last = True
rsp.fragment_source = source
rsp.fragment_context = context
rsp.fragment_opcode = 0
rsp.fragment_data = None
rspTasks.put(rsp)
# print("*** " + str(bmbId) + " " + hex(rsp.fragment_context))
for beat in range(beatCount):
cmd = Transaction()
cmd.last = beat == beatCount - 1
cmd.fragment_opcode = 1
cmd.fragment_address = address
cmd.fragment_length = length - 1
cmd.fragment_source = source
cmd.fragment_context = context
cmd.fragment_data = randBits(
len(bmb.cmd.payload.fragment_data))
if self.doWriteInit:
cmd.fragment_mask = (
1 << len(bmb.cmd.payload.fragment_mask)) - 1
else:
cmd.fragment_mask = randBits(
len(bmb.cmd.payload.fragment_mask))
cmdTasks.put(cmd)
# print("*** W " + str(bmbId) + " " + hex(cmd.fragment_context) + " " + str(length))
self.ram.write(address + beat * bytePerBeat, bytePerBeat,
cmd.fragment_data, cmd.fragment_mask)
if self.writeInitAddress >= addressRange:
self.writeInitAddress = False
def genRxCmd(self):
while self.getPhase() != PHASE_SIM:
yield None
trans = Transaction()
trans.ip = 0x11223344
trans.srcPort = 0x1234
trans.dstPort = 0x1111
trans.length = 2
trans.nextDelay = 6
yield trans
trans = Transaction()
trans.ip = 0x22334455
trans.srcPort = 0x2345
trans.dstPort = 37984
trans.length = 2
trans.nextDelay = 3
yield trans
trans = Transaction()
trans.ip = 0x33445566
trans.srcPort = 0x3456
trans.dstPort = 37984
trans.length = 1
trans.nextDelay = 6
yield trans
trans = Transaction()
trans.ip = 0x44556677
trans.srcPort = 0x4567
trans.dstPort = 37984
trans.length = 1
trans.nextDelay = 6
yield trans
while True:
yield None
def genReadCmd(self):
if self.closeIt:
return None
if not self.readCmdIdleRand.get():
return None
idOffset = randBits(2)
trans = Transaction()
trans.addr = self.genRandomReadAddress()
trans.hid = self.idBase*4 + idOffset #Each master can use 4 id
trans.region = randBits(4)
trans.len = randBits(4)
trans.size = randBits(3)
trans.burst = randBits(2)
trans.lock = randBits(1)
trans.cache = randBits(4)
trans.qos = randBits(4)
trans.prot = randBits(3)
return trans
def bundleAGen():
trans = Transaction()
trans.a = randBits(8)
trans.b = randBits(1)
return trans
def genCmd(self):
if self.closeIt or not self.cmdRandomizer.get():
return None
trans = Transaction()
if not self.burstRandomizer.get():
trans.address = randBits(9 + 2 + 2)
else:
trans.address = self.lastAddr + 1
trans.address = trans.address & ((1 << 13) - 1)
trans.write = self.writeRandomizer.get() and self.writeRandomizer.get()
trans.mask = randBits(2)
trans.data = randBits(16)
trans.context = randBits(8)
self.lastAddr = trans.address
if trans.write == 0:
rsp = Transaction()
rsp.data = self.ram[trans.address *
2] + (self.ram[trans.address * 2 + 1] << 8)
rsp.context = trans.context
self.scorboard.refPush(rsp)
if rsp.data != 0:
self.nonZeroRspCounter += 1
if self.nonZeroRspCounter % 50 == 0:
print(("self.nonZeroRspCounter=" +
str(self.nonZeroRspCounter)))
else:
for i in range(2):
if (trans.mask >> i) & 1 == 1:
self.ram[trans.address * 2 + i] = (trans.data >>
(i * 8)) & 0xFF
return trans
def run(self):
global crapyConflictCounter
global normalConflictCounter
global normalTransactionCounter
yield Timer(self.baudPeriod * 10)
while crapyConflictCounter < 2 or normalConflictCounter < 3 or normalTransactionCounter < 40:
while True:
colision = False
cmd = Transaction()
cmd.mode = 0
cmd.data = randBool()
self.cmdQueue.append(cmd)
address = randBits(8) | 2
for bitId in range(8):
cmd = Transaction()
cmd.mode = 1
cmd.data = (address >> (7 - bitId)) & 1
self.cmdQueue.append(cmd)
yield clockedWaitTrue(self.clk,self.rsp.valid)
if self.rsp.payload.data != cmd.data:
assert bitId == 6
colision = True
cmd = Transaction()
cmd.mode = 3 #DROP
cmd.data = randBool()
self.cmdQueue.append(cmd)
break
if colision:
continue
for bitId in range(8):
cmd = Transaction()
cmd.mode = 1
cmd.data = True
self.cmdQueue.append(cmd)
yield clockedWaitTrue(self.clk,self.rsp.valid)
assert self.rsp.payload.data == ((cmdToData[address] >> (7-bitId)) & 1)
if random.random() < 0.75:
cmd = Transaction()
cmd.mode = 2
cmd.data = randBool()
self.cmdQueue.append(cmd)
if random.random() < 0.75: #no other master frame
if random.random() < 0.5: # With inter frame delay
yield Timer(randInt(0,self.baudPeriod*20))
else:
@coroutine
def anotherFrameEmiter():
yield self.softMaster.sendStart()
for i in range(5):
yield self.softMaster.sendBit(randBool())
yield self.softMaster.sendStop()
yield Timer(randInt(self.baudPeriod * 4, self.baudPeriod * 10))
fork(anotherFrameEmiter())
yield Timer(randInt(self.baudPeriod * 1, self.baudPeriod * 14))
normalTransactionCounter += 1
break
while self.cmdQueue:
yield Timer(self.baudPeriod * 10)
def genReadCmd(self):
if self.closeIt:
return None
if not self.readCmdIdleRand.get():
return None
idOffset = randBits(2)
trans = Transaction()
trans.addr = self.genRandomReadAddress()
trans.hid = self.idBase * 4 + idOffset #Each master can use 4 id
trans.region = randBits(4)
trans.len = randBits(4)
trans.size = randBits(3)
trans.burst = randBits(2)
trans.lock = randBits(1)
trans.cache = randBits(4)
trans.qos = randBits(4)
trans.prot = randBits(3)
return trans
def genWrite(self):
idOffset = randBits(2)
writeCmd = Transaction()
writeCmd.addr = self.genRandomWriteAddress()
writeCmd.hid = self.idBase + idOffset #Each master can use 4 id
writeCmd.region = randBits(4)
writeCmd.len = randBits(4)
writeCmd.size = randBits(3)
writeCmd.burst = randBits(2)
writeCmd.lock = randBits(1)
writeCmd.cache = randBits(4)
writeCmd.qos = randBits(4)
writeCmd.prot = randBits(3)
self.writeCmdQueue.put(writeCmd)
for i in range(writeCmd.len + 1):
writeData = Transaction()
writeData.data = writeCmd.addr + i
writeData.strb = (writeCmd.addr + i) & 0xF
writeData.last = 1 if i == writeCmd.len else 0
self.writeDataQueue.put(writeData)
def bundleAGen():
trans = Transaction()
trans.a = randBits(8)
trans.b = randBits(1)
return trans
def genRxData(self):
while self.getPhase() != PHASE_SIM:
yield None
for i in range(2):
trans = Transaction()
trans.last = 0
trans.fragment = 0x55
trans.nextDelay = 4
yield trans
trans = Transaction()
trans.last = 1
trans.fragment = 0x66
trans.nextDelay = 10
yield trans
trans = Transaction()
trans.last = 1
trans.fragment = 0x11
trans.nextDelay = 0
yield trans
trans = Transaction()
trans.last = 1
trans.fragment = 0x11
yield trans
while True:
yield None
def run(self):
global crapyConflictCounter
global normalConflictCounter
global normalTransactionCounter
yield Timer(self.baudPeriod * 10)
while crapyConflictCounter < 2 or normalConflictCounter < 3 or normalTransactionCounter < 40:
while True:
colision = False
cmd = Transaction()
cmd.mode = 0
cmd.data = randBool()
self.cmdQueue.append(cmd)
address = randBits(8) | 2
for bitId in range(8):
cmd = Transaction()
cmd.mode = 1
cmd.data = (address >> (7 - bitId)) & 1
self.cmdQueue.append(cmd)
yield clockedWaitTrue(self.clk, self.rsp.valid)
if self.rsp.payload.data != cmd.data:
assert bitId == 6
colision = True
cmd = Transaction()
cmd.mode = 3 #DROP
cmd.data = randBool()
self.cmdQueue.append(cmd)
break
if colision:
continue
for bitId in range(8):
cmd = Transaction()
cmd.mode = 1
cmd.data = True
self.cmdQueue.append(cmd)
yield clockedWaitTrue(self.clk, self.rsp.valid)
assert self.rsp.payload.data == ((cmdToData[address] >>
(7 - bitId)) & 1)
if random.random() < 0.75:
cmd = Transaction()
cmd.mode = 2
cmd.data = randBool()
self.cmdQueue.append(cmd)
if random.random() < 0.75: #no other master frame
if random.random() < 0.5: # With inter frame delay
yield Timer(randInt(0, self.baudPeriod * 20))
else:
@coroutine
def anotherFrameEmiter():
yield self.softMaster.sendStart()
for i in range(5):
yield self.softMaster.sendBit(randBool())
yield self.softMaster.sendStop()
yield Timer(
randInt(self.baudPeriod * 4, self.baudPeriod * 10))
fork(anotherFrameEmiter())
yield Timer(
randInt(self.baudPeriod * 1, self.baudPeriod * 14))
normalTransactionCounter += 1
break
while self.cmdQueue:
yield Timer(self.baudPeriod * 10)
def genWrite(self):
idOffset = randBits(2)
writeCmd = Transaction()
writeCmd.addr = self.genRandomWriteAddress()
writeCmd.hid = self.idBase + idOffset #Each master can use 4 id
writeCmd.region = randBits(4)
writeCmd.len = randBits(4)
writeCmd.size = randBits(3)
writeCmd.burst = randBits(2)
writeCmd.lock = randBits(1)
writeCmd.cache = randBits(4)
writeCmd.qos = randBits(4)
writeCmd.prot = randBits(3)
self.writeCmdQueue.put(writeCmd)
for i in xrange(writeCmd.len + 1):
writeData = Transaction()
writeData.data = writeCmd.addr + i
writeData.strb = (writeCmd.addr + i) & 0xF
writeData.last = 1 if i == writeCmd.len else 0
self.writeDataQueue.put(writeData)
