def test1(dut): dut.log.info("Cocotb test boot") random.seed(0) from cocotblib.misc import cocotbXHack cocotbXHack() cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) threads = [] threads.append(cocotb.fork(Fifo(dut).run())) threads.append(cocotb.fork(Fork(dut).run())) threads.append(cocotb.fork(DispatcherInOrder(dut).run())) threads.append(cocotb.fork(StreamFlowArbiter(dut).run())) threads.append(cocotb.fork(ArbiterInOrder(dut).run())) threads.append(cocotb.fork(ArbiterLowIdPortFirst(dut).run())) threads.append(cocotb.fork(ArbiterRoundRobin(dut).run())) threads.append(cocotb.fork(ArbiterLowIdPortNoLockFirst(dut).run())) threads.append(cocotb.fork(ArbiterLowIdPortFragmentLockFirst(dut).run())) for thread in threads: yield thread.join() # # # yield fork dut.log.info("Cocotb test done")
def test1(dut): random.seed(0) from cocotblib.misc import cocotbXHack cocotbXHack() forks = [] def map(component, net, apply, delay=0): forks.append(cocotb.fork(stim(wave, component, net, apply, delay))) wave = parse_vcd( "../../../../../../../simWorkspace/SdramXdrCtrlPlusRtlPhy/test.vcd") top = "TOP" yield Timer(0) phaseCount = getLastValue(wave, top, "phaseCount") clockPeriod = getClockPeriod(wave, top, "clk") cocotb.fork(genClock(dut.Clk, None, clockPeriod // phaseCount)) list(map(top, "ADDR", lambda v: dut.Addr <= v)) list(map(top, "BA", lambda v: dut.Ba <= v)) list(map(top, "CASn", lambda v: dut.Cas_n <= v)) list(map(top, "CKE", lambda v: dut.Cke <= v)) list(map(top, "CSn", lambda v: dut.Cs_n <= v)) list(map(top, "RASn", lambda v: dut.Ras_n <= v)) list(map(top, "WEn", lambda v: dut.We_n <= v)) for fork in forks: yield fork
def test1(dut): random.seed(0) from cocotblib.misc import cocotbXHack cocotbXHack() uut = dut.uut cocotb.fork(simulationSpeedPrinter(uut.io_axiClk)) yield loadIHex(dut,"../hex/uart.hex",uut.io_axiClk,uut.io_asyncReset) pinsecClockGen(dut) cocotb.fork(txToRxBypass(uut)) yield assertions(uut)
def test1(dut): dut.log.info("Cocotb test boot") from cocotblib.misc import cocotbXHack cocotbXHack() #random.seed(0) queue = Queue() cocotb.fork(clockProcess(dut)) cocotb.fork(cmd(dut,queue)) yield rsp(dut,queue) dut.log.info("Cocotb test done")
def test_scenario(dut): dut.log.info("Cocotb I2C IO Layer - Basic test") from cocotblib.misc import cocotbXHack cocotbXHack() delay = 300000 listOperation = list() listOperation.append( [START(), WRITE_BIT(0), WRITE_BIT(1), WRITE_BIT(0), STOP()]) listOperation.append([START(), READ_BIT(0), READ_BIT(1), STOP()]) listOperation.append([START(), WRITE_BIT(), READ_BIT(), STOP()]) listOperation.append([START(), READ_BIT(0), START(), WRITE_BIT(0), STOP()]) for operationSeq in listOperation: helperMaster = I2CMasterIoLayer(dut) helperSlave = I2CSlaveIoLayer(dut) #analyser = I2CHALAnalyser(helperMaster, operationSeq) clockDomain = ClockDomain(dut.clk, 500, dut.resetn, RESET_ACTIVE_LEVEL.LOW) cocotb.fork(clockDomain.start()) # Init IO and wait the end of the reset helperMaster.io.init() helperSlave.io.init() yield clockDomain.event_endReset.wait() #cocotb.fork(analyser.start()) cocotb.fork(helperMaster.execOperations(operationSeq)) #cocotb.fork(helperMaster.checkResponse(operationSeq)) cocotb.fork(helperSlave.execOperations(operationSeq)) #yield helperSlave.checkResponse(operationSeq) yield Timer(500000) # Stop all processes clockDomain.stop() helperSlave.stop() helperMaster.stop() # analyser.stop() yield Timer(250000) dut.log.info("Cocotb I2C Io Layer - Basic test")
def test1(dut): from cocotblib.misc import cocotbXHack cocotbXHack() random.seed(0) uut = dut.uut log = open('uartTx.log', 'w') cocotb.fork(simulationSpeedPrinter(uut.io_axiClk)) yield loadIHex(dut,"../hex/dhrystone.hex",uut.io_axiClk,uut.io_asyncReset) pinsecClockGen(dut) cocotb.fork(uartTxBypass(uut.axi_uartCtrl.uartCtrl,uut.io_axiClk,log)) yield assertions(uut,log) yield Timer(1000*10)
def test1(dut): random.seed(0) from cocotblib.misc import cocotbXHack cocotbXHack() cocotb.fork(ClockDomainAsyncResetCustom(dut.clk, dut.reset)) cocotb.fork(simulationSpeedPrinter(dut.clk)) phaseManager = PhaseManager() phaseManager.setWaitTasksEndTime(1000 * 1000) SdramTester("sdramTester", phaseManager, Stream(dut, "io_bus_cmd"), Stream(dut, "io_bus_rsp"), dut.clk, dut.reset) yield phaseManager.run()
def jtagTest(dut): from cocotblib.misc import cocotbXHack cocotbXHack() uut = dut.uut log = open('uartTx.log', 'w') cocotb.fork(simulationSpeedPrinter(uut.io_axiClk)) yield loadIHex(dut,"../hex/dummy.hex",uut.io_axiClk,uut.io_asyncReset) pinsecClockGen(dut) yield Timer(1000*10) jtag = JtagMaster(Bundle(uut,"io_jtag"),20000*4,4) yield Timer(1000*50) yield jtag.goToIdle() yield Timer(1000*8) #yield jtagBridgeWrite(jtag,0xF00F0200,0x00030000,4) #yield Timer(1000*80) # Check rom write/read via jtag yield jtagBridgeWrite(jtag,8,0x11223344,4) yield jtagBridgeWrite(jtag,10,0x00550000,1) yield jtagBridgeReadAssert(jtag,8,4,0x11553344) yield jtagBridgeReadAssert(jtag,10,2,0x1155) yield jtagBridgeWrite(jtag,0x40004FF0,0x77665544,4) yield Timer(1000*50) yield jtagBridgeReadAssert(jtag,0x40004FF0,4,0x77665544) yield jtagBridgeWrite(jtag,0x40004FF2,0x00FF0000,1) yield Timer(1000*50) yield jtagBridgeReadAssert(jtag,0x40004FF0,4,0x77FF5544) # Check RISCV APB debug module via jtag yield jtagBridgeWrite(jtag,0xF00F0200,1 << 17,4) #halt CPU yield jtagBridgeReadAssert(jtag,0xF00F0200,4,(1 << 1),0x0F) yield jtagBridgeWrite(jtag,0xF00F0008,0x99887766,4) #write R2 yield jtagBridgeReadAssert(jtag,0xF00F0008,4,0x99887766) yield jtagBridgeReadAssert(jtag,0xF00F0000+10*4,4,0x55) #Written by dummy.hex yield Timer(1000*500)
def test1(dut): dut.log.info("Cocotb test boot") from cocotblib.misc import cocotbXHack cocotbXHack() #random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, None)) for i in range(0, 1000): randSignal(dut.io_inSIntA) randSignal(dut.io_inSIntB) yield Timer(1000) ref = Ref(dut) assertEquals(dut.io_outSInt, dut.io_outSIntRef, "io_outSInt") dut.log.info("Cocotb test done")
def test1(dut): from cocotblib.misc import cocotbXHack cocotbXHack() random.seed(0) uut = dut.uut log = open('uartTx.log', 'w') cocotb.fork(simulationSpeedPrinter(uut.io_axiClk)) yield loadIHex(dut, "../hex/dhrystone.hex", uut.io_axiClk, uut.io_asyncReset) pinsecClockGen(dut) cocotb.fork(uartTxBypass(uut.axi_uartCtrl.uartCtrl, uut.io_axiClk, log)) yield assertions(uut, log) yield Timer(1000 * 10)
def test1(dut): dut.log.info("Cocotb test boot") from cocotblib.misc import cocotbXHack cocotbXHack() #random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, None)) for i in range(0,1000): randSignal(dut.io_inSIntA) randSignal(dut.io_inSIntB) yield Timer(1000) ref = Ref(dut) assertEquals(dut.io_outSInt, dut.io_outSIntRef, "io_outSInt") dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") from cocotblib.misc import cocotbXHack cocotbXHack() queueTx = Queue() queueRx = Queue() cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) cocotb.fork(sendRandomPackets(dut, queueTx, queueRx)) cocotb.fork(checkTx(dut, queueTx)) cocotb.fork(txToRxBypass(dut)) cocotb.fork(simulationSpeedPrinter(dut.clk)) yield checkCtrlReadedBytes(dut, queueRx) dut.log.info("Cocotb test done")
def test1(dut): random.seed(0) from cocotblib.misc import cocotbXHack cocotbXHack() cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) cocotb.fork(simulationSpeedPrinter(dut.clk)) phaseManager = PhaseManager() phaseManager.setWaitTasksEndTime(1000*200) StreamFifoTester("fifoA",phaseManager,Stream(dut,"fifoAPush"),Stream(dut,"fifoAPop"),bundleAGen,3000,dut.clk,dut.reset).createInfrastructure() StreamFifoTester("fifoB",phaseManager,Stream(dut,"fifoBPush"),Stream(dut,"fifoBPop"),bundleAGen,3000,dut.clk,dut.reset).createInfrastructure() yield phaseManager.run()
def test1(dut): dut.log.info("Cocotb test boot") from cocotblib.misc import cocotbXHack cocotbXHack() random.seed(0) cocotb.fork(simulationSpeedPrinter(dut.clk)) # elements = [a for a in dut.AhbRam if a._name.startswith("")] # for e in elements: # print(str(e._name)) # while True: # dut.AhbRam.ram_port1_enable <= 1 # dut.AhbRam.ram_port1_mask <= 0xF # dut.AhbRam.ram_port1_address <= 0X90 # dut.AhbRam.ram_port1_data <= 0xCAFEF00D # # dut.AhbRam.reset <= 1 # dut.AhbRam.ram_port1_enable <= 1 # yield Timer(1000) # dut.AhbRam.ram_port1_enable <= 1 # dut.AhbRam.clk <= 0 # yield Timer(1000) # dut.AhbRam.ram_port1_enable <= 1 # dut.AhbRam.clk <= 1 # yield Timer(1000) # dut.AhbRam.ram_port1_enable <= 0 # yield Timer(1000) cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) readQueue = Queue() ahb = Bundle(dut, "ahb") driver = AhbLite3MasterDriver( ahb, AhbLite3TraficGeneratorWithMemory(10, 32, readQueue), dut.clk, dut.reset) checker = AhbLite3MasterReadChecker(ahb, readQueue, dut.clk, dut.reset) terminaison = AhbLite3Terminaison(ahb, dut.clk, dut.reset) while True: yield RisingEdge(dut.clk) if checker.counter > 4000: break dut.log.info("Cocotb test done")
def test1(dut): dut.log.info("Cocotb test boot") from cocotblib.misc import cocotbXHack cocotbXHack() random.seed(0) cocotb.fork(simulationSpeedPrinter(dut.clk)) # elements = [a for a in dut.AhbRam if a._name.startswith("")] # for e in elements: # print(str(e._name)) # while True: # dut.AhbRam.ram_port1_enable <= 1 # dut.AhbRam.ram_port1_mask <= 0xF # dut.AhbRam.ram_port1_address <= 0X90 # dut.AhbRam.ram_port1_data <= 0xCAFEF00D # # dut.AhbRam.reset <= 1 # dut.AhbRam.ram_port1_enable <= 1 # yield Timer(1000) # dut.AhbRam.ram_port1_enable <= 1 # dut.AhbRam.clk <= 0 # yield Timer(1000) # dut.AhbRam.ram_port1_enable <= 1 # dut.AhbRam.clk <= 1 # yield Timer(1000) # dut.AhbRam.ram_port1_enable <= 0 # yield Timer(1000) cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) readQueue = Queue() ahb = Bundle(dut, "ahb") driver = AhbLite3MasterDriver(ahb, AhbLite3TraficGeneratorWithMemory(10, 32,readQueue), dut.clk, dut.reset) checker = AhbLite3MasterReadChecker(ahb, readQueue, dut.clk, dut.reset) terminaison = AhbLite3Terminaison(ahb, dut.clk, dut.reset) while True: yield RisingEdge(dut.clk) if checker.counter > 4000: break dut.log.info("Cocotb test done")
def jtagTest(dut): from cocotblib.misc import cocotbXHack cocotbXHack() uut = dut.uut log = open('uartTx.log', 'w') cocotb.fork(simulationSpeedPrinter(uut.io_axiClk)) yield loadIHex(dut, "../hex/dummy.hex", uut.io_axiClk, uut.io_asyncReset) pinsecClockGen(dut) yield Timer(1000 * 10) jtag = JtagMaster(Bundle(uut, "io_jtag"), 20000 * 4, 4) yield Timer(1000 * 50) yield jtag.goToIdle() yield Timer(1000 * 8) #yield jtagBridgeWrite(jtag,0xF00F0200,0x00030000,4) #yield Timer(1000*80) # Check rom write/read via jtag yield jtagBridgeWrite(jtag, 8, 0x11223344, 4) yield jtagBridgeWrite(jtag, 10, 0x00550000, 1) yield jtagBridgeReadAssert(jtag, 8, 4, 0x11553344) yield jtagBridgeReadAssert(jtag, 10, 2, 0x1155) yield jtagBridgeWrite(jtag, 0x40004FF0, 0x77665544, 4) yield Timer(1000 * 50) yield jtagBridgeReadAssert(jtag, 0x40004FF0, 4, 0x77665544) yield jtagBridgeWrite(jtag, 0x40004FF2, 0x00FF0000, 1) yield Timer(1000 * 50) yield jtagBridgeReadAssert(jtag, 0x40004FF0, 4, 0x77FF5544) # Check RISCV APB debug module via jtag yield jtagBridgeWrite(jtag, 0xF00F0200, 1 << 17, 4) #halt CPU yield jtagBridgeReadAssert(jtag, 0xF00F0200, 4, (1 << 1), 0x0F) yield jtagBridgeWrite(jtag, 0xF00F0008, 0x99887766, 4) #write R2 yield jtagBridgeReadAssert(jtag, 0xF00F0008, 4, 0x99887766) yield jtagBridgeReadAssert(jtag, 0xF00F0000 + 10 * 4, 4, 0x55) #Written by dummy.hex yield Timer(1000 * 500)
def test1(dut): random.seed(0) from cocotblib.misc import cocotbXHack cocotbXHack() cocotb.fork(ClockDomainAsyncResetCustom(dut.clk, dut.reset)) cocotb.fork(simulationSpeedPrinter(dut.clk)) phaseManager = PhaseManager() phaseManager.setWaitTasksEndTime(1000 * 2000) checker = Axi4SharedMemoryChecker("checker", phaseManager, Axi4Shared(dut, "io_axi"), 12, dut.clk, dut.reset) checker.idWidth = 2 checker.nonZeroReadRspCounterTarget = 2000 yield phaseManager.run()
def test1(dut): dut.log.info("Cocotb test boot") from cocotblib.misc import cocotbXHack cocotbXHack() #random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) while True: yield RisingEdge(dut.clk) if int(dut.io_internalClkCounter) == 2: break counter = 3 for i in range(0,1000): yield RisingEdge(dut.clk) yield RisingEdge(dut.clk) assertEquals(counter, dut.io_internalClkCounter, "io_internalClkCounter") counter = truncUInt(counter + 1, dut.io_internalClkCounter) dut.log.info("Cocotb test done")
def test1(dut): random.seed(0) from cocotblib.misc import cocotbXHack cocotbXHack() cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) cocotb.fork(simulationSpeedPrinter(dut.clk)) phaseManager = PhaseManager() phaseManager.setWaitTasksEndTime(1000 * 200) StreamFifoTester("fifoA", phaseManager, Stream(dut, "fifoAPush"), Stream(dut, "fifoAPop"), bundleAGen, 3000, dut.clk, dut.reset).createInfrastructure() StreamFifoTester("fifoB", phaseManager, Stream(dut, "fifoBPush"), Stream(dut, "fifoBPop"), bundleAGen, 3000, dut.clk, dut.reset).createInfrastructure() yield phaseManager.run()
def test1(dut): dut.log.info("Cocotb test boot") from cocotblib.misc import cocotbXHack cocotbXHack() random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) cocotb.fork(simulationSpeedPrinter(dut.clk)) phaseManager = PhaseManager() phaseManager.setWaitTasksEndTime(1000*200) checker = Axi4SharedMemoryChecker("checker",phaseManager,Axi4Shared(dut, "io_axi"),12,dut.clk,dut.reset) checker.idWidth = 2 checker.nonZeroReadRspCounterTarget = 2000 yield phaseManager.run() dut.log.info("Cocotb test done")
def testAESCore(dut): dut.log.info("Cocotb test AES Core Start") from cocotblib.misc import cocotbXHack cocotbXHack() helperAES = AESCoreHelper(dut) clockDomain = ClockDomain(helperAES.io.clk, 200, helperAES.io.resetn, RESET_ACTIVE_LEVEL.LOW) # Start clock cocotb.fork(clockDomain.start()) # Init IO and wait the end of the reset helperAES.io.init() yield clockDomain.event_endReset.wait() # start monitoring the Valid signal helperAES.io.rsp.startMonitoringValid(helperAES.io.clk) key = 0x2b7e151628aed2a6abf7158809cf4f3c data = 0x6bc1bee22e409f96e93d7e117393172a # Encrpytion helperAES.io.cmd.valid <= 1 helperAES.io.cmd.payload.key <= key helperAES.io.cmd.payload.block <= data helperAES.io.cmd.payload.enc <= 1 # do an encryption # Wait the end of the process and read the result yield helperAES.io.rsp.event_valid.wait() rtlEncryptedBlock = int(helperAES.io.rsp.event_valid.data.block) #print("RTL encrypted", hex(rtlEncryptedBlock)) helperAES.io.cmd.valid <= 0 yield RisingEdge(helperAES.io.clk) # expected result: assertEquals(0x3ad77bb40d7a3660a89ecaf32466ef97, rtlEncryptedBlock, "Encryption data wrong ") dut.log.info("Cocotb test AES Core End")
def test1(dut): random.seed(0) from cocotblib.misc import cocotbXHack cocotbXHack() forks = [] def map(component, net, apply, delay=0): forks.append(cocotb.fork(stim(wave, component, net, apply, delay))) wave = parse_vcd( "../../../../../../../simWorkspace/SdramXdrCtrlPlusRtlPhy/test.vcd") phy = "TOP.SdramXdrCtrlPlusRtlPhy" top = "TOP" yield Timer(0) phaseCount = getLastValue(wave, top, "phaseCount") dataRate = 2 phaseDelay = 0 clockPeriod = getClockPeriod(wave, top, "clk") cocotb.fork(genClock(dut.ck, dut.ck_n, clockPeriod // phaseCount)) list(map(top, "ADDR", lambda v: dut.addr <= v)) list(map(top, "BA", lambda v: dut.ba <= v)) list(map(top, "CASn", lambda v: dut.cas_n <= v)) list(map(top, "CKE", lambda v: dut.cke <= v)) list(map(top, "CSn", lambda v: dut.cs_n <= v)) list(map(top, "RASn", lambda v: dut.ras_n <= v)) list(map(top, "WEn", lambda v: dut.we_n <= v)) list(map(top, "RESETn", lambda v: dut.rst_n <= v)) list(map(top, "ODT", lambda v: dut.odt <= v)) cocotb.fork( stimPulse( wave, top, "writeEnable", lambda v: cocotb.fork( genDqs( dut.dqs, dut.dqs_n, 1 + v / clockPeriod * phaseCount * dataRate // 2, clockPeriod // (phaseCount * dataRate) * (phaseCount * dataRate - 1), clockPeriod // phaseCount)))) for fork in forks: yield fork
def test1(dut): random.seed(0) from cocotblib.misc import cocotbXHack cocotbXHack() cocotb.fork(ClockDomainAsyncResetCustom(dut.clk, dut.reset)) cocotb.fork(simulationSpeedPrinter(dut.clk)) bmbs = [Bmb(dut, "io_ports_" + str(x)) for x in range(3)] tester = BmbMemoryTester(bmbs, 16*1024, 2, 32,dut.clk,dut.reset) @cocotb.coroutine def delay(): yield RisingEdge(dut.clk) apb = Apb3(dut, "io_apb", dut.clk) yield apb.write(0x10, 0x30d) yield apb.write(0x20, 0x1060103) yield apb.write(0x24, 0x1) yield apb.write(0x28, 0x1000004) yield apb.write(0x10c, 0x0) yield apb.write(0x108, 0x400) yield apb.write(0x104, 0x8) yield apb.write(0x100, 0x0) yield apb.write(0x10c, 0x0) yield apb.write(0x108, 0x0) yield apb.write(0x104, 0x10) yield apb.write(0x100, 0x0) yield apb.write(0x10c, 0x0) yield apb.write(0x108, 0x0) yield apb.write(0x104, 0x10) yield apb.write(0x100, 0x0) yield apb.write(0x10c, 0x0) yield apb.write(0x108, 0x20) yield apb.write(0x104, 0x0) yield apb.write(0x100, 0x0) delay() tester.run = True while True: yield Timer(0x1000000)
def test1(dut): dut.log.info("Cocotb test boot") from cocotblib.misc import cocotbXHack cocotbXHack() random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) cocotb.fork(simulationSpeedPrinter(dut.clk)) phaseManager = PhaseManager() phaseManager.setWaitTasksEndTime(1000 * 2000) axiMasters = [Axi4(dut, "axiMasters_" + str(i)) for i in range(2)] axiSlaves = [Axi4(dut, "axiSlaves_" + str(i)) for i in range(2)] axiReadOnlyMasters = [ Axi4ReadOnly(dut, "axiReadOnlyMasters_" + str(i)) for i in range(2) ] axiReadOnlySlaves = [ Axi4ReadOnly(dut, "axiReadOnlySlaves_" + str(i)) for i in range(2) ] axiWriteOnlyMasters = [ Axi4WriteOnly(dut, "axiWriteOnlyMasters_" + str(i)) for i in range(2) ] axiWriteOnlySlaves = [ Axi4WriteOnly(dut, "axiWriteOnlySlaves_" + str(i)) for i in range(2) ] axiSharedMasters = [ Axi4Shared(dut, "axiSharedMasters_" + str(i)) for i in range(2) ] axiSharedSlaves = [ Axi4Shared(dut, "axiSharedSlaves_" + str(i)) for i in range(2) ] # Instanciate master sides for idx, axiMaster in enumerate(axiMasters): WriteOnlyMasterDriver("Axi4WriteMasterDriver" + str(idx), phaseManager, 0 + idx * 4, axiMaster, dut).createInfrastructure() ReadOnlyMasterDriver("Axi4ReadMasterDriver" + str(idx), phaseManager, 0 + idx * 4, axiMaster, dut).createInfrastructure() ReadOnlyMasterMonitor("Axi4ReadMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure() WriteOnlyMasterMonitor("Axi4WriteMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure() for idx, axiMaster in enumerate(axiReadOnlyMasters): ReadOnlyMasterDriver("ReadOnlyMasterDriver" + str(idx), phaseManager, 4 + idx * 4, axiMaster, dut).createInfrastructure() ReadOnlyMasterMonitor("ReadOnlyMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure() for idx, axiMaster in enumerate(axiWriteOnlyMasters): WriteOnlyMasterDriver("WriteOnlyMasterDriver" + str(idx), phaseManager, 8 + idx * 4, axiMaster, dut).createInfrastructure() WriteOnlyMasterMonitor("WriteOnlyMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure() for idx, axiMaster in enumerate(axiSharedMasters): SharedMasterDriver("SharedMasterDriver" + str(idx), phaseManager, 12 + idx * 4, axiMaster, dut).createInfrastructure() SharedMasterMonitor("SharedMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure() for idx, axiSlave in enumerate(axiSlaves): WriteOnlySlaveDriver(axiSlave, 0x0000 + idx * 0x0800, 0x0800, dut).createInfrastructure() ReadOnlySlaveDriver(axiSlave, 0x0000 + idx * 0x0800, 0x0800, dut).createInfrastructure() WriteDataMonitor("Axi4DataSlaveMonitor" + str(idx), phaseManager, axiSlave, dut).createInfrastructure() for idx, axiSlave in enumerate(axiReadOnlySlaves): ReadOnlySlaveDriver(axiSlave, 0x2000 + idx * 0x0800, 0x0800, dut).createInfrastructure() for idx, axiSlave in enumerate(axiWriteOnlySlaves): WriteOnlySlaveDriver(axiSlave, 0x3000 + idx * 0x0800, 0x0800, dut).createInfrastructure() WriteDataMonitor("WriteOnlySlaveMonitor" + str(idx), phaseManager, axiSlave, dut).createInfrastructure() for idx, axiSlave in enumerate(axiSharedSlaves): SharedSlaveDriver(axiSlave, 0x1000 + idx * 0x0800, 0x0800, dut).createInfrastructure() SharedDataMonitor("SharedSlaveMonitor" + str(idx), phaseManager, axiSlave, dut).createInfrastructure() # cocotb.log.error("miaou") # Run until completion yield phaseManager.run() # yield Timer(1000*6000) dut.log.info("Cocotb test done")
def testMD5EngineStd(dut): dut.log.info("Cocotb test MD5 Engine Std") from cocotblib.misc import cocotbXHack cocotbXHack() helperMD5 = MD5EngineStdHelper(dut) clockDomain = ClockDomain(helperMD5.io.clk, 200) # Start clock cocotb.fork(clockDomain.start()) # Init IO and wait the end of the reset helperMD5.io.initIO() #yield clockDomain.event_endReset.wait() yield RisingEdge(helperMD5.io.clk) # start monitoring rsp helperMD5.io.rsp.startMonitoringValid(helperMD5.io.clk) # Fix patterns msgs = [ [ 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ], [ 0x00000080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ], [ 0x80636261000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001800000000 ], [ 0x34333231383736353231303936353433303938373433323138373635323130393635343330393837343332313837363532313039363534333039383734333231, 0x38373635323130393635343330393837000000800000000000000000000000000000000000000000000000000000000000000000000000000000028000000000 ] ] digests = [ 0x031F1DAC6EA58ED01FAB67B774317791, 0xD98C1DD404B2008F980980E97E42F8EC, 0x98500190B04FD23C7D3F96D6727FE128, 0xA2F4ED5755C9E32B2EDA49AC7AB60721 ] # Process all pattern indexPattern = 0 for msgPattern in msgs: # Init MD5 yield RisingEdge(helperMD5.io.clk) helperMD5.io.init <= 1 yield RisingEdge(helperMD5.io.clk) helperMD5.io.init <= 0 yield RisingEdge(helperMD5.io.clk) for msgBlock in msgPattern: # Hash data helperMD5.io.cmd.valid <= 1 helperMD5.io.cmd.payload.block <= msgBlock # wait the end of the encryption yield helperMD5.io.rsp.event_valid.wait() helperMD5.io.cmd.valid <= 0 rtlDigest = "{0:0>4X}".format( int(str(helperMD5.io.rsp.payload.digest), 2)) yield RisingEdge(helperMD5.io.clk) assertEquals(int(rtlDigest, 16), digests[indexPattern], "Wrong digest") yield RisingEdge(helperMD5.io.clk) yield Timer(50000) indexPattern += 1
import operator from cocotb.regression import TestFactory from spinal.RiscvTester.RiscvTester import isaTestsMemory, isaTestsMulDiv, isaTestsBase, testIsa from cocotblib.misc import cocotbXHack cocotbXHack() factory = TestFactory(testIsa) factory.add_option( "iHexPath", reduce(operator.add, [isaTestsBase, isaTestsMemory, isaTestsMulDiv])) factory.generate_tests()
def test1(dut): dut.log.info("Cocotb test boot") from cocotblib.misc import cocotbXHack cocotbXHack() cocotb.fork(genCLock(dut)) cocotb.fork(simulationSpeedPrinter(dut.clk)) apb = Apb3(dut, "io_apb", dut.clk) apb.idle() dut.io_xip_cmd_valid <= False # bus.nonStopWrite(streamUnbuffered.data, bitOffset=0) # bus.nonStopWrite(streamUnbuffered.write, bitOffset=8) # bus.nonStopWrite(streamUnbuffered.read, bitOffset=9) # bus.nonStopWrite(streamUnbuffered.kind, bitOffset=11) # bus.read(fifoAvailability, address=baseAddress + 4, 16) @cocotb.coroutine def waitNotFull(): while True: readThread = apb.read(4) yield readThread if (int(readThread.retval) >> 16) != 0: break @cocotb.coroutine def waitEmpty(): while True: readThread = apb.read(4) yield readThread if (int(readThread.retval) >> 16) == 32: break @cocotb.coroutine def start(): yield waitNotFull() yield apb.write(0, 0x880) @cocotb.coroutine def stop(): yield waitNotFull() yield apb.write(0, 0x800) @cocotb.coroutine def write(data): yield waitNotFull() yield apb.write(0, 0x100 | data) @cocotb.coroutine def readPush(length): for i in range(length): yield waitNotFull() yield apb.write(0, 0x200) @cocotb.coroutine def read(result): readSent = 0 for i in range(len(result)): while True: if readSent != len(result): readThread = apb.read(4) yield readThread if int(readThread.retval) >> 1 != 0: yield apb.write(0, 0x200) readSent += 1 readThread = apb.read(0) yield readThread ret = int(readThread.retval) if ret >> 31 != 0: result[i] = ret & 0xFF break @cocotb.coroutine def writeEnable(): yield start() yield write(0x06) yield stop() @cocotb.coroutine def readStatus(result): yield start() yield write(0x05) yield read(result) yield stop() @cocotb.coroutine def whileFlashBusy(): while True: pull = [0] yield readStatus(pull) if (pull[0] & 0x01) == 0: break @cocotb.coroutine def clearStatusRegister(): yield start() yield write(0x50) yield stop() @cocotb.coroutine def fastRead(addr, tab): yield start() yield write(0x0B) yield write((addr >> 16) & 0xFF) yield write((addr >> 8) & 0xFF) yield write((addr >> 0) & 0xFF) yield write(0xFF) yield read(tab) yield stop() @cocotb.coroutine def programPage(addr, data): yield writeEnable() yield start() yield write(0x02) yield write((addr >> 16) & 0xFF) yield write((addr >> 8) & 0xFF) yield write((addr >> 0) & 0xFF) for b in data: yield write(b) yield stop() yield whileFlashBusy() yield clearStatusRegister() @cocotb.coroutine def writeRegister(id, data): yield start() yield write(id) yield write(data) yield stop() @cocotb.coroutine def sectorErase(addr): yield writeEnable() yield start() yield write(0xD8) yield write((addr >> 16) & 0xFF) yield write((addr >> 8) & 0xFF) yield write((addr >> 0) & 0xFF) yield stop() yield whileFlashBusy() @cocotb.coroutine def readVolatileConfig(tab): yield start() yield write(0x85) yield read(tab) yield stop() @cocotb.coroutine def writeVolatileConfig(tab): yield writeEnable() yield start() yield write(0x81) yield write(tab) yield stop() dut.vcc <= 0 for i in range(300): yield Timer(10000) dut.vcc <= i * 10 # bus.drive(config.kind, baseAddress + 8, bitOffset=0) # bus.drive(config.mod, baseAddress + 8, bitOffset=4) yield apb.write(8, 0) yield apb.write(8, 0) # bus.drive(config.sclkToogle, baseAddress + 0x20) # bus.drive(config.fullRate, baseAddress + 0x20, bitOffset=31) yield apb.write(0x20, 2) # bus.drive(config.ss.setup, baseAddress + 0x24) yield apb.write(0x24, 14) # bus.drive(config.ss.hold, baseAddress + 0x28) yield apb.write(0x28, 18) # bus.drive(config.ss.disable, baseAddress + 0x2C) yield apb.write(0x2C, 22) # while True: yield start() yield write(0x9F) tab = [0] * 3 yield read(tab) print(tab) yield stop() # XIP = 0 dummy = 8 yield start() yield write(0x81) yield write(0x83) yield stop() # Write lock register # yield writeRegister(0xE5, ) yield programPage(0x1100, list(range(256))) yield programPage(0x1200, list(range(0x10, 0x20))) tab = [0] * 5 yield fastRead(0x1105, tab) print(tab) assert (tab == [5, 6, 7, 8, 9]) tab = [0] * 5 yield fastRead(0x1205, tab) print(tab) assert (tab == [0x15, 0x16, 0x17, 0x18, 0x19]) tab = [0] * 10 yield fastRead(0x11FA, tab) print(tab) assert (tab == [ 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0x10, 0x11, 0x12, 0x13 ]) # bus.drive(enable, baseAddress + 0x40) # bus.drive(instructionData, baseAddress + 0x44, bitOffset=0) # bus.drive(instructionEnable, baseAddress + 0x44, bitOffset=8) # bus.drive(dummyData, baseAddress + 0x44, bitOffset=16) # bus.drive(dummyCount, baseAddress + 0x44, bitOffset=24) yield waitEmpty() yield apb.write(0x44, 0x00FF010B) yield apb.write(0x40, 0x1) @cocotb.coroutine def xipCmd(addr): dut.io_xip_cmd_valid <= True dut.io_xip_cmd_payload <= addr yield waitClockedCond(dut.clk, lambda: dut.io_xip_cmd_ready == True) dut.io_xip_cmd_valid <= False xipRspRef = Queue() @cocotb.coroutine def xipRspScoreboard(): while True: yield waitClockedCond(dut.clk, lambda: dut.io_xip_rsp_valid == True) assert (not xipRspRef.empty()) assert (xipRspRef.get_nowait() == int(dut.io_xip_rsp_payload)) cocotb.fork(xipRspScoreboard()) @cocotb.coroutine def xip(addr, value): xipRspRef.put(value) yield xipCmd(addr) yield xip(0x1100, 0x03020100) yield xip(0x1104, 0x07060504) yield xip(0x1108, 0x0B0A0908) yield xip(0x1100, 0x03020100) yield xip(0x1104, 0x07060504) yield xip(0x1108, 0x0B0A0908) yield xip(0x1100, 0x03020100) yield xip(0x1104, 0x07060504) yield xip(0x1108, 0x0B0A0908) yield waitClockedCond(dut.clk, lambda: xipRspRef.empty()) yield apb.write(0x40, 0x0) yield stop() yield sectorErase(0x1205) tab = [0] * 10 yield fastRead(0x11FA, tab) print(tab) assert (tab == [0xFF] * 10) yield waitEmpty() tab = [0, 0] yield readVolatileConfig(tab) print(tab) yield Timer(1000000) dut.log.info("Cocotb test done")
def testHMACCore_MD5(dut): dut.log.info("Cocotb test HMAC - MD5 Core Std") from cocotblib.misc import cocotbXHack cocotbXHack() helperHMAC = HMACCoreStdHelper(dut) clockDomain = ClockDomain(helperHMAC.io.clk, 200, helperHMAC.io.resetn, RESET_ACTIVE_LEVEL.LOW) # Start clock cocotb.fork(clockDomain.start()) # Init IO and wait the end of the reset helperHMAC.io.initIO() yield clockDomain.event_endReset.wait() # start monitoring rsp helperHMAC.io.rsp.startMonitoringValid(helperHMAC.io.clk) helperHMAC.io.cmd.startMonitoringReady(helperHMAC.io.clk) msgPattern = [randomword(100 - size) for size in range(1, 100)] keyPattern = [randomword(30) for _ in range(1, 100)] #msgPattern = ["11111111222222223333333344444444555555556666666677777777"] #keyPattern = ["gxmlzvkwyuvtkyfhgliszczfdscqyh"] for index in range(0, len(msgPattern)): hexMsg = "".join([format(ord(c), "x") for c in msgPattern[index]]) hexKey = "".join([format(ord(c), "x") for c in keyPattern[index]]) print("key : ", keyPattern[index]) print("key : ", hexKey) print("msg : ", msgPattern[index]) print("msg : ", hexMsg) ## key padding to get a key of the size of the md5 block if (len(hexKey) < 128): hexKey = hexKey + "0" * (128 - len(hexKey)) # Init yield RisingEdge(helperHMAC.io.clk) helperHMAC.io.init <= 1 yield RisingEdge(helperHMAC.io.clk) helperHMAC.io.init <= 0 yield RisingEdge(helperHMAC.io.clk) while (hexMsg != None): if len(hexMsg) > 8: block = endianessWord(hexMsg[:8]) hexMsg = hexMsg[8:] isLast = 0 sizeLast = 0 else: block = endianessWord(hexMsg + "0" * (8 - len(hexMsg))) isLast = 1 sizeLast = (len(hexMsg) / 2) - 1 hexMsg = None helperHMAC.io.cmd.valid <= 1 helperHMAC.io.cmd.payload.fragment_msg <= int(block, 16) helperHMAC.io.cmd.payload.fragment_key <= int( endianess(hexKey), 16) helperHMAC.io.cmd.payload.fragment_size <= sizeLast helperHMAC.io.cmd.payload.last <= isLast if isLast == 1: yield helperHMAC.io.rsp.event_valid.wait() rtlhmac = hex(int( helperHMAC.io.rsp.event_valid.data.hmac))[2:-1] if (len(rtlhmac) != 32): rtlhmac = "0" * (32 - len(rtlhmac)) + rtlhmac else: yield helperHMAC.io.cmd.event_ready.wait() helperHMAC.io.cmd.valid <= 0 rtlhmac = endianess(rtlhmac) print("index : ", index) modelHmac = hmac.new(keyPattern[index], msgPattern[index], hashlib.md5).hexdigest() print("hmac : ", rtlhmac, modelHmac, int(rtlhmac, 16) == int(modelHmac, 16)) print() # assertEquals(int(rtlhmac, 16), int(modelHmac, 16), "Wrong hmac hash value computed ") yield Timer(50000)
def testMD5CoreStd(dut): dut.log.info("Cocotb test MD5 Core Std") from cocotblib.misc import cocotbXHack cocotbXHack() helperMD5 = MD5CoreStdHelper(dut) clockDomain = ClockDomain(helperMD5.io.clk, 200, helperMD5.io.resetn, RESET_ACTIVE_LEVEL.LOW) # Start clock cocotb.fork(clockDomain.start()) # Init IO and wait the end of the reset helperMD5.io.initIO() yield clockDomain.event_endReset.wait() # start monitoring rsp helperMD5.io.rsp.startMonitoringValid(helperMD5.io.clk) helperMD5.io.cmd.startMonitoringReady(helperMD5.io.clk) # Fix patterns # msgPattern = [randomword(100 - size) for size in range(1, 100)] #msgPattern = ["11111111222222223333333344444444555555556666666677777777"] for tmpMsg in msgPattern: hexMsg = "".join([format(ord(c), "x") for c in tmpMsg]) # Init MD5 yield RisingEdge(helperMD5.io.clk) helperMD5.io.init <= 1 yield RisingEdge(helperMD5.io.clk) helperMD5.io.init <= 0 yield RisingEdge(helperMD5.io.clk) block = 0 rtlHash = 0 while (hexMsg != None): isLast = 0 sizeLast = 0 if len(hexMsg) > 8: block = endianessWord(hexMsg[:8]) hexMsg = hexMsg[8:] isLast = 0 else: block = endianessWord(hexMsg + "0" * (8 - len(hexMsg))) isLast = 1 sizeLast = (len(hexMsg) / 2) - 1 hexMsg = None helperMD5.io.cmd.valid <= 1 helperMD5.io.cmd.payload.fragment_msg <= int(block, 16) helperMD5.io.cmd.payload.fragment_size <= sizeLast helperMD5.io.cmd.payload.last <= isLast if isLast == 1: yield helperMD5.io.rsp.event_valid.wait() tmp = hex(int(helperMD5.io.rsp.event_valid.data.digest))[2:-1] if (len(tmp) != 32): tmp = "0" * (32 - len(tmp)) + tmp else: yield helperMD5.io.cmd.event_ready.wait() helperMD5.io.cmd.valid <= 0 yield RisingEdge(helperMD5.io.clk) rtlHash = endianess(tmp) # Check result m = hashlib.md5(tmpMsg) modelHash = m.hexdigest() assertEquals(int(rtlHash, 16), int(modelHash, 16), "Wrong MD5 hash value computed ") #print("hash-model: ", int(rtlHash, 16) == int(modelHash, 16) , " :" , rtlHash, " - ", modelHash , " -- : ", tmpMsg) yield Timer(50000)
def test1(dut): dut.log.info("Cocotb test boot") from cocotblib.misc import cocotbXHack cocotbXHack() random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) cocotb.fork(simulationSpeedPrinter(dut.clk)) phaseManager = PhaseManager() phaseManager.setWaitTasksEndTime(1000*2000) axiMasters = [Axi4(dut, "axiMasters_" + str(i)) for i in range(2)] axiSlaves = [Axi4(dut, "axiSlaves_" + str(i)) for i in range(2)] axiReadOnlyMasters = [Axi4ReadOnly(dut, "axiReadOnlyMasters_" + str(i)) for i in range(2)] axiReadOnlySlaves = [Axi4ReadOnly(dut, "axiReadOnlySlaves_" + str(i)) for i in range(2)] axiWriteOnlyMasters = [Axi4WriteOnly(dut, "axiWriteOnlyMasters_" + str(i)) for i in range(2)] axiWriteOnlySlaves = [Axi4WriteOnly(dut, "axiWriteOnlySlaves_" + str(i)) for i in range(2)] axiSharedMasters = [Axi4Shared(dut, "axiSharedMasters_" + str(i)) for i in range(2)] axiSharedSlaves = [Axi4Shared(dut, "axiSharedSlaves_" + str(i)) for i in range(2)] # Instanciate master sides for idx,axiMaster in enumerate(axiMasters): WriteOnlyMasterDriver("Axi4WriteMasterDriver" + str(idx),phaseManager,0 + idx * 4, axiMaster, dut).createInfrastructure() ReadOnlyMasterDriver("Axi4ReadMasterDriver" + str(idx),phaseManager,0 + idx * 4, axiMaster, dut).createInfrastructure() ReadOnlyMasterMonitor("Axi4ReadMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure() WriteOnlyMasterMonitor("Axi4WriteMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure() for idx,axiMaster in enumerate(axiReadOnlyMasters): ReadOnlyMasterDriver("ReadOnlyMasterDriver" + str(idx),phaseManager,4 + idx * 4, axiMaster, dut).createInfrastructure() ReadOnlyMasterMonitor("ReadOnlyMasterMonitor" + str(idx),phaseManager,axiMaster,dut).createInfrastructure() for idx,axiMaster in enumerate(axiWriteOnlyMasters): WriteOnlyMasterDriver("WriteOnlyMasterDriver" + str(idx),phaseManager,8 + idx * 4, axiMaster, dut).createInfrastructure() WriteOnlyMasterMonitor("WriteOnlyMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure() for idx,axiMaster in enumerate(axiSharedMasters): SharedMasterDriver("SharedMasterDriver" + str(idx),phaseManager,12 + idx * 4, axiMaster, dut).createInfrastructure() SharedMasterMonitor("SharedMasterMonitor" + str(idx), phaseManager, axiMaster, dut).createInfrastructure() for idx,axiSlave in enumerate(axiSlaves): WriteOnlySlaveDriver(axiSlave,0x0000 + idx*0x0800,0x0800, dut).createInfrastructure() ReadOnlySlaveDriver(axiSlave,0x0000 + idx*0x0800,0x0800, dut).createInfrastructure() WriteDataMonitor("Axi4DataSlaveMonitor" + str(idx), phaseManager, axiSlave, dut).createInfrastructure() for idx,axiSlave in enumerate(axiReadOnlySlaves): ReadOnlySlaveDriver(axiSlave,0x2000 + idx*0x0800,0x0800, dut).createInfrastructure() for idx,axiSlave in enumerate(axiWriteOnlySlaves): WriteOnlySlaveDriver(axiSlave,0x3000 + idx*0x0800,0x0800, dut).createInfrastructure() WriteDataMonitor("WriteOnlySlaveMonitor" + str(idx),phaseManager,axiSlave,dut).createInfrastructure() for idx,axiSlave in enumerate(axiSharedSlaves): SharedSlaveDriver(axiSlave,0x1000 + idx*0x0800,0x0800, dut).createInfrastructure() SharedDataMonitor("SharedSlaveMonitor" + str(idx), phaseManager, axiSlave, dut).createInfrastructure() # cocotb.log.error("miaou") # Run until completion yield phaseManager.run() # yield Timer(1000*6000) dut.log.info("Cocotb test done")
def test1(dut): random.seed(0) from cocotblib.misc import cocotbXHack cocotbXHack() cocotb.fork( ClockDomainAsyncResetCustom(3300, dut.clk0, dut.serdesClk0, dut.serdesClk90, dut.rst0)) cocotb.fork(simulationSpeedPrinter(dut.clk0)) bmbs = [Bmb(dut, "system_io_ports_" + str(x)) for x in range(1)] tester = BmbMemoryTester(bmbs, 64 * 1024, 8, 32, dut.clk0, dut.rst0, True) @cocotb.coroutine def delay(): yield RisingEdge(dut.clk0) ctrlApb = Apb3(dut, "system_io_ctrlApb", dut.clk0) phyApb = Apb3(dut, "system_io_phyApb", dut.clk0) @cocotb.coroutine def apbWrite(address, data): yield ctrlApb.write(address, data) yield apbWrite(0x0, 0x20001) yield apbWrite(0x4, 0x2) yield apbWrite(0x10, 0x491) yield apbWrite(0x20, 0x1170205) yield apbWrite(0x24, 0x2) yield apbWrite(0x28, 0x2030102) yield apbWrite(0x30, 0x5) yield apbWrite(0x34, 0x103) yield apbWrite(0x110, 0x0) yield apbWrite(0x110, 0x1) yield apbWrite(0x110, 0x3) yield apbWrite(0x10c, 0x2) yield apbWrite(0x108, 0x200) yield apbWrite(0x104, 0x0) yield apbWrite(0x100, 0x0) yield apbWrite(0x10c, 0x3) yield apbWrite(0x108, 0x0) yield apbWrite(0x104, 0x0) yield apbWrite(0x100, 0x0) yield apbWrite(0x10c, 0x1) yield apbWrite(0x108, 0x44) yield apbWrite(0x104, 0x0) yield apbWrite(0x100, 0x0) yield apbWrite(0x10c, 0x0) yield apbWrite(0x108, 0x310) yield apbWrite(0x104, 0x0) yield apbWrite(0x100, 0x0) yield apbWrite(0x10c, 0x0) yield apbWrite(0x108, 0x400) yield apbWrite(0x104, 0xc) yield apbWrite(0x100, 0x0) # yield ctrlApb.write(0x000, 0x00) #phase command = 0 # yield ctrlApb.write(0x110, 0x00) #reset # yield ctrlApb.delay(10) # yield ctrlApb.write(0x110, 0x01) #!reset # yield ctrlApb.delay(10) # yield ctrlApb.write(0x110, 0x03) #cke # yield ctrlApb.delay(10) # # # @cocotb.coroutine # def command(cmd, bank, address): # yield ctrlApb.write(0x10C, bank) # yield ctrlApb.write(0x108, address) # yield ctrlApb.write(0x104, cmd) # yield ctrlApb.write(0x100, 0) # yield ctrlApb.delay(10) # # CKE = 1 << 0 # CSn = 1 << 1 # RASn = 1 << 2 # CASn = 1 << 3 # WEn = 1 << 4 # # PRE = CKE | CASn # REF = CKE | WEn # MOD = CKE # ZQCL = CKE | RASn | CASn # # CL = 2 # 5 # # # yield command(MOD, 2, 0) # yield command(MOD, 3, 0) # yield command(MOD, 1, 0) # yield command(MOD, 0, (1 << 9) | 0x100 | ((CL & 1) << 2) | ((CL & 0xE) << 3)) #DDL reset # yield command(ZQCL, 0, 0x400) # yield ctrlApb.delay(1000) delay() tester.run = True while True: yield Timer(0x1000000)
import operator from cocotb.regression import TestFactory from spinal.RiscvTester.RiscvTester import isaTestsMemory, isaTestsMulDiv, isaTestsBase, testIsa from cocotblib.misc import cocotbXHack cocotbXHack() factory = TestFactory(testIsa) factory.add_option("iHexPath", reduce(operator.add, [isaTestsBase, isaTestsMemory, isaTestsMulDiv])) factory.generate_tests()
def testDESCore(dut): dut.log.info("Cocotb test DES Core") from cocotblib.misc import cocotbXHack cocotbXHack() helperDES = DESCoreStdHelper(dut) clockDomain = ClockDomain(helperDES.io.clk, 200, helperDES.io.resetn, RESET_ACTIVE_LEVEL.LOW) # Start clock cocotb.fork(clockDomain.start()) # Init IO and wait the end of the reset helperDES.io.init() yield clockDomain.event_endReset.wait() # start monitoring the Valid signal helperDES.io.rsp.startMonitoringValid(helperDES.io.clk) for _ in range(0, 5): # Vector test ... #key = 0xAABB09182736CCDD #data = 0x123456ABCD132536 #data = 0xC0B7A8D05F3A829C # Gen random value key = randBits(64) data = randBits(64) # Encrpytion helperDES.io.cmd.valid <= 1 helperDES.io.cmd.payload.key <= key helperDES.io.cmd.payload.block <= data helperDES.io.cmd.payload.enc <= 1 # do an encryption # Wait the end of the process and read the result yield helperDES.io.rsp.event_valid.wait() rtlEncryptedBlock = int(helperDES.io.rsp.event_valid.data.block) #print("RTL encrypted", hex(rtlEncryptedBlock)) helperDES.io.cmd.valid <= 0 yield RisingEdge(helperDES.io.clk) # Encrpytion helperDES.io.cmd.valid <= 1 helperDES.io.cmd.payload.key <= key helperDES.io.cmd.payload.block <= rtlEncryptedBlock helperDES.io.cmd.payload.enc <= 0 # do a decryption # Wait the end of the process and read the result yield helperDES.io.rsp.event_valid.wait() rtlDecryptedBlock = int(helperDES.io.rsp.event_valid.data.block) #print("RTL decrypted", hex(rtlDecryptedBlock)) helperDES.io.cmd.valid <= 0 yield RisingEdge(helperDES.io.clk) # Encrypted data with the model k = des(int_2_String(key), CBC, "\0\0\0\0\0\0\0\0", pad=None, padmode=PAD_PKCS5) refEncryptedOutput = (k.encrypt(int_2_String(data))).encode('hex')[:16] # print("Ref encrypted ", refEncryptedOutput) # compare result assertEquals(int(refEncryptedOutput, 16), rtlEncryptedBlock, "Encryption data wrong ") assertEquals(rtlDecryptedBlock, data, "Decryption data wrong ") dut.log.info("Cocotb end test DES Core")