def getTop():
top = Component('aegean_top')
top.addPackage('ieee','std_logic_1164')
top.addPackage('ieee','numeric_std')
top.addPackage('work','config')
top.addPackage('work','ocp')
return top
def getNocNode(self):
nocNode = Component('noc_node')
nocNode.entity.addGeneric('MASTER', 'boolean', 'false')
nocNode.entity.addPort('clk')
nocNode.entity.addPort('reset')
nocNode.entity.addPort('supervisor')
nocNode.entity.addPort('run')
nocNode.entity.addPort('master_run', 'out', 'std_logic')
nocNode.entity.addPort('proc_m', 'in', 'ocp_io_m')
nocNode.entity.addPort('proc_s', 'out', 'ocp_io_s')
nocNode.entity.addPort('spm_m', 'out', 'mem_if_master')
nocNode.entity.addPort('spm_s', 'in', 'mem_if_slave')
nocNode.entity.addPort('irq', 'out', 'std_logic_vector', 2)
nocNode.entity.addPort('north_in_f', 'in', 'channel_forward')
nocNode.entity.addPort('north_in_b', 'out', 'channel_backward')
nocNode.entity.addPort('south_in_f', 'in', 'channel_forward')
nocNode.entity.addPort('south_in_b', 'out', 'channel_backward')
nocNode.entity.addPort('east_in_f', 'in', 'channel_forward')
nocNode.entity.addPort('east_in_b', 'out', 'channel_backward')
nocNode.entity.addPort('west_in_f', 'in', 'channel_forward')
nocNode.entity.addPort('west_in_b', 'out', 'channel_backward')
nocNode.entity.addPort('north_out_f', 'out', 'channel_forward')
nocNode.entity.addPort('north_out_b', 'in', 'channel_backward')
nocNode.entity.addPort('south_out_f', 'out', 'channel_forward')
nocNode.entity.addPort('south_out_b', 'in', 'channel_backward')
nocNode.entity.addPort('east_out_f', 'out', 'channel_forward')
nocNode.entity.addPort('east_out_b', 'in', 'channel_backward')
nocNode.entity.addPort('west_out_f', 'out', 'channel_forward')
nocNode.entity.addPort('west_out_b', 'in', 'channel_backward')
return nocNode
def getArbiter(numPorts, ocpBurstAddrWidth):
arbiter = Component('TdmArbiterWrapper')
arbiter.entity.addPort('clk')
arbiter.entity.addPort('reset')
arbiter.entity.addPort('io_slave_M_Cmd', 'out', 'std_logic_vector', 3)
arbiter.entity.addPort('io_slave_M_Addr', 'out', 'std_logic_vector',
ocpBurstAddrWidth)
arbiter.entity.addPort('io_slave_M_Data', 'out', 'std_logic_vector', 32)
arbiter.entity.addPort('io_slave_M_DataValid', 'out', 'std_logic')
arbiter.entity.addPort('io_slave_M_DataByteEn', 'out', 'std_logic_vector',
4)
arbiter.entity.addPort('io_slave_S_Resp', 'in', 'std_logic_vector', 2)
arbiter.entity.addPort('io_slave_S_Data', 'in', 'std_logic_vector', 32)
arbiter.entity.addPort('io_slave_S_CmdAccept', 'in', 'std_logic')
arbiter.entity.addPort('io_slave_S_DataAccept', 'in', 'std_logic')
for i in range(0, numPorts):
arbiter.entity.addPort('io_master_' + str(i) + '_M_Cmd', 'in',
'std_logic_vector', 3)
arbiter.entity.addPort('io_master_' + str(i) + '_M_Addr', 'in',
'std_logic_vector', ocpBurstAddrWidth)
arbiter.entity.addPort('io_master_' + str(i) + '_M_Data', 'in',
'std_logic_vector', 32)
arbiter.entity.addPort('io_master_' + str(i) + '_M_DataValid', 'in',
'std_logic')
arbiter.entity.addPort('io_master_' + str(i) + '_M_DataByteEn', 'in',
'std_logic_vector', 4)
arbiter.entity.addPort('io_master_' + str(i) + '_S_Resp', 'out',
'std_logic_vector', 2)
arbiter.entity.addPort('io_master_' + str(i) + '_S_Data', 'out',
'std_logic_vector', 32)
arbiter.entity.addPort('io_master_' + str(i) + '_S_CmdAccept', 'out',
'std_logic')
arbiter.entity.addPort('io_master_' + str(i) + '_S_DataAccept', 'out',
'std_logic')
return arbiter
def getPatmos(IPType, ocpBurstAddrWidth=21):
patmos = Component(IPType + 'PatmosCore')
patmos.entity.addPort('clk')
patmos.entity.addPort('reset')
patmos.entity.addPort('io_superMode', 'out', 'std_logic')
patmos.entity.addPort('io_comConf_M_Cmd', 'out', 'std_logic_vector', 3)
patmos.entity.addPort('io_comConf_M_Addr', 'out', 'std_logic_vector', 32)
patmos.entity.addPort('io_comConf_M_Data', 'out', 'std_logic_vector', 32)
patmos.entity.addPort('io_comConf_M_ByteEn', 'out', 'std_logic_vector', 4)
patmos.entity.addPort('io_comConf_M_RespAccept', 'out', 'std_logic')
patmos.entity.addPort('io_comConf_S_Resp', 'in', 'std_logic_vector', 2)
patmos.entity.addPort('io_comConf_S_Data', 'in', 'std_logic_vector', 32)
patmos.entity.addPort('io_comConf_S_CmdAccept', 'in', 'std_logic')
patmos.entity.addPort('io_comConf_S_Reset_n', 'in', 'std_logic')
patmos.entity.addPort('io_comConf_S_Flag', 'in', 'std_logic_vector', 2)
patmos.entity.addPort('io_comSpm_M_Cmd', 'out', 'std_logic_vector', 3)
patmos.entity.addPort('io_comSpm_M_Addr', 'out', 'std_logic_vector', 32)
patmos.entity.addPort('io_comSpm_M_Data', 'out', 'std_logic_vector', 32)
patmos.entity.addPort('io_comSpm_M_ByteEn', 'out', 'std_logic_vector', 4)
patmos.entity.addPort('io_comSpm_S_Resp', 'in', 'std_logic_vector', 2)
patmos.entity.addPort('io_comSpm_S_Data', 'in', 'std_logic_vector', 32)
patmos.entity.addPort('io_cpuInfoPins_id', 'in', 'std_logic_vector', 32)
patmos.entity.addPort('io_cpuInfoPins_cnt', 'in', 'std_logic_vector', 32)
patmos.entity.addPort('io_memPort_M_Cmd', 'out', 'std_logic_vector', 3)
patmos.entity.addPort('io_memPort_M_Addr', 'out', 'std_logic_vector',
ocpBurstAddrWidth)
patmos.entity.addPort('io_memPort_M_Data', 'out', 'std_logic_vector', 32)
patmos.entity.addPort('io_memPort_M_DataValid', 'out', 'std_logic')
patmos.entity.addPort('io_memPort_M_DataByteEn', 'out', 'std_logic_vector',
4)
patmos.entity.addPort('io_memPort_S_Resp', 'in', 'std_logic_vector', 2)
patmos.entity.addPort('io_memPort_S_Data', 'in', 'std_logic_vector', 32)
patmos.entity.addPort('io_memPort_S_CmdAccept', 'in', 'std_logic')
patmos.entity.addPort('io_memPort_S_DataAccept', 'in', 'std_logic')
patmos.entity.addPort('io_sSPMioPins_M_Cmd', 'out', 'std_logic_vector', 3)
patmos.entity.addPort('io_sSPMioPins_M_Addr', 'out', 'std_logic_vector',
32)
patmos.entity.addPort('io_sSPMioPins_M_Data', 'out', 'std_logic_vector',
32)
patmos.entity.addPort('io_sSPMioPins_M_ByteEn', 'out', 'std_logic_vector',
4)
patmos.entity.addPort('io_sSPMioPins_S_Resp', 'in', 'std_logic_vector', 2)
patmos.entity.addPort('io_sSPMioPins_S_Data', 'in', 'std_logic_vector', 32)
return patmos
def getSSPM(numPorts):
sspm = Component(
'SSPMAegean'
) # SSPM becomes the name of the component in the vhdl file, and sspm of the instance
sspm.entity.addPort('clk')
sspm.entity.addPort('reset')
for i in range(numPorts - 1, -1, -1):
sspm.entity.addPort('io_' + str(i) + '_M_Cmd', 'in',
'std_logic_vector', 3)
sspm.entity.addPort('io_' + str(i) + '_M_Addr', 'in',
'std_logic_vector', 32)
sspm.entity.addPort('io_' + str(i) + '_M_Data', 'in',
'std_logic_vector', 32)
sspm.entity.addPort('io_' + str(i) + '_M_ByteEn', 'in',
'std_logic_vector', 4)
sspm.entity.addPort('io_' + str(i) + '_S_Resp', 'out',
'std_logic_vector', 2)
sspm.entity.addPort('io_' + str(i) + '_S_Data', 'out',
'std_logic_vector', 32)
return sspm
def generate(self):
# Instantiation of noc nodes and links
nodes = self.getNodes()
noc = Component('noc')
noc.addPackage('ieee','std_logic_1164')
noc.addPackage('ieee','std_logic_unsigned')
noc.addPackage('ieee','numeric_std')
noc.addPackage('work','config_types')
noc.addPackage('work','config')
noc.addPackage('work','ocp')
noc.addPackage('work','noc_defs')
noc.addPackage('work','noc_interface')
noc.entity.addPort('clk','in','std_logic',1)
noc.entity.addPort('reset','in','std_logic',1)
noc.entity.addPort('ocp_io_ms','in','ocp_io_m_a',1)
noc.entity.addPort('ocp_io_ss','out','ocp_io_s_a',1)
noc.entity.addPort('spm_ports_m','out','spm_masters',1)
noc.entity.addPort('spm_ports_s','in','spm_slaves',1)
noc.arch.declSignal('north_in_f, east_in_f, south_in_f, west_in_f','link_m_f')
noc.arch.declSignal('north_in_b, east_in_b, south_in_b, west_in_b','link_m_b')
noc.arch.declSignal('north_out_f, east_out_f, south_out_f, west_out_f','link_m_f')
noc.arch.declSignal('north_out_b, east_out_b, south_out_b, west_out_b','link_m_b')
for k in range(0,len(nodes)):
j, i = nodes[k].get('loc').strip('()').split(',')
instancename = nodes[k].get('id') + '_' + nodes[k].get('IPTypeRef')
nocNode = self.getNocNode()
self.bindNocNode(nocNode,k,i,j)
noc.arch.instComp(nocNode,instancename)
noc.arch.declComp(nocNode)
if self.getTopType() == 'custom':
links = self.getLinks()
for k in range(0,len(links)):
j1, i1 = links[k].get('source').strip('()').split(',')
j2, i2 = links[k].get('sink').strip('()').split(',')
same_col = (j1 == j2)
same_row = (i1 == i2)
#if not (same_row != same_col):
if not ((same_row or same_col) and (same_row != same_col)):
raise SystemExit(__file__ +': Error: Link in specification is illegal. ' + str(etree.tostring(links[k])))
if (abs(int(j1)-int(j2)) > 1) or (abs(int(i1)-int(i2)) > 1):
raise SystemExit(__file__ +': Error: Link is trying to connect cores too far appart. ' + str(etree.tostring(links[k])))
if same_row:
if int(j1) > int(j2):
nocCode.writeEast(noc,i1,i2,j1,j2)
elif int(j1) < int(j2):
nocCode.writeWest(noc,i1,i2,j1,j2)
else:
raise SystemExit(__file__ +': Error: Something is wrong!!!')
if same_col:
if int(i1) > int(i2):
nocCode.writeSouth(noc,i1,i2,j1,j2)
elif int(i1) < int(i2):
nocCode.writeNorth(noc,i1,i2,j1,j2)
else:
raise SystemExit(__file__ +': Error: Something is wrong!!!')
elif self.getTopType() == 'bitorus':
nocCode.writeBitorus(noc)
elif self.getTopType() == 'mesh':
nocCode.writeMesh(noc)
else:
SystemExit(__file__ +': Error: xml validation error')
noc.writeComp(self.p.NOCFile)
routerType = self.getRouterType()
argo_src = open(self.p.BUILD_PATH+'/.argo_src','w')
argo_src.write(self.p.ARGO_PATH+'/src/config_types.vhd ')
argo_src.write(self.p.BUILD_PATH + '/ocp_config.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/ocp/ocp.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/util/math_util.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/noc_defs.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/noc_interface.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/mem/bram.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/mem/bram_tdp.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/ni/counter.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/ni/dma.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/mem/com_spm.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/ni/nAdapter.vhd ')
if routerType == 'sync':
argo_src.write(self.p.ARGO_PATH+'/src/routers/synchronous/xbar.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/synchronous/hpu.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/synchronous/router.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/noc/synchronous/noc_node.vhd ')
#raise SystemExit(__file__ +': Error: routerType: ' + routerType + ' is not yet implemented.')
elif routerType == 'async':
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/delays.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/rtl/matched_delay.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/rtl/sr_latch.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/rtl/c_gate_generic.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/crossbar.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/latch_controller.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/channel_latch.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/hpu_latch.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/hpu_comb.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/crossbar_stage.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/hpu.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/router.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/fifo.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/noc/asynchronous/noc_node.vhd ')
elif routerType == 'async_fpga':
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/delays.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/fpga/matched_delay.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/fpga/AS_C2.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/fpga/c_gate_generic.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/crossbar.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/latch_controller.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/channel_latch.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/hpu_latch.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/hpu_comb.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/crossbar_stage.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/hpu.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/router.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/routers/asynchronous/fifo.vhd ')
argo_src.write(self.p.ARGO_PATH+'/src/noc/asynchronous/noc_node.vhd ')
argo_src.close()
return noc
def getAegean():
aegean = Component('aegean')
aegean.addPackage('ieee','std_logic_1164')
aegean.addPackage('ieee','numeric_std')
aegean.addPackage('work','config_types')
aegean.addPackage('work','config')
aegean.addPackage('work','ocp')
aegean.addPackage('work','argo_types')
aegean.addPackage('work','noc_interface')
aegean.entity.addPort('clk')
aegean.entity.addPort('reset')
aegean.entity.addPort('sram_burst_m','out','ocp_burst_m')
aegean.entity.addPort('sram_burst_s','in','ocp_burst_s')
return aegean
def generateTopLevel(self, aegean, audioEnabled):
vendor = self.board.get('vendor')
if vendor == 'Altera':
self.addPinsToQSF()
self.addDeviceToQSF()
self.addDeviceToCDF()
self.addGeneratedFilesToQSF()
elif vendor == 'Xilinx':
#raise SystemExit(__file__ +': Error: Unsupported vendor: ' + vendor)
print("Project files not generated!!")
else:
raise SystemExit(__file__ + ': Error: Unsupported vendor: ' +
vendor)
top = topCode.getTop()
# One Port for each signal in for loop
for IOSignal in self.IOSignals:
portType = 'std_logic'
if IOSignal[3] > 1:
portType = 'std_logic_vector'
top.entity.addPort(
IOSignal[1], IOSignal[2], portType,
IOSignal[3]) # (name,direction,portType,len(pins))
top.arch.declConstant('pll_mult', 'natural', 1, '8')
top.arch.declConstant('pll_div', 'natural', 1, '5')
top.arch.declSignal('clk_int', 'std_logic')
top.arch.declSignal('int_res', 'std_logic')
top.arch.declSignal('res_reg1,res_reg2', 'std_logic')
top.arch.declSignal('res_cnt', 'unsigned', 3, '"000"')
top.arch.declSignal('sram_burst_m', 'ocp_burst_m')
top.arch.declSignal('sram_burst_s', 'ocp_burst_s')
# Declaration of the Tri state signals
# One tri state for the sram possibly in a for loop for more tri states
for IOSignal in self.IOSignals:
if IOSignal[2] == 'inout':
topCode.writeTriStateSig(top, IOSignal[0], IOSignal[3])
#if (IOSignal[0] == 'AudioPins'):
# topCode.writeAudioTriStateSigs(top)
#else:
# topCode.writeTriStateSig(top,IOSignal[0],IOSignal[3])
topCode.attr(top)
topCode.reset(top)
#topCode.audioI2tristate(top)
sramType = self.memory.get('DevTypeRef')
sramDev = self.Devs[sramType]
sramPorts = util.findTag(sramDev, 'ports')
if sramPorts != None:
sramPorts = list(sramPorts)
sramParams = list(util.findTag(sramDev, 'params'))
if sramParams != None:
sramParams = list(sramParams)
sramEntity = sramDev.get('entity')
sramIFace = sramDev.get('iface')
# The tristate logic and registers
for IOSignal in self.IOSignals:
if IOSignal[2] == 'inout': # and (IOSignal[0] != 'AudioPins') ):
topCode.writeTriState(top, IOSignal[0], sramEntity,
IOSignal[1])
sram = Component(sramEntity)
sram.entity.addPort('clk')
sram.entity.addPort('reset')
for param in sramParams:
if param.get('addr_width') != 'None':
addrWidth = param.get('value')
ocp.addSlavePort(sram, sramIFace, addrWidth)
if sramPorts != None:
for port in sramPorts:
width = port.get('width')
if port.tag == 'outport':
if width != None:
sram.entity.addPort(port.get('name'), 'out',
'std_logic_vector', int(width))
else:
sram.entity.addPort(port.get('name'), 'out')
elif port.tag == 'inport':
if width != None:
sram.entity.addPort(port.get('name'), 'in',
'std_logic_vector', int(width))
else:
sram.entity.addPort(port.get('name'), 'in')
clkPin = 'open'
if sramEntity == 'SSRam32Ctrl':
clkPin = 'oSRAM_CLK'
topCode.pll(top, vendor, clkPin)
top.arch.declComp(sram)
topCode.bindAegean(aegean, len(self.nodes), audioEnabled)
top.arch.instComp(aegean, 'cmp', True)
topCode.bindSram(sram, sramEntity, 'sram_burst_m', 'sram_burst_s')
top.arch.instComp(sram, 'ssram')
top.writeComp(self.p.TopFile)
return top
def getTest():
test = Component('aegean_testbench')
test.addPackage('ieee','std_logic_1164')
test.addPackage('ieee','numeric_std')
test.addPackage('std','textio')
test.addPackage('modelsim_lib','util')
test.addPackage('work','test')
test.addPackage('work','ocp')
return test
def getAegean():
aegean = Component('aegean')
aegean.addPackage('ieee', 'std_logic_1164')
aegean.addPackage('ieee', 'numeric_std')
aegean.addPackage('work', 'config_types')
aegean.addPackage('work', 'config')
aegean.addPackage('work', 'ocp')
aegean.addPackage('work', 'argo_types')
aegean.addPackage('work', 'noc_interface')
aegean.entity.addPort('clk')
aegean.entity.addPort('reset')
aegean.entity.addPort('sram_burst_m', 'out', 'ocp_burst_m')
aegean.entity.addPort('sram_burst_s', 'in', 'ocp_burst_s')
return aegean
def generate(self):
# Instantiation of noc nodes and links
nodes = self.getNodes()
noc = Component('noc')
noc.addPackage('ieee', 'std_logic_1164')
noc.addPackage('ieee', 'std_logic_unsigned')
noc.addPackage('ieee', 'numeric_std')
noc.addPackage('work', 'config_types')
noc.addPackage('work', 'config')
noc.addPackage('work', 'ocp')
noc.addPackage('work', 'argo_types')
noc.addPackage('work', 'noc_interface')
noc.entity.addPort('clk', 'in', 'std_logic', 1)
noc.entity.addPort('reset', 'in', 'std_logic', 1)
noc.entity.addPort('ocp_io_ms', 'in', 'ocp_io_m_a', 1)
noc.entity.addPort('supervisor', 'in', 'std_logic_vector', len(nodes))
noc.entity.addPort('ocp_io_ss', 'out', 'ocp_io_s_a', 1)
noc.entity.addPort('spm_ports_m', 'out', 'mem_if_masters', 1)
noc.entity.addPort('spm_ports_s', 'in', 'mem_if_slaves', 1)
noc.entity.addPort('irq', 'out', 'std_logic_vector', len(nodes) * 2)
noc.arch.declSignal('master_run', 'std_logic')
noc.arch.declSignal('north_in_f, east_in_f, south_in_f, west_in_f',
'link_m_f')
noc.arch.declSignal('north_in_b, east_in_b, south_in_b, west_in_b',
'link_m_b')
noc.arch.declSignal('north_out_f, east_out_f, south_out_f, west_out_f',
'link_m_f')
noc.arch.declSignal('north_out_b, east_out_b, south_out_b, west_out_b',
'link_m_b')
for k in range(0, len(nodes)):
j, i = nodes[k].get('loc').strip('()').split(',')
instancename = nodes[k].get('id') + '_' + nodes[k].get(
'IPTypeRef').replace('-', '_')
nocNode = self.getNocNode()
if k == 0:
nocMaster = True
else:
nocMaster = False
self.bindNocNode(nocNode, k, i, j, nocMaster)
noc.arch.instComp(nocNode, instancename)
noc.arch.declComp(nocNode)
if self.getTopType() == 'custom':
links = self.getLinks()
for k in range(0, len(links)):
j1, i1 = links[k].get('source').strip('()').split(',')
j2, i2 = links[k].get('sink').strip('()').split(',')
same_col = (j1 == j2)
same_row = (i1 == i2)
#if not (same_row != same_col):
if not ((same_row or same_col) and (same_row != same_col)):
raise SystemExit(
__file__ +
': Error: Link in specification is illegal. ' +
str(etree.tostring(links[k])))
if (abs(int(j1) - int(j2)) > 1) or (abs(int(i1) - int(i2)) >
1):
raise SystemExit(
__file__ +
': Error: Link is trying to connect cores too far appart. '
+ str(etree.tostring(links[k])))
if same_row:
if int(j1) > int(j2):
nocCode.writeEast(noc, i1, i2, j1, j2)
elif int(j1) < int(j2):
nocCode.writeWest(noc, i1, i2, j1, j2)
else:
raise SystemExit(__file__ +
': Error: Something is wrong!!!')
if same_col:
if int(i1) > int(i2):
nocCode.writeSouth(noc, i1, i2, j1, j2)
elif int(i1) < int(i2):
nocCode.writeNorth(noc, i1, i2, j1, j2)
else:
raise SystemExit(__file__ +
': Error: Something is wrong!!!')
elif self.getTopType() == 'bitorus':
nocCode.writeBitorus(noc)
elif self.getTopType() == 'mesh':
nocCode.writeMesh(noc)
else:
SystemExit(__file__ + ': Error: xml validation error')
noc.writeComp(self.p.NOCFile)
routerType = self.getRouterType()
argo_src = open(self.p.BUILD_PATH + '/.argo_src', 'w')
argo_src.write(self.p.ARGO_PATH + '/src/config_types.vhd ')
argo_src.write(self.p.BUILD_PATH + '/ocp_config.vhd ')
argo_src.write(self.p.BUILD_PATH + '/config.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ocp/ocp.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/util/math_util.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/argo_types.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/noc_interface.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/mem/tdp_ram.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/mem/tdp_bram.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/rx_unit.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/irq_fifo.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/config_bus.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/spm_bus.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/packet_manager.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/schedule_table.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/TDM_controller.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/MC_controller.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/mem/com_spm.vhd ')
argo_src.write(self.p.ARGO_PATH + '/src/ni/network_interface.vhd ')
if routerType == 'sync':
argo_src.write(self.p.ARGO_PATH +
'/src/routers/synchronous/xbar.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/synchronous/hpu.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/synchronous/router.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/noc/synchronous/noc_node.vhd ')
#raise SystemExit(__file__ +': Error: routerType: ' + routerType + ' is not yet implemented.')
elif routerType == 'async':
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/delays.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/rtl/matched_delay.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/rtl/sr_latch.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/rtl/c_gate_generic.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/crossbar.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/latch_controller.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/channel_latch.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/hpu_latch.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/hpu_comb.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/crossbar_stage.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/hpu.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/router.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/fifo.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/noc/asynchronous/noc_node.vhd ')
elif routerType == 'async_fpga':
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/delays.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/fpga/matched_delay.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/fpga/AS_C2.vhd ')
argo_src.write(
self.p.ARGO_PATH +
'/src/routers/asynchronous/fpga/c_gate_generic.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/crossbar.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/latch_controller.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/channel_latch.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/hpu_latch.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/hpu_comb.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/crossbar_stage.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/hpu.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/router.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/routers/asynchronous/fifo.vhd ')
argo_src.write(self.p.ARGO_PATH +
'/src/noc/asynchronous/noc_node.vhd ')
argo_src.close()
return noc
def getTest():
test = Component('aegean_testbench')
test.addPackage('ieee', 'std_logic_1164')
test.addPackage('ieee', 'numeric_std')
test.addPackage('std', 'textio')
test.addPackage('modelsim_lib', 'util')
test.addPackage('work', 'test')
test.addPackage('work', 'ocp')
return test
