def __init__(self, addr_depth, data_width):
self.duration = 1000 * nsec
self.stimuli = []
self.system, system_inst = create_system()
self.stimuli.append(system_inst)
self.dut = Ram(self.system, addr_depth, data_width)
self.bus = self.dut.bus()
@instance
def master():
yield delay(99 * nsec)
for i in range(3):
yield delay(99 * nsec)
yield(sb_write(self.system, self.bus, i + 1, (i + 1) * 2))
for i in range(3):
yield delay(99 * nsec)
yield(sb_read(self.system, self.bus, i + 1))
assert self.bus.RD_DATA == (i + 1) * 2
self.stimuli.append(master)
# Any parameters you want to have at the top level
self.args = self.system, self.bus
def __init__(self, addr_depth, data_width):
self.duration = 1000 * nsec
self.stimuli = []
self.system, system_inst = create_system()
self.stimuli.append(system_inst)
self.dut = Ram(self.system, addr_depth, data_width)
self.bus = self.dut.bus()
@instance
def master():
yield delay(99 * nsec)
for i in range(3):
yield delay(99 * nsec)
yield (sb_write(self.system, self.bus, i + 1, (i + 1) * 2))
for i in range(3):
yield delay(99 * nsec)
yield (sb_read(self.system, self.bus, i + 1))
assert self.bus.RD_DATA == (i + 1) * 2
self.stimuli.append(master)
# Any parameters you want to have at the top level
self.args = self.system, self.bus
def __init__(self,
fifo_depth=5,
data_width=32,
nr_keys=7,
ts_width=8,
prescaler=2):
self.duration = 30000 * nsec
self.stimuli = []
self.system, system_inst = create_system()
self.stimuli.append(system_inst)
fp_rst = Signal(False)
fp_clk = Signal(False)
fp_din = Signal(False)
fp_din = Signal(False)
self.mux = Mux(self.system)
self.fp = FrontPanel(self.system,
fp_rst,
fp_clk,
fp_din,
fifo_depth=fifo_depth,
data_width=32,
nr_keys=nr_keys,
ts_width=8,
prescaler=prescaler,
nr_overscan_keys=4,
overscan_ratio=4)
self.mux.add(self.fp.ctl_bus)
self.mux.add(self.fp.data_bus)
self.bus = self.mux.bus()
self.stimuli.append(fake_panel(fp_rst, fp_clk, fp_din,
nr_keys=nr_keys))
@instance
def master():
yield delay(299 * nsec)
while 1:
yield delay(99 * nsec)
yield (sb_read(self.system, self.bus, 1))
self.stimuli.append(master)
# Any parameters you want to have at the top level
self.args = (self.system, self.bus, fp_rst, fp_clk, fp_din)
def __init__(self):
self.duration = 1200 * nsec
self.stimuli = []
self.system, system_inst = create_system()
self.stimuli.append(system_inst)
self.mux = Mux(self.system)
self.ram1 = Ram(self.system, 11, 8)
self.mux.add(self.ram1.bus())
self.ram2 = Ram(self.system, 5, 16)
self.mux.add(self.ram2.bus())
print "ram1.addr", self.ram1.bus().addr
print "ram2.addr", self.ram2.bus().addr
self.bus = self.mux.bus()
@instance
def master():
yield delay(99 * nsec)
# Out of bounds write, just to make sure nothing dies
yield(sb_write(self.system, self.bus, 10, 0x1234))
for i in range(3):
yield delay(99 * nsec)
yield(sb_write(self.system, self.bus, i + 1, (i + 1) * 2))
yield(sb_write(self.system, self.bus, i + 17, (i + 1) * 3))
for i in range(3):
yield delay(99 * nsec)
yield(sb_read(self.system, self.bus, i + 1))
assert self.bus.RD_DATA == (i + 1) * 2
yield(sb_read(self.system, self.bus, i + 17))
assert self.bus.RD_DATA == (i + 1) * 3
self.stimuli.append(master)
# Any parameters you want to have at the top level
self.args = self.system, self.bus
def __init__(self, addr_depth, data_width):
self.duration = 1000 * nsec
self.stimuli = []
self.system, system_inst = create_system()
self.stimuli.append(system_inst)
self.bus = Bus(addr_depth, data_width)
@instance
def master():
yield delay(99 * nsec)
yield delay(99 * nsec)
yield(sb_write(self.system, self.bus, 1, 2))
yield delay(99 * nsec)
yield(sb_read(self.system, self.bus, 1))
self.stimuli.append(master)
# Any parameters you want to have at the top level
self.args = self.system, self.bus
def __init__(self, fifo_depth = 5, data_width = 32, nr_keys = 7, ts_width = 8, prescaler = 2):
self.duration = 30000 * nsec
self.stimuli = []
self.system, system_inst = create_system()
self.stimuli.append(system_inst)
fp_rst = Signal(False)
fp_clk = Signal(False)
fp_din = Signal(False)
fp_din = Signal(False)
self.mux = Mux(self.system)
self.fp = FrontPanel(self.system,
fp_rst, fp_clk, fp_din,
fifo_depth = fifo_depth, data_width = 32,
nr_keys = nr_keys, ts_width = 8,
prescaler = prescaler,
nr_overscan_keys = 4, overscan_ratio = 4)
self.mux.add(self.fp.ctl_bus)
self.mux.add(self.fp.data_bus)
self.bus = self.mux.bus()
self.stimuli.append(fake_panel(fp_rst, fp_clk, fp_din, nr_keys = nr_keys))
@instance
def master():
yield delay(299 * nsec)
while 1:
yield delay(99 * nsec)
yield(sb_read(self.system, self.bus, 1))
self.stimuli.append(master)
# Any parameters you want to have at the top level
self.args = ( self.system, self.bus,
fp_rst, fp_clk, fp_din )
def __init__(self, addr_depth, data_width):
self.duration = 1000 * nsec
self.stimuli = []
self.system, system_inst = create_system()
self.stimuli.append(system_inst)
self.dut = Algo(self.system, addr_depth, data_width)
self.bus = self.dut.bus()
@instance
def master():
yield delay(99 * nsec)
for i in range(5):
yield delay(99 * nsec)
yield(sb_read(self.system, self.bus, 1 + i))
self.stimuli.append(master)
# Any parameters you want to have at the top level
self.args = self.system, self.bus
def __init__(self, addr_depth, data_width):
self.duration = 1000 * nsec
self.stimuli = []
self.system, system_inst = create_system()
self.stimuli.append(system_inst)
self.dut = Algo(self.system, addr_depth, data_width)
self.bus = self.dut.bus()
@instance
def master():
yield delay(99 * nsec)
for i in range(5):
yield delay(99 * nsec)
yield (sb_read(self.system, self.bus, 1 + i))
self.stimuli.append(master)
# Any parameters you want to have at the top level
self.args = self.system, self.bus
def __init__(self, addr_depth, data_width):
self.duration = 1000 * nsec
self.stimuli = []
self.system, system_inst = create_system(reset_duration=10)
self.stimuli.append(system_inst)
if 1:
self.fifo = SyncFifo(self.system.RST, self.system.CLK,
intbv(0)[data_width:], 4)
else:
self.fifo = AsyncFifo(self.system.RST, self.system.CLK,
self.system.CLK,
intbv(0)[data_width:], 2)
self.dut = FifoRam('fifo', self.system, self.fifo, self.fifo,
addr_depth, data_width)
self.bus = self.dut.bus()
@instance
def master():
yield delay(99 * nsec)
for i in range(len(self.dut._ram)):
self.dut._ram[i].next = i
yield self.system.CLK.posedge
self.dut.wr_addr.next = 0x9
self.dut.rd_addr.next = 0x2
self.dut.rd_count.next = 0x06
self.stimuli.append(master)
# Any parameters you want to have at the top level
self.args = self.system, self.bus
def __init__(self):
self.duration = 400 * nsec
self.stimuli = []
self.system, system_inst = create_system()
self.stimuli.append(system_inst)
self.ro = Signal(False)
self.rw = Signal(intbv(0)[2:])
self.port1 = Port(4)
self.port2 = Port(4)
self.dut = Reg(self.system, 'reg', "A Register", [
RoField('rofield', "Read Only Field", self.ro),
RwField('rwfield', "Read/Write Field", self.rw),
DummyField(1),
Field('field1', "A Field", self.port1),
Field('field2', "Another Field", self.port2),
])
self.bus = self.dut.bus()
@instance
def master():
yield delay(199 * nsec)
yield(sb_read(self.system, self.bus, 0))
assert self.bus.RD_DATA == 0x1f0
yield(sb_write(self.system, self.bus, 0, 0x234))
yield(sb_read(self.system, self.bus, 0))
assert self.bus.RD_DATA == 0x3c5
self.stimuli.append(master)
# Any parameters you want to have at the top level
self.args = self.system, self.bus
def __init__(self):
self.duration = 400 * nsec
self.stimuli = []
self.system, system_inst = create_system()
self.stimuli.append(system_inst)
self.ro = Signal(False)
self.rw = Signal(intbv(0)[2:])
self.port1 = Port(4)
self.port2 = Port(4)
self.dut = Reg(self.system, 'reg', "A Register", [
RoField('rofield', "Read Only Field", self.ro),
RwField('rwfield', "Read/Write Field", self.rw),
DummyField(1),
Field('field1', "A Field", self.port1),
Field('field2', "Another Field", self.port2),
])
self.bus = self.dut.bus()
@instance
def master():
yield delay(199 * nsec)
yield (sb_read(self.system, self.bus, 0))
assert self.bus.RD_DATA == 0x1f0
yield (sb_write(self.system, self.bus, 0, 0x234))
yield (sb_read(self.system, self.bus, 0))
assert self.bus.RD_DATA == 0x3c5
self.stimuli.append(master)
# Any parameters you want to have at the top level
self.args = self.system, self.bus