def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem(test_mem_mode, options.machine_type, np, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory= options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, voltage_domain = test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, voltage_domain = test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) else: print("Error: a kernel must be provided to run in full system mode") sys.exit(1) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np)] if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: bootmem = getattr(test_sys, 'bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, voltage_domain = test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.simpoint_profile: if not CpuConfig.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal("SimPoint generation not supported with more than one CPUs") for i in range(np): if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() if options.bp_type: bpClass = BPConfig.get(options.bp_type) test_sys.cpu[i].branchPred = bpClass() if options.indirect_bp_type: IndirectBPClass = \ BPConfig.get_indirect(options.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) return test_sys
def run(options, root, testsys, cpu_class): if options.checkpoint_dir: cptdir = options.checkpoint_dir elif m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.fast_forward and options.checkpoint_restore != None: fatal("Can't specify both --fast-forward and --checkpoint-restore") if options.standard_switch and not options.caches: fatal("Must specify --caches when using --standard-switch") if options.standard_switch and options.repeat_switch: fatal("Can't specify both --standard-switch and --repeat-switch") if options.repeat_switch and options.take_checkpoints: fatal("Can't specify both --repeat-switch and --take-checkpoints") np = options.num_cpus switch_cpus = None if options.prog_interval: for i in xrange(np): testsys.cpu[i].progress_interval = options.prog_interval if options.maxinsts: for i in xrange(np): testsys.cpu[i].max_insts_any_thread = options.maxinsts if cpu_class: switch_cpus = [cpu_class(switched_out=True, cpu_id=(i)) for i in xrange(np)] for i in xrange(np): if options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) switch_cpus[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain switch_cpus[i].progress_interval = \ testsys.cpu[i].progress_interval switch_cpus[i].isa = testsys.cpu[i].isa # simulation period if options.maxinsts: switch_cpus[i].max_insts_any_thread = options.maxinsts # Add checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() if options.bp_type: bpClass = BPConfig.get(options.bp_type) switch_cpus[i].branchPred = bpClass() # If elastic tracing is enabled attach the elastic trace probe # to the switch CPUs if options.elastic_trace_en: CpuConfig.config_etrace(cpu_class, switch_cpus, options) testsys.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] if options.repeat_switch: switch_class = getCPUClass(options.cpu_type)[0] if switch_class.require_caches() and \ not options.caches: print("%s: Must be used with caches" % str(switch_class)) sys.exit(1) if not switch_class.support_take_over(): print("%s: CPU switching not supported" % str(switch_class)) sys.exit(1) repeat_switch_cpus = [switch_class(switched_out=True, \ cpu_id=(i)) for i in xrange(np)] for i in xrange(np): repeat_switch_cpus[i].system = testsys repeat_switch_cpus[i].workload = testsys.cpu[i].workload repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain repeat_switch_cpus[i].isa = testsys.cpu[i].isa if options.maxinsts: repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts if options.checker: repeat_switch_cpus[i].addCheckerCpu() testsys.repeat_switch_cpus = repeat_switch_cpus if cpu_class: repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) for i in xrange(np)] else: repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) for i in xrange(np)] if options.standard_switch: switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i)) for i in xrange(np)] switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i)) for i in xrange(np)] for i in xrange(np): switch_cpus[i].system = testsys switch_cpus_1[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus_1[i].workload = testsys.cpu[i].workload switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain switch_cpus[i].isa = testsys.cpu[i].isa switch_cpus_1[i].isa = testsys.cpu[i].isa # if restoring, make atomic cpu simulate only a few instructions if options.checkpoint_restore != None: testsys.cpu[i].max_insts_any_thread = 1 # Fast forward to specified location if we are not restoring elif options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) # Fast forward to a simpoint (warning: time consuming) elif options.simpoint: if testsys.cpu[i].workload[0].simpoint == 0: fatal('simpoint not found') testsys.cpu[i].max_insts_any_thread = \ testsys.cpu[i].workload[0].simpoint # No distance specified, just switch else: testsys.cpu[i].max_insts_any_thread = 1 # warmup period if options.warmup_insts: switch_cpus[i].max_insts_any_thread = options.warmup_insts # simulation period if options.maxinsts: switch_cpus_1[i].max_insts_any_thread = options.maxinsts # attach the checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() switch_cpus_1[i].addCheckerCpu() testsys.switch_cpus = switch_cpus testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] # set the checkpoint in the cpu before m5.instantiate is called if options.take_checkpoints != None and \ (options.simpoint or options.at_instruction): offset = int(options.take_checkpoints) # Set an instruction break point if options.simpoint: for i in xrange(np): if testsys.cpu[i].workload[0].simpoint == 0: fatal('no simpoint for testsys.cpu[%d].workload[0]', i) checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset testsys.cpu[i].max_insts_any_thread = checkpoint_inst # used for output below options.take_checkpoints = checkpoint_inst else: options.take_checkpoints = offset # Set all test cpus with the right number of instructions # for the upcoming simulation for i in xrange(np): testsys.cpu[i].max_insts_any_thread = offset if options.take_simpoint_checkpoints != None: simpoints, interval_length = parseSimpointAnalysisFile(options, testsys) checkpoint_dir = None if options.checkpoint_restore: cpt_starttick, checkpoint_dir = findCptDir(options, cptdir, testsys) root.apply_config(options.param) m5.instantiate(checkpoint_dir) # Initialization is complete. If we're not in control of simulation # (that is, if we're a slave simulator acting as a component in another # 'master' simulator) then we're done here. The other simulator will # call simulate() directly. --initialize-only is used to indicate this. if options.initialize_only: return # Handle the max tick settings now that tick frequency was resolved # during system instantiation # NOTE: the maxtick variable here is in absolute ticks, so it must # include any simulated ticks before a checkpoint explicit_maxticks = 0 maxtick_from_abs = m5.MaxTick maxtick_from_rel = m5.MaxTick maxtick_from_maxtime = m5.MaxTick if options.abs_max_tick: maxtick_from_abs = options.abs_max_tick explicit_maxticks += 1 if options.rel_max_tick: maxtick_from_rel = options.rel_max_tick if options.checkpoint_restore: # NOTE: this may need to be updated if checkpoints ever store # the ticks per simulated second maxtick_from_rel += cpt_starttick if options.at_instruction or options.simpoint: warn("Relative max tick specified with --at-instruction or" \ " --simpoint\n These options don't specify the " \ "checkpoint start tick, so assuming\n you mean " \ "absolute max tick") explicit_maxticks += 1 if options.maxtime: maxtick_from_maxtime = m5.ticks.fromSeconds(options.maxtime) explicit_maxticks += 1 if explicit_maxticks > 1: warn("Specified multiple of --abs-max-tick, --rel-max-tick, --maxtime."\ " Using least") maxtick = min([maxtick_from_abs, maxtick_from_rel, maxtick_from_maxtime]) if options.checkpoint_restore != None and maxtick < cpt_starttick: fatal("Bad maxtick (%d) specified: " \ "Checkpoint starts starts from tick: %d", maxtick, cpt_starttick) if options.standard_switch or cpu_class: if options.standard_switch: print("Switch at instruction count:%s" % str(testsys.cpu[0].max_insts_any_thread)) exit_event = m5.simulate() elif cpu_class and options.fast_forward: print("Switch at instruction count:%s" % str(testsys.cpu[0].max_insts_any_thread)) exit_event = m5.simulate() else: print("Switch at curTick count:%s" % str(10000)) exit_event = m5.simulate(10000) print("Switched CPUS @ tick %s" % (m5.curTick())) m5.switchCpus(testsys, switch_cpu_list) if options.standard_switch: print("Switch at instruction count:%d" % (testsys.switch_cpus[0].max_insts_any_thread)) #warmup instruction count may have already been set if options.warmup_insts: exit_event = m5.simulate() else: exit_event = m5.simulate(options.standard_switch) print("Switching CPUS @ tick %s" % (m5.curTick())) print("Simulation ends instruction count:%d" % (testsys.switch_cpus_1[0].max_insts_any_thread)) m5.switchCpus(testsys, switch_cpu_list1) # If we're taking and restoring checkpoints, use checkpoint_dir # option only for finding the checkpoints to restore from. This # lets us test checkpointing by restoring from one set of # checkpoints, generating a second set, and then comparing them. if (options.take_checkpoints or options.take_simpoint_checkpoints) \ and options.checkpoint_restore: if m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.take_checkpoints != None : # Checkpoints being taken via the command line at <when> and at # subsequent periods of <period>. Checkpoint instructions # received from the benchmark running are ignored and skipped in # favor of command line checkpoint instructions. exit_event = scriptCheckpoints(options, maxtick, cptdir) # Take SimPoint checkpoints elif options.take_simpoint_checkpoints != None: takeSimpointCheckpoints(simpoints, interval_length, cptdir) # Restore from SimPoint checkpoints elif options.restore_simpoint_checkpoint != None: restoreSimpointCheckpoint() else: if options.fast_forward: m5.stats.reset() print("**** REAL SIMULATION ****") # If checkpoints are being taken, then the checkpoint instruction # will occur in the benchmark code it self. if options.repeat_switch and maxtick > options.repeat_switch: exit_event = repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, options.repeat_switch) else: exit_event = benchCheckpoints(options, maxtick, cptdir) print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())) if options.checkpoint_at_end: m5.checkpoint(joinpath(cptdir, "cpt.%d")) if exit_event.getCode() != 0: print("Simulated exit code not 0! Exit code is", exit_event.getCode())
# Create a source clock for the system and set the clock period system.clk_domain = SrcClockDomain(clock = options.sys_clock, voltage_domain = system.voltage_domain) # Create a CPU voltage domain system.cpu_voltage_domain = VoltageDomain() # Create a separate clock domain for the CPUs system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, voltage_domain = system.cpu_voltage_domain) # If elastic tracing is enabled, then configure the cpu and attach the elastic # trace probe if options.elastic_trace_en: CpuConfig.config_etrace(CPUClass, system.cpu, options) # All cpus belong to a common cpu_clk_domain, therefore running at a common # frequency. for cpu in system.cpu: cpu.clk_domain = system.cpu_clk_domain if is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass): if buildEnv['TARGET_ISA'] == 'x86': system.kvm_vm = KvmVM() for process in multiprocesses: process.useArchPT = True process.kvmInSE = True else: fatal("KvmCPU can only be used in SE mode with x86")
# Create a source clock for the system and set the clock period system.clk_domain = SrcClockDomain(clock=options.sys_clock, voltage_domain=system.voltage_domain) # Create a CPU voltage domain system.cpu_voltage_domain = VoltageDomain() # Create a separate clock domain for the CPUs system.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=system.cpu_voltage_domain) # If elastic tracing is enabled, then configure the cpu and attach the elastic # trace probe if options.elastic_trace_en: CpuConfig.config_etrace(CPUClass, system.cpu, options) # All cpus belong to a common cpu_clk_domain, therefore running at a common # frequency. for cpu in system.cpu: cpu.clk_domain = system.cpu_clk_domain if ObjectList.is_kvm_cpu(CPUClass) or ObjectList.is_kvm_cpu(FutureClass): if buildEnv['TARGET_ISA'] == 'x86': system.kvm_vm = KvmVM() for process in multiprocesses: process.useArchPT = True process.kvmInSE = True else: fatal("KvmCPU can only be used in SE mode with x86")
def run(options, root, testsys, cpu_class): if options.checkpoint_dir: cptdir = options.checkpoint_dir elif m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.fast_forward and options.checkpoint_restore != None: fatal("Can't specify both --fast-forward and --checkpoint-restore") if options.standard_switch and not options.caches: fatal("Must specify --caches when using --standard-switch") if options.standard_switch and options.repeat_switch: fatal("Can't specify both --standard-switch and --repeat-switch") if options.repeat_switch and options.take_checkpoints: fatal("Can't specify both --repeat-switch and --take-checkpoints") np = options.num_cpus switch_cpus = None if options.prog_interval: for i in xrange(np): testsys.cpu[i].progress_interval = options.prog_interval if options.maxinsts: for i in xrange(np): testsys.cpu[i].max_insts_any_thread = options.maxinsts if cpu_class: switch_cpus = [ cpu_class(switched_out=True, cpu_id=(i)) for i in xrange(np) ] if cpu_class == DerivO3CPU: print("DETECTED DERIVO3CPU") for i in xrange(np): if options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) switch_cpus[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain switch_cpus[i].progress_interval = \ testsys.cpu[i].progress_interval switch_cpus[i].isa = testsys.cpu[i].isa if cpu_class == DerivO3CPU: switch_cpus[i].fetchToDecodeDelay = options.fetchToDecodeDelay switch_cpus[ i].decodeToRenameDelay = options.decodeToRenameDelay switch_cpus[i].renameToIEWDelay = options.renameToIEWDelay switch_cpus[i].iewToCommitDelay = options.iewToCommitDelay switch_cpus[ i].issueToExecuteDelay = options.issueToExecuteDelay switch_cpus[i].renameToROBDelay = options.renameToROBDelay switch_cpus[i].fetchWidth = options.fetchWidth switch_cpus[i].decodeWidth = options.decodeWidth switch_cpus[i].renameWidth = options.renameWidth switch_cpus[i].dispatchWidth = options.dispatchWidth switch_cpus[i].issueWidth = options.issueWidth switch_cpus[i].wbWidth = options.wbWidth switch_cpus[i].commitWidth = options.commitWidth switch_cpus[i].squashWidth = options.squashWidth switch_cpus[i].numPhysIntRegs = options.numPhysIntRegs switch_cpus[i].numPhysFloatRegs = options.numPhysFloatRegs switch_cpus[i].numPhysVecRegs = options.numPhysVecRegs switch_cpus[i].numROBEntries = options.numROBEntries # simulation period if options.maxinsts: switch_cpus[i].max_insts_any_thread = options.maxinsts # Add checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() # If elastic tracing is enabled attach the elastic trace probe # to the switch CPUs if options.elastic_trace_en: CpuConfig.config_etrace(cpu_class, switch_cpus, options) testsys.switch_cpus = switch_cpus switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] if options.repeat_switch: switch_class = getCPUClass(options.cpu_type)[0] if switch_class.require_caches() and \ not options.caches: print("%s: Must be used with caches" % str(switch_class)) sys.exit(1) if not switch_class.support_take_over(): print("%s: CPU switching not supported" % str(switch_class)) sys.exit(1) repeat_switch_cpus = [switch_class(switched_out=True, \ cpu_id=(i)) for i in xrange(np)] for i in xrange(np): repeat_switch_cpus[i].system = testsys repeat_switch_cpus[i].workload = testsys.cpu[i].workload repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain repeat_switch_cpus[i].isa = testsys.cpu[i].isa if options.maxinsts: repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts if options.checker: repeat_switch_cpus[i].addCheckerCpu() testsys.repeat_switch_cpus = repeat_switch_cpus if cpu_class: repeat_switch_cpu_list = [(switch_cpus[i], repeat_switch_cpus[i]) for i in xrange(np)] else: repeat_switch_cpu_list = [(testsys.cpu[i], repeat_switch_cpus[i]) for i in xrange(np)] if options.standard_switch: switch_cpus = [ TimingSimpleCPU(switched_out=True, cpu_id=(i)) for i in xrange(np) ] switch_cpus_1 = [ DerivO3CPU(switched_out=True, cpu_id=(i)) for i in xrange(np) ] for i in xrange(np): switch_cpus[i].system = testsys switch_cpus_1[i].system = testsys switch_cpus[i].workload = testsys.cpu[i].workload switch_cpus_1[i].workload = testsys.cpu[i].workload switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain switch_cpus[i].isa = testsys.cpu[i].isa switch_cpus_1[i].isa = testsys.cpu[i].isa # if restoring, make atomic cpu simulate only a few instructions if options.checkpoint_restore != None: testsys.cpu[i].max_insts_any_thread = 1 # Fast forward to specified location if we are not restoring elif options.fast_forward: testsys.cpu[i].max_insts_any_thread = int(options.fast_forward) # Fast forward to a simpoint (warning: time consuming) elif options.simpoint: if testsys.cpu[i].workload[0].simpoint == 0: fatal('simpoint not found') testsys.cpu[i].max_insts_any_thread = \ testsys.cpu[i].workload[0].simpoint # No distance specified, just switch else: testsys.cpu[i].max_insts_any_thread = 1 # warmup period if options.warmup_insts: switch_cpus[i].max_insts_any_thread = options.warmup_insts # simulation period if options.maxinsts: switch_cpus_1[i].max_insts_any_thread = options.maxinsts # attach the checker cpu if selected if options.checker: switch_cpus[i].addCheckerCpu() switch_cpus_1[i].addCheckerCpu() testsys.switch_cpus = switch_cpus testsys.switch_cpus_1 = switch_cpus_1 switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)] # set the checkpoint in the cpu before m5.instantiate is called if options.take_checkpoints != None and \ (options.simpoint or options.at_instruction): offset = int(options.take_checkpoints) # Set an instruction break point if options.simpoint: for i in xrange(np): if testsys.cpu[i].workload[0].simpoint == 0: fatal('no simpoint for testsys.cpu[%d].workload[0]', i) checkpoint_inst = int( testsys.cpu[i].workload[0].simpoint) + offset testsys.cpu[i].max_insts_any_thread = checkpoint_inst # used for output below options.take_checkpoints = checkpoint_inst else: options.take_checkpoints = offset # Set all test cpus with the right number of instructions # for the upcoming simulation for i in xrange(np): testsys.cpu[i].max_insts_any_thread = offset if options.take_simpoint_checkpoints != None: simpoints, interval_length = parseSimpointAnalysisFile( options, testsys) checkpoint_dir = None if options.checkpoint_restore: cpt_starttick, checkpoint_dir = findCptDir(options, cptdir, testsys) m5.instantiate(checkpoint_dir) # Initialization is complete. If we're not in control of simulation # (that is, if we're a slave simulator acting as a component in another # 'master' simulator) then we're done here. The other simulator will # call simulate() directly. --initialize-only is used to indicate this. if options.initialize_only: return # Handle the max tick settings now that tick frequency was resolved # during system instantiation # NOTE: the maxtick variable here is in absolute ticks, so it must # include any simulated ticks before a checkpoint explicit_maxticks = 0 maxtick_from_abs = m5.MaxTick maxtick_from_rel = m5.MaxTick maxtick_from_maxtime = m5.MaxTick if options.abs_max_tick: maxtick_from_abs = options.abs_max_tick explicit_maxticks += 1 if options.rel_max_tick: maxtick_from_rel = options.rel_max_tick if options.checkpoint_restore: # NOTE: this may need to be updated if checkpoints ever store # the ticks per simulated second maxtick_from_rel += cpt_starttick if options.at_instruction or options.simpoint: warn("Relative max tick specified with --at-instruction or" \ " --simpoint\n These options don't specify the " \ "checkpoint start tick, so assuming\n you mean " \ "absolute max tick") explicit_maxticks += 1 if options.maxtime: maxtick_from_maxtime = m5.ticks.fromSeconds(options.maxtime) explicit_maxticks += 1 if explicit_maxticks > 1: warn("Specified multiple of --abs-max-tick, --rel-max-tick, --maxtime."\ " Using least") maxtick = min([maxtick_from_abs, maxtick_from_rel, maxtick_from_maxtime]) if options.checkpoint_restore != None and maxtick < cpt_starttick: fatal("Bad maxtick (%d) specified: " \ "Checkpoint starts starts from tick: %d", maxtick, cpt_starttick) if options.standard_switch or cpu_class: if options.standard_switch: print("Switch at instruction count:%s" % str(testsys.cpu[0].max_insts_any_thread)) exit_event = m5.simulate() elif cpu_class and options.fast_forward: print("Switch at instruction count:%s" % str(testsys.cpu[0].max_insts_any_thread)) exit_event = m5.simulate() else: print("Switch at curTick count:%s" % str(10000)) exit_event = m5.simulate(10000) print("Switched CPUS @ tick %s" % (m5.curTick())) m5.switchCpus(testsys, switch_cpu_list) if options.standard_switch: print("Switch at instruction count:%d" % (testsys.switch_cpus[0].max_insts_any_thread)) #warmup instruction count may have already been set if options.warmup_insts: exit_event = m5.simulate() else: exit_event = m5.simulate(options.standard_switch) print("Switching CPUS @ tick %s" % (m5.curTick())) print("Simulation ends instruction count:%d" % (testsys.switch_cpus_1[0].max_insts_any_thread)) m5.switchCpus(testsys, switch_cpu_list1) # If we're taking and restoring checkpoints, use checkpoint_dir # option only for finding the checkpoints to restore from. This # lets us test checkpointing by restoring from one set of # checkpoints, generating a second set, and then comparing them. if (options.take_checkpoints or options.take_simpoint_checkpoints) \ and options.checkpoint_restore: if m5.options.outdir: cptdir = m5.options.outdir else: cptdir = getcwd() if options.take_checkpoints != None: # Checkpoints being taken via the command line at <when> and at # subsequent periods of <period>. Checkpoint instructions # received from the benchmark running are ignored and skipped in # favor of command line checkpoint instructions. exit_event = scriptCheckpoints(options, maxtick, cptdir) # Take SimPoint checkpoints elif options.take_simpoint_checkpoints != None: takeSimpointCheckpoints(simpoints, interval_length, cptdir) # Restore from SimPoint checkpoints elif options.restore_simpoint_checkpoint != None: restoreSimpointCheckpoint() else: if options.fast_forward: m5.stats.reset() print("**** REAL SIMULATION ****") # If checkpoints are being taken, then the checkpoint instruction # will occur in the benchmark code it self. if options.repeat_switch and maxtick > options.repeat_switch: exit_event = repeatSwitch(testsys, repeat_switch_cpu_list, maxtick, options.repeat_switch) else: exit_event = benchCheckpoints(options, maxtick, cptdir) print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())) if options.checkpoint_at_end: m5.checkpoint(joinpath(cptdir, "cpt.%d")) if not m5.options.interactive: sys.exit(exit_event.getCode())
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, np, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions, vio_9p=options.vio_9p, ) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) test_sys.kernel_extras = [ "/data/src/750-SALAM/benchmarks/vadd-inputs/m0.bin", "/data/src/750-SALAM/benchmarks/vadd-inputs/m1.bin" ] test_sys.kernel_extras_addrs = [0x80c00000, 0x80c00000 + 8 * 8] else: print("Error: a kernel must be provided to run in full system mode") sys.exit(1) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np) ] if ObjectList.is_kvm_cpu(TestCPUClass) or \ ObjectList.is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: bootmem = getattr(test_sys, '_bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.simpoint_profile: if not ObjectList.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in range(np): if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() if not ObjectList.is_kvm_cpu(TestCPUClass): if options.bp_type: bpClass = ObjectList.bp_list.get(options.bp_type) test_sys.cpu[i].branchPred = bpClass() if options.indirect_bp_type: IndirectBPClass = ObjectList.indirect_bp_list.get( options.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) if buildEnv['TARGET_ISA'] == "arm": HWAcc.makeHWAcc(options, test_sys) return test_sys
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "riscv": test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], args.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, args.machine_type, np, bm[0], args.dtb_filename, bare_metal=args.bare_metal, cmdline=cmdline, external_memory=args.external_memory_system, ruby=args.ruby, security=args.enable_security_extensions, vio_9p=args.vio_9p, bootloader=args.bootloader, ) if args.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = args.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=args.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=args.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=args.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if buildEnv['TARGET_ISA'] == 'riscv': test_sys.workload.bootloader = args.kernel elif args.kernel is not None: test_sys.workload.object_file = binary(args.kernel) if args.script is not None: test_sys.readfile = args.script if args.lpae: test_sys.have_lpae = True if args.virtualisation: test_sys.have_virtualization = True test_sys.init_param = args.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np) ] if args.ruby: bootmem = getattr(test_sys, '_bootmem', None) Ruby.create_system(args, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=args.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() test_sys.ruby._cpu_ports[i].connectCpuPorts(cpu) else: if args.caches or args.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not args.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if args.simpoint_profile: if not ObjectList.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in range(np): if args.simpoint_profile: test_sys.cpu[i].addSimPointProbe(args.simpoint_interval) if args.checker: test_sys.cpu[i].addCheckerCpu() if not ObjectList.is_kvm_cpu(TestCPUClass): if args.bp_type: bpClass = ObjectList.bp_list.get(args.bp_type) test_sys.cpu[i].branchPred = bpClass() if args.indirect_bp_type: IndirectBPClass = ObjectList.indirect_bp_list.get( args.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if args.elastic_trace_en and args.checkpoint_restore == None and \ not args.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, args) CacheConfig.config_cache(args, test_sys) MemConfig.config_mem(args, test_sys) if ObjectList.is_kvm_cpu(TestCPUClass) or \ ObjectList.is_kvm_cpu(FutureClass): # Assign KVM CPUs to their own event queues / threads. This # has to be done after creating caches and other child objects # since these mustn't inherit the CPU event queue. for i, cpu in enumerate(test_sys.cpu): # Child objects usually inherit the parent's event # queue. Override that and use the same event queue for # all devices. for obj in cpu.descendants(): obj.eventq_index = 0 cpu.eventq_index = i + 1 test_sys.kvm_vm = KvmVM() return test_sys
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, options.num_cpus, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in xrange(np) ] if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: # Check for timing mode because ruby does not support atomic accesses if not (options.cpu_type == "DerivO3CPU" or options.cpu_type == "TimingSimpleCPU"): print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" sys.exit(1) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.fastmem: if TestCPUClass != AtomicSimpleCPU: fatal("Fastmem can only be used with atomic CPU!") if (options.caches or options.l2cache): fatal("You cannot use fastmem in combination with caches!") if options.simpoint_profile: if not options.fastmem: # Atomic CPU checked with fastmem option already fatal( "SimPoint generation should be done with atomic cpu and fastmem" ) if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in xrange(np): if options.fastmem: test_sys.cpu[i].fastmem = True if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) return test_sys