def create(args): ''' Create and configure the system object. ''' system = SimpleSeSystem(args) # Tell components about the expected physical memory ranges. This # is, for example, used by the MemConfig helper to determine where # to map DRAMs in the physical address space. system.mem_ranges = [ AddrRange(start=0, size=args.mem_size) ] # Configure the off-chip memory system. MemConfig.config_mem(args, system) # Parse the command line and get a list of Processes instances # that we can pass to gem5. processes = get_processes(args.commands_to_run) if len(processes) != args.num_cores: print("Error: Cannot map %d command(s) onto %d CPU(s)" % (len(processes), args.num_cores)) sys.exit(1) system.workload = SEWorkload.init_compatible(processes[0].executable) # Assign one workload to each CPU for cpu, workload in zip(system.cpu_cluster.cpus, processes): cpu.workload = workload return system
def create(args): ''' Create and configure the system object. ''' system = SimpleSeSystem(args) # Tell components about the expected physical memory ranges. This # is, for example, used by the MemConfig helper to determine where # to map DRAMs in the physical address space. system.mem_ranges = [ AddrRange(start=0, size=args.mem_size) ] # Configure the off-chip memory system. MemConfig.config_mem(args, system) # Parse the command line and get a list of Processes instances # that we can pass to gem5. processes = get_processes(args.commands_to_run) if len(processes) != args.num_cores: print("Error: Cannot map %d command(s) onto %d CPU(s)" % (len(processes), args.num_cores)) sys.exit(1) # Assign one workload to each CPU for cpu, workload in zip(system.cpu_cluster.cpus, processes): cpu.workload = workload return system
def create(args): # System CpuClass, mem_mode, _ = Simulation.setCPUClass(args) sys_cfg = Benchmarks.SysConfig(args.script, args.mem_size) system = FSConfig.makeArmSystem(mem_mode, "VExpress_GEM5_V2", args.num_cpus, sys_cfg, bare_metal=True, security=True) system.voltage_domain = VoltageDomain(voltage=args.sys_voltage) system.clk_domain = SrcClockDomain(clock=args.sys_clock, voltage_domain=system.voltage_domain) system.highest_el_is_64 = True system.have_virtualization = True system.workload.object_file = args.kernel # CPU cluster system.cpu_voltage_domain = VoltageDomain() system.cpu_clk_domain = SrcClockDomain( clock=args.cpu_clock, voltage_domain=system.cpu_voltage_domain) system.cpu = [ CpuClass(clk_domain=system.cpu_clk_domain, cpu_id=i) for i in range(args.num_cpus) ] for cpu in system.cpu: cpu.createThreads() # (gem5 v20.1) Disable FEAT_VHE, prevents booting features = cpu.isa[0].id_aa64mmfr1_el1.getValue() cpu.isa[0].id_aa64mmfr1_el1 = features & ~0xf00 CacheConfig.config_cache(args, system) # Devices system.realview.atp_adapter = ProfileGen(config_files=args.atp_file, exit_when_done=False, init_only=True, disable_watchdog=True, disable_mem_check=True) system.realview.atp_device = ATPDevice(pio_addr=0x2b500000, interrupt=ArmSPI(num=104), atp_id="STREAM") system.realview.attachSmmu([system.realview.atp_device], system.membus) # (gem5 v20.1) Ensure 128 CMDQ entries for compatibility from Linux v5.4 system.realview.smmu.smmu_idr1 = 0x00E00000 # (gem5 v20.2+) Enable SMMUv3 interrupt interface to boot Linux if hasattr(system.realview.smmu, "irq_interface_enable"): system.realview.smmu.irq_interface_enable = True connect_adapter(system.realview.atp_adapter, system.realview.smmu) if args.disk_image: system.disk = [ PciVirtIO(vio=VirtIOBlock(image=create_cow_image(disk))) for disk in args.disk_image ] for disk in system.disk: system.realview.attachPciDevice(disk, system.iobus) # Memory MemConfig.config_mem(args, system) return system
def setup_memory_controllers(system, ruby, dir_cntrls, options): ruby.block_size_bytes = options.cacheline_size ruby.memory_size_bits = 48 block_size_bits = int(math.log(options.cacheline_size, 2)) if options.numa_high_bit: numa_bit = options.numa_high_bit else: # if the numa_bit is not specified, set the directory bits as the # lowest bits above the block offset bits, and the numa_bit as the # highest of those directory bits dir_bits = int(math.log(options.num_dirs, 2)) numa_bit = block_size_bits + dir_bits - 1 index = 0 mem_ctrls = [] crossbars = [] # Sets bits to be used for interleaving. Creates memory controllers # attached to a directory controller. A separate controller is created # for each address range as the abstract memory can handle only one # contiguous address range as of now. for dir_cntrl in dir_cntrls: dir_cntrl.directory.numa_high_bit = numa_bit crossbar = None if len(system.mem_ranges) > 1: crossbar = IOXBar() crossbars.append(crossbar) dir_cntrl.memory = crossbar.slave for r in system.mem_ranges: mem_ctrl = MemConfig.create_mem_ctrl( MemConfig.get(options.mem_type), r, index, options.num_dirs, int(math.log(options.num_dirs, 2)), options.cacheline_size, ) if options.access_backing_store: mem_ctrl.kvm_map = False mem_ctrls.append(mem_ctrl) if crossbar != None: mem_ctrl.port = crossbar.master else: mem_ctrl.port = dir_cntrl.memory index += 1 system.mem_ctrls = mem_ctrls if len(crossbars) > 0: ruby.crossbars = crossbars
def setup_memory_controllers(system, ruby, dir_cntrls, options): ruby.block_size_bytes = options.cacheline_size ruby.memory_size_bits = 48 index = 0 mem_ctrls = [] crossbars = [] if options.numa_high_bit: dir_bits = int(math.log(options.num_dirs, 2)) intlv_size = 2**(options.numa_high_bit - dir_bits + 1) else: # if the numa_bit is not specified, set the directory bits as the # lowest bits above the block offset bits intlv_size = options.cacheline_size # Sets bits to be used for interleaving. Creates memory controllers # attached to a directory controller. A separate controller is created # for each address range as the abstract memory can handle only one # contiguous address range as of now. for dir_cntrl in dir_cntrls: crossbar = None if len(system.mem_ranges) > 1: crossbar = IOXBar() crossbars.append(crossbar) dir_cntrl.memory = crossbar.slave dir_ranges = [] for r in system.mem_ranges: mem_ctrl = MemConfig.create_mem_ctrl( MemConfig.get(options.mem_type), r, index, options.num_dirs, int(math.log(options.num_dirs, 2)), intlv_size) if options.access_backing_store: mem_ctrl.kvm_map = False mem_ctrls.append(mem_ctrl) dir_ranges.append(mem_ctrl.range) if crossbar != None: mem_ctrl.port = crossbar.master else: mem_ctrl.port = dir_cntrl.memory # Enable low-power DRAM states if option is set if issubclass(MemConfig.get(options.mem_type), DRAMCtrl): mem_ctrl.enable_dram_powerdown = \ options.enable_dram_powerdown index += 1 dir_cntrl.addr_ranges = dir_ranges system.mem_ctrls = mem_ctrls if len(crossbars) > 0: ruby.crossbars = crossbars
def setup_memory_controllers(system, ruby, dir_cntrls, options): ruby.block_size_bytes = options.cacheline_size ruby.memory_size_bits = 48 block_size_bits = int(math.log(options.cacheline_size, 2)) if options.numa_high_bit: numa_bit = options.numa_high_bit else: # if the numa_bit is not specified, set the directory bits as the # lowest bits above the block offset bits, and the numa_bit as the # highest of those directory bits dir_bits = int(math.log(options.num_dirs, 2)) numa_bit = block_size_bits + dir_bits - 1 index = 0 mem_ctrls = [] crossbars = [] # Sets bits to be used for interleaving. Creates memory controllers # attached to a directory controller. A separate controller is created # for each address range as the abstract memory can handle only one # contiguous address range as of now. for dir_cntrl in dir_cntrls: dir_cntrl.directory.numa_high_bit = numa_bit crossbar = None if len(system.mem_ranges) > 1: crossbar = IOXBar() crossbars.append(crossbar) dir_cntrl.memory = crossbar.slave for r in system.mem_ranges: mem_ctrl = MemConfig.create_mem_ctrl( MemConfig.get(options.mem_type), r, index, options.num_dirs, int(math.log(options.num_dirs, 2)), options.cacheline_size) if options.access_backing_store: mem_ctrl.kvm_map = False mem_ctrls.append(mem_ctrl) if crossbar != None: mem_ctrl.port = crossbar.master else: mem_ctrl.port = dir_cntrl.memory index += 1 system.mem_ctrls = mem_ctrls if len(crossbars) > 0: ruby.crossbars = crossbars
def setup_mem_subsystem(system, ruby, dir_cntrls, options): import math from m5.objects import CowardAddrMapper, PortForwarder from m5.util import fatal ruby.block_size_bytes = options.cacheline_size ruby.memory_size_bits = 48 if len(dir_cntrls) != 1: fatal("len(dir_cntrls) != 1") if options.numa_high_bit: intlv_size = 2**(options.numa_high_bit + 1) else: intlv_size = options.cacheline_size disable_kvm_map = False if options.access_backing_store: disable_kvm_map = True system_mem_range_port = [] mem_subsystem_forwarder = PortForwarder() mem_subsystem = MemConfig.create_mem_subsystem( \ options, system, intlv_size, disable_kvm_map) mem_subsystem_forwarder.master = mem_subsystem.slave if len(system.mem_ranges) > 1: crossbar = IOXBar() dir_cntrls[0].memory = crossbar.slave for rg in system.mem_ranges: range_port = CowardAddrMapper( \ original_ranges = rg, remapped_ranges = rg) crossbar.master = range_port.slave range_port.master = mem_subsystem_forwarder.slave system_mem_range_port.append(range_port) ruby.crossbars = [crossbar] else: assert (MemConfig.valid_size_of(system.mem_ranges) == 1) rg = system.mem_ranges[0] range_port = CowardAddrMapper( \ original_ranges = rg, remapped_ranges = rg) dir_cntrls[0].memory = range_port.slave range_port.master = mem_subsystem_forwarder.slave system_mem_range_port.append(range_port) system.system_mem_range_port = system_mem_range_port system.mem_subsystem_forwarder = mem_subsystem_forwarder dir_cntrls[0].addr_ranges = system.mem_ranges
def main(): parser = argparse.ArgumentParser(epilog=__doc__) parser.add_argument("--dtb", type=str, default=None, help="DTB file to load") parser.add_argument("--kernel", type=str, default=default_kernel, help="Linux kernel") parser.add_argument("--disk-image", type=str, default=default_disk, help="Disk to instantiate") parser.add_argument("--script", type=str, default="", help="Linux bootscript") parser.add_argument("--cpu", type=str, choices=cpu_types.keys(), default="atomic", help="CPU model to use") parser.add_argument("--cpu-freq", type=str, default="4GHz") parser.add_argument("--num-cores", type=int, default=1, help="Number of CPU cores") parser.add_argument("--mem-type", default="DDR3_1600_8x8", choices=MemConfig.mem_names(), help="type of memory to use") parser.add_argument("--mem-channels", type=int, default=1, help="number of memory channels") parser.add_argument("--mem-ranks", type=int, default=None, help="number of memory ranks per channel") parser.add_argument("--mem-size", action="store", type=str, default="2GB", help="Specify the physical memory size") parser.add_argument("--checkpoint", action="store_true") parser.add_argument("--restore", type=str, default=None) args = parser.parse_args() root = Root(full_system=True) root.system = create(args) if args.restore is not None: m5.instantiate(args.restore) else: m5.instantiate() run(args)
def add_main_memory(system, options): system.mem_ranges = [AddrRange(options.mem_address_range)] # create and connect DRAM to the system MemConfig.config_mem(options, system) for mem_ctrl in system.mem_ctrls: # don't save any data mem_ctrl.null = True if options.addr_map == 0: mem_ctrl.addr_mapping = "RoCoRaBaCh" elif options.addr_map == 1: mem_ctrl.addr_mapping = "RoRaBaCoCh" else: fatal("Invalid address map argument.")
def setup_memory_controllers(system, ruby, dir_cntrls, options): if (options.numa_high_bit): block_size_bits = options.numa_high_bit + 1 - \ int(math.log(options.num_dirs, 2)) ruby.block_size_bytes = 2**(block_size_bits) else: ruby.block_size_bytes = options.cacheline_size ruby.memory_size_bits = 48 index = 0 mem_ctrls = [] crossbars = [] # Sets bits to be used for interleaving. Creates memory controllers # attached to a directory controller. A separate controller is created # for each address range as the abstract memory can handle only one # contiguous address range as of now. for dir_cntrl in dir_cntrls: crossbar = None if len(system.mem_ranges) > 1: crossbar = IOXBar() crossbars.append(crossbar) dir_cntrl.memory = crossbar.slave for r in system.mem_ranges: mem_ctrl = MemConfig.create_mem_ctrl( MemConfig.get(options.mem_type), r, index, options.num_dirs, int(math.log(options.num_dirs, 2)), ruby.block_size_bytes, options.xor_low_bit) if options.access_backing_store: mem_ctrl.kvm_map = False mem_ctrls.append(mem_ctrl) if crossbar != None: mem_ctrl.port = crossbar.master else: mem_ctrl.port = dir_cntrl.memory index += 1 system.mem_ctrls = mem_ctrls if len(crossbars) > 0: ruby.crossbars = crossbars
def build_system(options): # create the system we are going to simulate system = System() # use timing mode for the interaction between master-slave ports system.mem_mode = 'timing' # set the clock fequency of the system clk = '100GHz' vd = VoltageDomain(voltage='1V') system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd) # add traffic generators to the system system.tgen = [ TrafficGen(config_file=options.tgen_cfg_file) for i in range(options.num_tgen) ] # Config memory system with given HMC arch MemConfig.config_mem(options, system) # Connect the traffic generatiors if options.arch == "distributed": for i in range(options.num_tgen): system.tgen[i].port = system.membus.slave # connect the system port even if it is not used in this example system.system_port = system.membus.slave if options.arch == "mixed": for i in range(int(options.num_tgen / 2)): system.tgen[i].port = system.membus.slave hh = system.hmc_host if options.enable_global_monitor: system.tgen[2].port = hh.lmonitor[2].slave hh.lmonitor[2].master = hh.seriallink[2].slave system.tgen[3].port = hh.lmonitor[3].slave hh.lmonitor[3].master = hh.seriallink[3].slave else: system.tgen[2].port = hh.seriallink[2].slave system.tgen[3].port = hh.seriallink[3].slave # connect the system port even if it is not used in this example system.system_port = system.membus.slave if options.arch == "same": hh = system.hmc_host for i in range(options.num_links_controllers): if options.enable_global_monitor: system.tgen[i].port = hh.lmonitor[i].slave else: system.tgen[i].port = hh.seriallink[i].slave # set up the root SimObject root = Root(full_system=False, system=system) return root
def build_system(options): # create the system we are going to simulate system = System() # use timing mode for the interaction between master-slave ports system.mem_mode = 'timing' # set the clock fequency of the system clk = '100GHz' vd = VoltageDomain(voltage='1V') system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd) # add traffic generators to the system system.tgen = [TrafficGen(config_file=options.tgen_cfg_file) for i in range(options.num_tgen)] # Config memory system with given HMC arch MemConfig.config_mem(options, system) # Connect the traffic generatiors if options.arch == "distributed": for i in range(options.num_tgen): system.tgen[i].port = system.membus.slave # connect the system port even if it is not used in this example system.system_port = system.membus.slave if options.arch == "mixed": for i in range(int(options.num_tgen/2)): system.tgen[i].port = system.membus.slave hh = system.hmc_host if options.enable_global_monitor: system.tgen[2].port = hh.lmonitor[2].slave hh.lmonitor[2].master = hh.seriallink[2].slave system.tgen[3].port = hh.lmonitor[3].slave hh.lmonitor[3].master = hh.seriallink[3].slave else: system.tgen[2].port = hh.seriallink[2].slave system.tgen[3].port = hh.seriallink[3].slave # connect the system port even if it is not used in this example system.system_port = system.membus.slave if options.arch == "same": hh = system.hmc_host for i in range(options.num_links_controllers): if options.enable_global_monitor: system.tgen[i].port = hh.lmonitor[i].slave else: system.tgen[i].port = hh.seriallink[i].slave # set up the root SimObject root = Root(full_system=False, system=system) return root
def setup_memory_controllers(system, ruby, dir_cntrls, options): ruby.block_size_bytes = options.cacheline_size ruby.memory_size_bits = 48 index = 0 mem_ctrls = [] crossbars = [] # Sets bits to be used for interleaving. Creates memory controllers # attached to a directory controller. A separate controller is created # for each address range as the abstract memory can handle only one # contiguous address range as of now. for dir_cntrl in dir_cntrls: crossbar = None if len(system.mem_ranges) > 1: crossbar = IOXBar() crossbars.append(crossbar) dir_cntrl.memory = crossbar.slave for r in system.mem_ranges: mem_ctrl = MemConfig.create_mem_ctrl( MemConfig.get(options.mem_type), r, index, options.num_dirs, int(math.log(options.num_dirs, 2)), options.cacheline_size) if options.access_backing_store: mem_ctrl.kvm_map=False mem_ctrls.append(mem_ctrl) if crossbar != None: mem_ctrl.port = crossbar.master else: mem_ctrl.port = dir_cntrl.memory index += 1 system.mem_ctrls = mem_ctrls if len(crossbars) > 0: ruby.crossbars = crossbars
def main(): parser = argparse.ArgumentParser(epilog=__doc__) parser.add_argument("commands_to_run", metavar="command(s)", nargs='*', help="Command(s) to run") parser.add_argument("--cpu", type=str, choices=cpu_types.keys(), default="atomic", help="CPU model to use") parser.add_argument("--cpu-freq", type=str, default="4GHz") parser.add_argument("--num-cores", type=int, default=1, help="Number of CPU cores") parser.add_argument("--mem-type", default="DDR3_1600_8x8", choices=MemConfig.mem_names(), help = "type of memory to use") parser.add_argument("--mem-channels", type=int, default=2, help = "number of memory channels") parser.add_argument("--mem-ranks", type=int, default=None, help = "number of memory ranks per channel") parser.add_argument("--mem-size", action="store", type=str, default="2GB", help="Specify the physical memory size") args = parser.parse_args() # Create a single root node for gem5's object hierarchy. There can # only exist one root node in the simulator at any given # time. Tell gem5 that we want to use syscall emulation mode # instead of full system mode. root = Root(full_system=False) # Populate the root node with a system. A system corresponds to a # single node with shared memory. root.system = create(args) # Instantiate the C++ object hierarchy. After this point, # SimObjects can't be instantiated anymore. m5.instantiate() # Start the simulator. This gives control to the C++ world and # starts the simulator. The returned event tells the simulation # script why the simulator exited. event = m5.simulate() # Print the reason for the simulation exit. Some exit codes are # requests for service (e.g., checkpoints) from the simulation # script. We'll just ignore them here and exit. print(event.getCause(), " @ ", m5.curTick()) sys.exit(event.getCode())
def main(): parser = argparse.ArgumentParser(epilog=__doc__) parser.add_argument("commands_to_run", metavar="command(s)", nargs='*', help="Command(s) to run") parser.add_argument("--cpu", type=str, choices=cpu_types.keys(), default="atomic", help="CPU model to use") parser.add_argument("--cpu-freq", type=str, default="4GHz") parser.add_argument("--num-cores", type=int, default=1, help="Number of CPU cores") parser.add_argument("--mem-type", default="DDR3_1600_8x8", choices=MemConfig.mem_names(), help = "type of memory to use") parser.add_argument("--mem-channels", type=int, default=2, help = "number of memory channels") parser.add_argument("--mem-ranks", type=int, default=None, help = "number of memory ranks per channel") parser.add_argument("--mem-size", action="store", type=str, default="2GB", help="Specify the physical memory size") args = parser.parse_args() # Create a single root node for gem5's object hierarchy. There can # only exist one root node in the simulator at any given # time. Tell gem5 that we want to use syscall emulation mode # instead of full system mode. root = Root(full_system=False) # Populate the root node with a system. A system corresponds to a # single node with shared memory. root.system = create(args) # Instantiate the C++ object hierarchy. After this point, # SimObjects can't be instantiated anymore. m5.instantiate() # Start the simulator. This gives control to the C++ world and # starts the simulator. The returned event tells the simulation # script why the simulator exited. event = m5.simulate() # Print the reason for the simulation exit. Some exit codes are # requests for service (e.g., checkpoints) from the simulation # script. We'll just ignore them here and exit. print event.getCause(), " @ ", m5.curTick() sys.exit(event.getCode())
def main(): parser = argparse.ArgumentParser(epilog=__doc__) parser.add_argument("--dtb", type=str, default=None, help="DTB file to load") parser.add_argument("--kernel", type=str, default=default_kernel, help="Linux kernel") parser.add_argument("--disk-image", type=str, default=default_disk, help="Disk to instantiate") parser.add_argument("--script", type=str, default="", help = "Linux bootscript") parser.add_argument("--cpu", type=str, choices=cpu_types.keys(), default="atomic", help="CPU model to use") parser.add_argument("--cpu-freq", type=str, default="4GHz") parser.add_argument("--num-cores", type=int, default=1, help="Number of CPU cores") parser.add_argument("--mem-type", default="DDR3_1600_8x8", choices=MemConfig.mem_names(), help = "type of memory to use") parser.add_argument("--mem-channels", type=int, default=1, help = "number of memory channels") parser.add_argument("--mem-ranks", type=int, default=None, help = "number of memory ranks per channel") parser.add_argument("--mem-size", action="store", type=str, default="2GB", help="Specify the physical memory size") parser.add_argument("--checkpoint", action="store_true") parser.add_argument("--restore", type=str, default=None) args = parser.parse_args() root = Root(full_system=True) root.system = create(args) if args.restore is not None: m5.instantiate(args.restore) else: m5.instantiate() run(args)
def addCommonOptions(parser): # system options parser.add_option("--num-fpgas", type="int", default=0) parser.add_option("--list-cpu-types", action="callback", callback=_listCpuTypes, help="List available CPU types") parser.add_option("--cpu-type", type="choice", default="timing", choices=CpuConfig.cpu_names(), help="type of cpu to run with") parser.add_option("--checker", action="store_true") parser.add_option("-n", "--num-cpus", type="int", default=1) parser.add_option("--sys-voltage", action="store", type="string", default='1.0V', help="""Top-level voltage for blocks running at system power supply""") parser.add_option("--sys-clock", action="store", type="string", default='1GHz', help="""Top-level clock for blocks running at system speed""") parser.add_option("--cpu-clock", action="store", type="string", default='2GHz', help="Clock for blocks running at CPU speed") parser.add_option("--fpga-clock", action="store", type="string", default='300MHz', help="Clock for blocks running at FPGA speed") parser.add_option("--smt", action="store_true", default=False, help=""" Only used if multiple programs are specified. If true, then the number of threads per cpu is same as the number of programs.""") parser.add_option("--elastic-trace-en", action="store_true", help="""Enable capture of data dependency and instruction fetch traces using elastic trace probe.""") # Trace file paths input to trace probe in a capture simulation and input # to Trace CPU in a replay simulation parser.add_option("--inst-trace-file", action="store", type="string", help="""Instruction fetch trace file input to Elastic Trace probe in a capture simulation and Trace CPU in a replay simulation""", default="") parser.add_option("--data-trace-file", action="store", type="string", help="""Data dependency trace file input to Elastic Trace probe in a capture simulation and Trace CPU in a replay simulation""", default="") # Memory Options parser.add_option("--list-mem-types", action="callback", callback=_listMemTypes, help="List available memory types") parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64", choices=MemConfig.mem_names(), help="type of memory to use") parser.add_option("--mem-channels", type="int", default=1, help="number of memory channels") parser.add_option("--mem-ranks", type="int", default=None, help="number of memory ranks per channel") parser.add_option("--mem-size", action="store", type="string", default="512MB", help="Specify the physical memory size (single memory)") parser.add_option("-l", "--lpae", action="store_true") parser.add_option("-V", "--virtualisation", action="store_true") parser.add_option("--memchecker", action="store_true") # Cache Options parser.add_option("--external-memory-system", type="string", help="use external ports of this port_type for caches") parser.add_option("--tlm-memory", type="string", help="use external port for SystemC TLM cosimulation") parser.add_option("--caches", action="store_true") parser.add_option("--l2cache", action="store_true") parser.add_option("--fastmem", action="store_true") parser.add_option("--num-dirs", type="int", default=1) parser.add_option("--num-l2caches", type="int", default=1) parser.add_option("--num-l3caches", type="int", default=1) parser.add_option("--l1d_size", type="string", default="64kB") parser.add_option("--l1i_size", type="string", default="32kB") parser.add_option("--l2_size", type="string", default="2MB") parser.add_option("--l3_size", type="string", default="16MB") parser.add_option("--l1d_assoc", type="int", default=2) parser.add_option("--l1i_assoc", type="int", default=2) parser.add_option("--l2_assoc", type="int", default=8) parser.add_option("--l3_assoc", type="int", default=16) parser.add_option("--cacheline_size", type="int", default=64) # dist-gem5 options parser.add_option("--dist", action="store_true", help="Parallel distributed gem5 simulation.") parser.add_option("--is-switch", action="store_true", help="Select the network switch simulator process for a"\ "distributed gem5 run") parser.add_option("--dist-rank", default=0, action="store", type="int", help="Rank of this system within the dist gem5 run.") parser.add_option( "--dist-size", default=0, action="store", type="int", help="Number of gem5 processes within the dist gem5 run.") parser.add_option( "--dist-server-name", default="127.0.0.1", action="store", type="string", help="Name of the message server host\nDEFAULT: localhost") parser.add_option("--dist-server-port", default=2200, action="store", type="int", help="Message server listen port\nDEFAULT: 2200") parser.add_option( "--dist-sync-repeat", default="0us", action="store", type="string", help= "Repeat interval for synchronisation barriers among dist-gem5 processes\nDEFAULT: --ethernet-linkdelay" ) parser.add_option( "--dist-sync-start", default="5200000000000t", action="store", type="string", help= "Time to schedule the first dist synchronisation barrier\nDEFAULT:5200000000000t" ) parser.add_option("--ethernet-linkspeed", default="10Gbps", action="store", type="string", help="Link speed in bps\nDEFAULT: 10Gbps") parser.add_option("--ethernet-linkdelay", default="10us", action="store", type="string", help="Link delay in seconds\nDEFAULT: 10us") # Enable Ruby parser.add_option("--ruby", action="store_true") # Run duration options parser.add_option("-m", "--abs-max-tick", type="int", default=m5.MaxTick, metavar="TICKS", help="Run to absolute simulated tick " \ "specified including ticks from a restored checkpoint") parser.add_option("--rel-max-tick", type="int", default=None, metavar="TICKS", help="Simulate for specified number of" \ " ticks relative to the simulation start tick (e.g. if " \ "restoring a checkpoint)") parser.add_option("--maxtime", type="float", default=None, help="Run to the specified absolute simulated time in " \ "seconds") parser.add_option("-I", "--maxinsts", action="store", type="int", default=None, help="""Total number of instructions to simulate (default: run forever)""") parser.add_option("--work-item-id", action="store", type="int", help="the specific work id for exit & checkpointing") parser.add_option("--num-work-ids", action="store", type="int", help="Number of distinct work item types") parser.add_option("--work-begin-cpu-id-exit", action="store", type="int", help="exit when work starts on the specified cpu") parser.add_option("--work-end-exit-count", action="store", type="int", help="exit at specified work end count") parser.add_option("--work-begin-exit-count", action="store", type="int", help="exit at specified work begin count") parser.add_option("--init-param", action="store", type="int", default=0, help="""Parameter available in simulation with m5 initparam""") parser.add_option("--initialize-only", action="store_true", default=False, help="""Exit after initialization. Do not simulate time. Useful when gem5 is run as a library.""") # Simpoint options parser.add_option("--simpoint-profile", action="store_true", help="Enable basic block profiling for SimPoints") parser.add_option("--simpoint-interval", type="int", default=10000000, help="SimPoint interval in num of instructions") parser.add_option( "--take-simpoint-checkpoints", action="store", type="string", help="<simpoint file,weight file,interval-length,warmup-length>") parser.add_option("--restore-simpoint-checkpoint", action="store_true", help="restore from a simpoint checkpoint taken with " + "--take-simpoint-checkpoints") # Checkpointing options ###Note that performing checkpointing via python script files will override ###checkpoint instructions built into binaries. parser.add_option( "--take-checkpoints", action="store", type="string", help="<M,N> take checkpoints at tick M and every N ticks thereafter") parser.add_option("--max-checkpoints", action="store", type="int", help="the maximum number of checkpoints to drop", default=5) parser.add_option("--checkpoint-dir", action="store", type="string", help="Place all checkpoints in this absolute directory") parser.add_option("-r", "--checkpoint-restore", action="store", type="int", help="restore from checkpoint <N>") parser.add_option("--checkpoint-at-end", action="store_true", help="take a checkpoint at end of run") parser.add_option("--work-begin-checkpoint-count", action="store", type="int", help="checkpoint at specified work begin count") parser.add_option("--work-end-checkpoint-count", action="store", type="int", help="checkpoint at specified work end count") parser.add_option( "--work-cpus-checkpoint-count", action="store", type="int", help="checkpoint and exit when active cpu count is reached") parser.add_option("--restore-with-cpu", action="store", type="choice", default="atomic", choices=CpuConfig.cpu_names(), help="cpu type for restoring from a checkpoint") # CPU Switching - default switch model goes from a checkpoint # to a timing simple CPU with caches to warm up, then to detailed CPU for # data measurement parser.add_option( "--repeat-switch", action="store", type="int", default=None, help="switch back and forth between CPUs with period <N>") parser.add_option( "-s", "--standard-switch", action="store", type="int", default=None, help="switch from timing to Detailed CPU after warmup period of <N>") parser.add_option("-p", "--prog-interval", type="str", help="CPU Progress Interval") # Fastforwarding and simpoint related materials parser.add_option( "-W", "--warmup-insts", action="store", type="int", default=None, help="Warmup period in total instructions (requires --standard-switch)" ) parser.add_option( "--bench", action="store", type="string", default=None, help="base names for --take-checkpoint and --checkpoint-restore") parser.add_option( "-F", "--fast-forward", action="store", type="string", default=None, help="Number of instructions to fast forward before switching") parser.add_option( "-S", "--simpoint", action="store_true", default=False, help="""Use workload simpoints as an instruction offset for --checkpoint-restore or --take-checkpoint.""") parser.add_option( "--at-instruction", action="store_true", default=False, help="""Treat value of --checkpoint-restore or --take-checkpoint as a number of instructions.""") parser.add_option( "--spec-input", default="ref", type="choice", choices=["ref", "test", "train", "smred", "mdred", "lgred"], help="Input set size for SPEC CPU2000 benchmarks.") parser.add_option("--arm-iset", default="arm", type="choice", choices=["arm", "thumb", "aarch64"], help="ARM instruction set.")
import subprocess import m5 from m5.objects import * from m5.util import addToPath addToPath("../") from common import MemConfig from common import HMC parser = optparse.OptionParser() # Use a HMC_2500_x32 by default parser.add_option( "--mem-type", type="choice", default="HMC_2500_x32", choices=MemConfig.mem_names(), help="type of memory to use" ) parser.add_option("--ranks", "-r", type="int", default=1, help="Number of ranks to iterate across") parser.add_option("--rd_perc", type="int", default=100, help="Percentage of read commands") parser.add_option( "--mode", type="choice", default="DRAM", choices=["DRAM", "DRAM_ROTATE", "RANDOM"], help="DRAM: Random traffic; \ DRAM_ROTATE: Traffic rotating across banks and ranks", )
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "riscv": test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, np, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions, vio_9p=options.vio_9p, bootloader=options.bootloader, ) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if buildEnv['TARGET_ISA'] == 'riscv': test_sys.workload.bootloader = options.kernel elif options.kernel is not None: test_sys.workload.object_file = binary(options.kernel) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np) ] if ObjectList.is_kvm_cpu(TestCPUClass) or \ ObjectList.is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: bootmem = getattr(test_sys, '_bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.simpoint_profile: if not ObjectList.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in range(np): if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() if not ObjectList.is_kvm_cpu(TestCPUClass): if options.bp_type: bpClass = ObjectList.bp_list.get(options.bp_type) test_sys.cpu[i].branchPred = bpClass() if options.indirect_bp_type: IndirectBPClass = ObjectList.indirect_bp_list.get( options.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) ''' pmu_listeners = [] for cpu in test_sys.cpu: if buildEnv['TARGET_ISA'] in "arm": for isa in cpu.isa: isa.pmu = ArmPMU(interrupt=ArmPPI(num=20)) isa.pmu.addArchEvents( cpu=cpu, dtb=cpu.dtb, itb=cpu.itb, icache=getattr(cpu, "icache", None), dcache=getattr(cpu, "dcache", None), l2cache=getattr(test_sys, "l2", None)) pmu_listeners.append(PmuListener( cpu=cpu, dtb=cpu.dtb, itb=cpu.itb, icache=getattr(cpu, "icache", None), dcache=getattr(cpu, "dcache", None), l2cache=getattr(test_sys, "l2", None), bpred=getattr(cpu, "branchPred", None), )) test_sys.pmu_listeners = pmu_listeners ''' for cpu in test_sys.cpu: if buildEnv['TARGET_ISA'] in "arm": for isa in cpu.isa: isa.pmu = ArmPMU(interrupt=ArmPPI(num=20)) isa.pmu.addArchEvents(cpu=cpu, dtb=cpu.dtb, itb=cpu.itb, icache=getattr(cpu, "icache", None), dcache=getattr(cpu, "dcache", None), l2cache=getattr(test_sys, "l2", None)) return test_sys
def build_test_system(np, simplessd): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, simplessd, options.num_cpus, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, simplessd, options.num_cpus, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np) ] if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if buildEnv['TARGET_ISA'] in "x86": test_sys.eventq_index = np if options.ruby: bootmem = getattr(test_sys, 'bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: gicv2m_range = AddrRange(0x2c1c0000, 0x2c1d0000 - 1) if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave if buildEnv['TARGET_ISA'] in "arm": if options.machine_type == "VExpress_GEM5_V1": test_sys.iobridge = Bridge(delay='50ns', ranges=[gicv2m_range]) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave elif not options.external_memory_system: mem_ranges = list(test_sys.mem_ranges) # Copy list not reference # Bypass MSI/MSI-X if buildEnv['TARGET_ISA'] in "arm": if options.machine_type == "VExpress_GEM5_V1": mem_ranges.append(gicv2m_range) test_sys.iobridge = Bridge(delay='50ns', ranges=mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.simpoint_profile: if not CpuConfig.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in range(np): if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() if options.bp_type: bpClass = BPConfig.get(options.bp_type) test_sys.cpu[i].branchPred = bpClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) if buildEnv['TARGET_ISA'] in "x86": lapics = [] for i in range(np): lapics.append(test_sys.cpu[i].interrupts[0]) test_sys.msi_handler.lapics = lapics if buildEnv['TARGET_ISA'] in "x86" and test_sys.eventq_index == np: test_sys.eventq_index = 0 for idx, cpu in enumerate(test_sys.cpu): for obj in cpu.descendants(): obj.eventq_index = test_sys.eventq_index cpu.eventq_index = idx + 1 return test_sys
def _listMemTypes(option, opt, value, parser): MemConfig.print_mem_list() sys.exit(0)
assert(options.num_cpus == len(system.ruby._cpu_ports)) system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, voltage_domain = system.voltage_domain) for i in xrange(np): ruby_port = system.ruby._cpu_ports[i] # Create the interrupt controller and connect its ports to Ruby # Note that the interrupt controller is always present but only # in x86 does it have message ports that need to be connected system.cpu[i].createInterruptController() # Connect the cpu's cache ports to Ruby system.cpu[i].icache_port = ruby_port.slave system.cpu[i].dcache_port = ruby_port.slave if buildEnv['TARGET_ISA'] == 'x86': system.cpu[i].interrupts[0].pio = ruby_port.master system.cpu[i].interrupts[0].int_master = ruby_port.slave system.cpu[i].interrupts[0].int_slave = ruby_port.master system.cpu[i].itb.walker.port = ruby_port.slave system.cpu[i].dtb.walker.port = ruby_port.slave else: MemClass = Simulation.setMemClass(options) system.membus = SystemXBar() system.system_port = system.membus.slave CacheConfig.config_cache(options, system) MemConfig.config_mem(options, system) root = Root(full_system = False, system = system) Simulation.run(options, root, system, FutureClass)
def addNoISAOptions(parser): parser.add_option("-n", "--num-cpus", type="int", default=1) parser.add_option("--sys-voltage", action="store", type="string", default='1.0V', help = """Top-level voltage for blocks running at system power supply""") parser.add_option("--sys-clock", action="store", type="string", default='1GHz', help = """Top-level clock for blocks running at system speed""") # Memory Options parser.add_option("--list-mem-types", action="callback", callback=_listMemTypes, help="List available memory types") parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", choices=MemConfig.mem_names(), help = "type of memory to use") parser.add_option("--mem-channels", type="int", default=1, help = "number of memory channels") parser.add_option("--mem-ranks", type="int", default=None, help = "number of memory ranks per channel") parser.add_option("--mem-size", action="store", type="string", default="512MB", help="Specify the physical memory size (single memory)") parser.add_option("--memchecker", action="store_true") # Cache Options parser.add_option("--external-memory-system", type="string", help="use external ports of this port_type for caches") parser.add_option("--tlm-memory", type="string", help="use external port for SystemC TLM cosimulation") parser.add_option("--caches", action="store_true") parser.add_option("--l2cache", action="store_true") parser.add_option("--num-dirs", type="int", default=1) parser.add_option("--num-l2caches", type="int", default=1) parser.add_option("--num-l3caches", type="int", default=1) parser.add_option("--l1d_size", type="string", default="64kB") parser.add_option("--l1i_size", type="string", default="32kB") parser.add_option("--l2_size", type="string", default="2MB") parser.add_option("--l3_size", type="string", default="16MB") parser.add_option("--l1d_assoc", type="int", default=2) parser.add_option("--l1i_assoc", type="int", default=2) parser.add_option("--l2_assoc", type="int", default=8) parser.add_option("--l3_assoc", type="int", default=16) parser.add_option("--cacheline_size", type="int", default=64) # Enable Ruby parser.add_option("--ruby", action="store_true") # Run duration options parser.add_option("-m", "--abs-max-tick", type="int", default=m5.MaxTick, metavar="TICKS", help="Run to absolute simulated tick " "specified including ticks from a restored checkpoint") parser.add_option("--rel-max-tick", type="int", default=None, metavar="TICKS", help="Simulate for specified number of" " ticks relative to the simulation start tick (e.g. if " "restoring a checkpoint)") parser.add_option("--maxtime", type="float", default=None, help="Run to the specified absolute simulated time in " "seconds")
def addNoISAOptions(parser): parser.add_option("-n", "--num-cpus", type="int", default=1) parser.add_option("--sys-voltage", action="store", type="string", default='1.0V', help="""Top-level voltage for blocks running at system power supply""") parser.add_option("--sys-clock", action="store", type="string", default='1GHz', help="""Top-level clock for blocks running at system speed""") # Memory Options parser.add_option("--list-mem-types", action="callback", callback=_listMemTypes, help="List available memory types") parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", choices=MemConfig.mem_names(), help="type of memory to use") parser.add_option("--mem-channels", type="int", default=1, help="number of memory channels") parser.add_option("--mem-ranks", type="int", default=None, help="number of memory ranks per channel") parser.add_option("--mem-size", action="store", type="string", default="512MB", help="Specify the physical memory size (single memory)") parser.add_option("--memchecker", action="store_true") # Cache Options parser.add_option("--external-memory-system", type="string", help="use external ports of this port_type for caches") parser.add_option("--tlm-memory", type="string", help="use external port for SystemC TLM cosimulation") parser.add_option("--caches", action="store_true") parser.add_option("--l2cache", action="store_true") parser.add_option("--num-dirs", type="int", default=1) parser.add_option("--num-l2caches", type="int", default=1) parser.add_option("--num-l3caches", type="int", default=1) parser.add_option("--l1d_size", type="string", default="64kB") parser.add_option("--l1i_size", type="string", default="32kB") parser.add_option("--l2_size", type="string", default="2MB") parser.add_option("--l3_size", type="string", default="16MB") parser.add_option("--l1d_assoc", type="int", default=2) parser.add_option("--l1i_assoc", type="int", default=2) parser.add_option("--l2_assoc", type="int", default=8) parser.add_option("--l3_assoc", type="int", default=16) parser.add_option("--cacheline_size", type="int", default=64) # Enable Ruby parser.add_option("--ruby", action="store_true") # Run duration options parser.add_option("-m", "--abs-max-tick", type="int", default=m5.MaxTick, metavar="TICKS", help="Run to absolute simulated tick " "specified including ticks from a restored checkpoint") parser.add_option("--rel-max-tick", type="int", default=None, metavar="TICKS", help="Simulate for specified number of" " ticks relative to the simulation start tick (e.g. if " "restoring a checkpoint)") parser.add_option("--maxtime", type="float", default=None, help="Run to the specified absolute simulated time in " "seconds")
# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock # is actually used only by the caches connected to the CPU. system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, voltage_domain = system.cpu_voltage_domain) # All cpus belong to a common cpu_clk_domain, therefore running at a common # frequency. for cpu in system.cpu: cpu.clk_domain = system.cpu_clk_domain # BaseCPU no longer has default values for the BaseCPU.isa # createThreads() is needed to fill in the cpu.isa for cpu in system.cpu: cpu.createThreads() # Assign input trace files to the Trace CPU system.cpu.instTraceFile=options.inst_trace_file system.cpu.dataTraceFile=options.data_trace_file # Configure the classic memory system options MemClass = Simulation.setMemClass(options) system.membus = SystemXBar() system.system_port = system.membus.slave CacheConfig.config_cache(options, system) MemConfig.config_mem(options, system) root = Root(full_system = False, system = system) Simulation.run(options, root, system, FutureClass)
def setMemClass(options): """Returns a memory controller class.""" return MemConfig.get(options.mem_type)
def create(args): ''' Create and configure the system object. ''' if not args.dtb: dtb_file = SysPaths.binary("armv8_gem5_v1_%icpu.%s.dtb" % (args.num_cores, default_dist_version)) else: dtb_file = args.dtb if args.script and not os.path.isfile(args.script): print "Error: Bootscript %s does not exist" % args.script sys.exit(1) cpu_class = cpu_types[args.cpu][0] mem_mode = cpu_class.memory_mode() # Only simulate caches when using a timing CPU (e.g., the HPI model) want_caches = True if mem_mode == "timing" else False system = devices.SimpleSystem(want_caches, args.mem_size, mem_mode=mem_mode, dtb_filename=dtb_file, kernel=SysPaths.binary(args.kernel), readfile=args.script, machine_type="DTOnly") MemConfig.config_mem(args, system) # Add the PCI devices we need for this system. The base system # doesn't have any PCI devices by default since they are assumed # to be added by the configurastion scripts needin them. system.pci_devices = [ # Create a VirtIO block device for the system's boot # disk. Attach the disk image using gem5's Copy-on-Write # functionality to avoid writing changes to the stored copy of # the disk image. PciVirtIO(vio=VirtIOBlock(image=create_cow_image(args.disk_image))), ] # Attach the PCI devices to the system. The helper method in the # system assigns a unique PCI bus ID to each of the devices and # connects them to the IO bus. for dev in system.pci_devices: system.attach_pci(dev) # Wire up the system's memory system system.connect() # Add CPU clusters to the system system.cpu_cluster = [ devices.CpuCluster(system, args.num_cores, args.cpu_freq, "1.0V", *cpu_types[args.cpu]), ] # Create a cache hierarchy for the cluster. We are assuming that # clusters have core-private L1 caches and an L2 that's shared # within the cluster. for cluster in system.cpu_cluster: system.addCaches(want_caches, last_cache_level=2) # Setup gem5's minimal Linux boot loader. system.realview.setupBootLoader(system.membus, system, SysPaths.binary) # Linux boot command flags kernel_cmd = [ # Tell Linux to use the simulated serial port as a console "console=ttyAMA0", # Hard-code timi "lpj=19988480", # Disable address space randomisation to get a consistent # memory layout. "norandmaps", # Tell Linux where to find the root disk image. "root=/dev/vda1", # Mount the root disk read-write by default. "rw", # Tell Linux about the amount of physical memory present. "mem=%s" % args.mem_size, ] system.boot_osflags = " ".join(kernel_cmd) return system
system.workload.dtb_filename = args.dtb_filename else: generateDtb(system) system.workload.dtb_filename = path.join(m5.options.outdir, 'device.dtb') # Default DTB address if bbl is bulit with --with-dts option system.workload.dtb_addr = 0x87e00000 # Linux boot command flags if args.command_line: system.workload.command_line = args.command_line else: kernel_cmd = ["console=ttyS0", "root=/dev/vda", "ro"] system.workload.command_line = " ".join(kernel_cmd) # ---------------------------- Default Setup --------------------------- # if args.elastic_trace_en and args.checkpoint_restore == None and \ not args.fast_forward: CpuConfig.config_etrace(CPUClass, system.cpu, args) CacheConfig.config_cache(args, system) MemConfig.config_mem(args, system) root = Root(full_system=True, system=system) Simulation.setWorkCountOptions(system, args) Simulation.run(args, root, system, FutureClass)
try: import google.protobuf except: print("Please install the Python protobuf module") exit(-1) import packet_pb2 else: print("Failed to import packet proto definitions") exit(-1) parser = optparse.OptionParser() parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", choices=MemConfig.mem_names(), help = "type of memory to use") parser.add_option("--mem-size", action="store", type="string", default="16MB", help="Specify the memory size") parser.add_option("--reuse-trace", action="store_true", help="Prevent generation of traces and reuse existing") (options, args) = parser.parse_args() if args: print("Error: script doesn't take any positional arguments") sys.exit(1) # start by creating the system itself, using a multi-layer 2.0 GHz # crossbar, delivering 64 bytes / 3 cycles (one header cycle) which
def addNoISAOptions(parser): parser.add_option("-n", "--num-cpus", type="int", default=1) parser.add_option("--sys-voltage", action="store", type="string", default='1.0V', help = """Top-level voltage for blocks running at system power supply""") parser.add_option("--sys-clock", action="store", type="string", default='1GHz', help = """Top-level clock for blocks running at system speed""") # Memory Options parser.add_option("--list-mem-types", action="callback", callback=_listMemTypes, help="List available memory types") parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", choices=MemConfig.mem_names(), help = "type of memory to use") parser.add_option("--mem-channels", type="int", default=1, help = "number of memory channels") parser.add_option("--mem-ranks", type="int", default=None, help = "number of memory ranks per channel") parser.add_option("--mem-size", action="store", type="string", default="512MB", help="Specify the physical memory size (single memory)") parser.add_option("--memchecker", action="store_true") parser.add_option("--membus-width", type="int", default=16, help="System membus Width") # Cache Options parser.add_option("--external-memory-system", type="string", help="use external ports of this port_type for caches") parser.add_option("--tlm-memory", type="string", help="use external port for SystemC TLM cosimulation") parser.add_option("--caches", action="store_true") parser.add_option("--l2cache", action="store_true") parser.add_option("--num-dirs", type="int", default=1) parser.add_option("--num-l2caches", type="int", default=1) parser.add_option("--num-l3caches", type="int", default=1) parser.add_option("--l1d_size", type="string", default="64kB") parser.add_option("--l1i_size", type="string", default="32kB") parser.add_option("--l2_size", type="string", default="2MB") parser.add_option("--l3_size", type="string", default="16MB") parser.add_option("--l1d_assoc", type="int", default=2) parser.add_option("--l1i_assoc", type="int", default=2) parser.add_option("--l2_assoc", type="int", default=8) parser.add_option("--l3_assoc", type="int", default=16) parser.add_option("--cacheline_size", type="int", default=64) parser.add_option("--l2bus-width", type="int", default=32, help="L2 Bus Width") # DerivO3CPU Options parser.add_option("--fetchToDecodeDelay", type="int", default=1, help="Fetch to decode delay") parser.add_option("--decodeToRenameDelay", type="int", default=1, help="Decode to rename delay") parser.add_option("--renameToIEWDelay", type="int", default=2, help="Rename to IEW delay") parser.add_option("--iewToCommitDelay", type="int", default=1, help="Issue/Execute/Writeback to commit") parser.add_option("--issueToExecuteDelay", type="int", default=1, help="Issue to execute delay") parser.add_option("--renameToROBDelay", type="int", default=1, help="Rename to reorder buffer delay") parser.add_option("--fetchWidth", type="int", default=5, help="Fetch width") parser.add_option("--decodeWidth", type="int", default=5, help="Decode width") parser.add_option("--renameWidth", type="int", default=5, help="Rename width") parser.add_option("--dispatchWidth", type="int", default=5, help="Dispatch width") parser.add_option("--issueWidth", type="int", default=5, help="issue width") parser.add_option("--wbWidth", type="int", default=5, help="Writeback width") parser.add_option("--commitWidth", type="int", default=5, help="Commit width") parser.add_option("--squashWidth", type="int", default=5, help="Squash width") parser.add_option("--numPhysIntRegs", type="int", default=256, help="Number of physical integer registers") parser.add_option("--numPhysFloatRegs", type="int", default=256, help="Number of physical floating registers") parser.add_option("--numPhysVecRegs", type="int", default=256, help="Number of physical vector registers") parser.add_option("--numROBEntries", type="int", default=128, help="Number of reorder buffer entries") # Enable Ruby parser.add_option("--ruby", action="store_true") # Run duration options parser.add_option("-m", "--abs-max-tick", type="int", default=m5.MaxTick, metavar="TICKS", help="Run to absolute simulated tick " "specified including ticks from a restored checkpoint") parser.add_option("--rel-max-tick", type="int", default=None, metavar="TICKS", help="Simulate for specified number of" " ticks relative to the simulation start tick (e.g. if " "restoring a checkpoint)") parser.add_option("--maxtime", type="float", default=None, help="Run to the specified absolute simulated time in " "seconds")
import google.protobuf except: print("Please install the Python protobuf module") exit(-1) import packet_pb2 else: print("Failed to import packet proto definitions") exit(-1) parser = optparse.OptionParser() parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", choices=MemConfig.mem_names(), help="type of memory to use") parser.add_option("--mem-size", action="store", type="string", default="16MB", help="Specify the memory size") parser.add_option("--reuse-trace", action="store_true", help="Prevent generation of traces and reuse existing") (options, args) = parser.parse_args() if args: print("Error: script doesn't take any positional arguments") sys.exit(1)
def create(args): ''' Create and configure the system object. ''' if args.readfile and not os.path.isfile(args.readfile): print("Error: Bootscript %s does not exist" % args.readfile) sys.exit(1) object_file = args.kernel if args.kernel else "" cpu_class = cpu_types[args.cpu][0] mem_mode = cpu_class.memory_mode() # Only simulate caches when using a timing CPU (e.g., the HPI model) want_caches = True if mem_mode == "timing" else False platform = ObjectList.platform_list.get(args.machine_type) system = devices.simpleSystem(ArmSystem, want_caches, args.mem_size, platform=platform(), mem_mode=mem_mode, readfile=args.readfile) MemConfig.config_mem(args, system) if args.semi_enable: system.semihosting = ArmSemihosting(stdin=args.semi_stdin, stdout=args.semi_stdout, stderr=args.semi_stderr, files_root_dir=args.semi_path, cmd_line=" ".join([object_file] + args.args)) # Add the PCI devices we need for this system. The base system # doesn't have any PCI devices by default since they are assumed # to be added by the configurastion scripts needin them. pci_devices = [] if args.disk_image: # Create a VirtIO block device for the system's boot # disk. Attach the disk image using gem5's Copy-on-Write # functionality to avoid writing changes to the stored copy of # the disk image. system.disk = PciVirtIO(vio=VirtIOBlock( image=create_cow_image(args.disk_image))) pci_devices.append(system.disk) # Attach the PCI devices to the system. The helper method in the # system assigns a unique PCI bus ID to each of the devices and # connects them to the IO bus. for dev in pci_devices: system.attach_pci(dev) # Wire up the system's memory system system.connect() # Add CPU clusters to the system system.cpu_cluster = [ devices.CpuCluster(system, args.num_cores, args.cpu_freq, "1.0V", *cpu_types[args.cpu]), ] # Create a cache hierarchy for the cluster. We are assuming that # clusters have core-private L1 caches and an L2 that's shared # within the cluster. for cluster in system.cpu_cluster: system.addCaches(want_caches, last_cache_level=2) # Setup gem5's minimal Linux boot loader. system.auto_reset_addr = True # Using GICv3 system.realview.gic.gicv4 = False system.highest_el_is_64 = True system.have_virtualization = True system.have_security = True workload_class = workloads.workload_list.get(args.workload) system.workload = workload_class(object_file, system) return system
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, options.membus_width, options, options.num_cpus, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, ignore_dtb=options.generate_dtb, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in xrange(np) ] if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: bootmem = getattr(test_sys, 'bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.fastmem: if TestCPUClass != AtomicSimpleCPU: fatal("Fastmem can only be used with atomic CPU!") if (options.caches or options.l2cache): fatal("You cannot use fastmem in combination with caches!") if options.simpoint_profile: if not options.fastmem: # Atomic CPU checked with fastmem option already fatal( "SimPoint generation should be done with atomic cpu and fastmem" ) if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in xrange(np): if options.fastmem: test_sys.cpu[i].fastmem = True if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) if buildEnv['TARGET_ISA'] != "arm" and options.workload_automation_vio: warn("Ignoring --workload-automation-vio. It is unsupported on " "non-ARM systems.") elif options.workload_automation_vio: from m5.objects import PciVirtIO, VirtIO9PDiod viopci = PciVirtIO( pci_bus=0, pci_dev=test_sys.realview._num_pci_dev, pci_func=0, InterruptPin=1, InterruptLine=test_sys.realview._num_pci_int_line) test_sys.realview._num_pci_dev = test_sys.realview._num_pci_dev + 1 test_sys.realview._num_pci_int_line = test_sys.realview._num_pci_int_line + 1 viopci.vio = VirtIO9PDiod() viopci.vio.root = options.workload_automation_vio viopci.vio.socketPath = "/home/yqureshi/shares/local/scrap/temp" test_sys.realview.viopci = viopci test_sys.realview.viopci.dma = test_sys.iobus.slave test_sys.realview.viopci.pio = test_sys.iobus.master CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) return test_sys
def addNoISAOptions(parser): parser.add_option("-n", "--num-cpus", type="int", default=1) parser.add_option("--sys-voltage", action="store", type="string", default='1.0V', help = """Top-level voltage for blocks running at system power supply""") parser.add_option("--sys-clock", action="store", type="string", default='1GHz', help = """Top-level clock for blocks running at system speed""") # Memory Options parser.add_option("--list-mem-types", action="callback", callback=_listMemTypes, help="List available memory types") parser.add_option("--mem-type", type="choice", default="HBM_2000_8H_x256_BL8_PK", choices=MemConfig.mem_names(), help = "type of memory to use") parser.add_option("--mem-channels", type="int", default=4, help = "number of memory channels") parser.add_option("--mem-ranks", type="int", default=None, help = "number of memory ranks per channel") parser.add_option("--mem-size", action="store", type="string", default="8GB", help="Specify the physical memory size (single memory)") parser.add_option("--memchecker", action="store_true") # Cache Options parser.add_option("--external-memory-system", type="string", help="use external ports of this port_type for caches") parser.add_option("--tlm-memory", type="string", help="use external port for SystemC TLM cosimulation") parser.add_option("--caches", action="store_true", default="True") parser.add_option("--l2cache", action="store_true", default="True") parser.add_option("--num-dirs", type="int", default=1) parser.add_option("--num-l2caches", type="int", default=1) parser.add_option("--num-l3caches", type="int", default=1) parser.add_option("--l1d_size", type="string", default="64kB") parser.add_option("--l1i_size", type="string", default="64kB") parser.add_option("--l2_size", type="string", default="8MB") parser.add_option("--l2_bankbit", type="int", default="2") parser.add_option("--l3_size", type="string", default="16MB") parser.add_option("--l1d_assoc", type="int", default=4) parser.add_option("--l1i_assoc", type="int", default=4) parser.add_option("--l2_assoc", type="int", default=16) parser.add_option("--l3_assoc", type="int", default=16) parser.add_option("--cacheline_size", type="int", default=256) # Bus bandwidth options parser.add_option("--mem_bus_width", type="int", default=32) parser.add_option("--mem_resp_width", type="int", default=64) parser.add_option("--mem_front_lat", type="int", default=10) parser.add_option("--mem_forw_lat", type="int", default=10) parser.add_option("--mem_resp_lat", type="int", default=10) parser.add_option("--l2_bus_width", type="int", default=64) parser.add_option("--l2_resp_width", type="int", default=128) # Enable Ruby parser.add_option("--ruby", action="store_true") # Run duration options parser.add_option("-m", "--abs-max-tick", type="int", default=m5.MaxTick, metavar="TICKS", help="Run to absolute simulated tick " "specified including ticks from a restored checkpoint") parser.add_option("--rel-max-tick", type="int", default=None, metavar="TICKS", help="Simulate for specified number of" " ticks relative to the simulation start tick (e.g. if " "restoring a checkpoint)") parser.add_option("--maxtime", type="float", default=None, help="Run to the specified absolute simulated time in " "seconds") parser.add_option("--show-flops", action="store_true", help="Display Flops and Bytes at every dumpstat (o3 only)") parser.add_option("--show-flops-detailed", action="store_true", help="Display Flops and Bytes at every dumpstat - detailed version (o3 only)")
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "riscv": test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], args.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, args.machine_type, np, bm[0], args.dtb_filename, bare_metal=args.bare_metal, cmdline=cmdline, external_memory=args.external_memory_system, ruby=args.ruby, vio_9p=args.vio_9p, bootloader=args.bootloader, ) if args.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = args.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=args.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=args.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=args.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if buildEnv['TARGET_ISA'] == 'riscv': test_sys.workload.bootloader = args.kernel elif args.kernel is not None: test_sys.workload.object_file = binary(args.kernel) if args.script is not None: test_sys.readfile = args.script test_sys.init_param = args.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np) ] if args.ruby: bootmem = getattr(test_sys, '_bootmem', None) Ruby.create_system(args, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=args.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.mem_side_ports = test_sys.ruby._io_port.in_ports for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() test_sys.ruby._cpu_ports[i].connectCpuPorts(cpu) else: if args.caches or args.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.mem_side_ports test_sys.iocache.mem_side = test_sys.membus.cpu_side_ports elif not args.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.cpu_side_port = test_sys.iobus.mem_side_ports test_sys.iobridge.mem_side_port = test_sys.membus.cpu_side_ports # Sanity check if args.simpoint_profile: if not ObjectList.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in range(np): if args.simpoint_profile: test_sys.cpu[i].addSimPointProbe(args.simpoint_interval) if args.checker: test_sys.cpu[i].addCheckerCpu() if not ObjectList.is_kvm_cpu(TestCPUClass): if args.bp_type: bpClass = ObjectList.bp_list.get(args.bp_type) test_sys.cpu[i].branchPred = bpClass() if args.indirect_bp_type: IndirectBPClass = ObjectList.indirect_bp_list.get( args.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if args.elastic_trace_en and args.checkpoint_restore == None and \ not args.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, args) CacheConfig.config_cache(args, test_sys) MemConfig.config_mem(args, test_sys) if ObjectList.is_kvm_cpu(TestCPUClass) or \ ObjectList.is_kvm_cpu(FutureClass): # Assign KVM CPUs to their own event queues / threads. This # has to be done after creating caches and other child objects # since these mustn't inherit the CPU event queue. for i, cpu in enumerate(test_sys.cpu): # Child objects usually inherit the parent's event # queue. Override that and use the same event queue for # all devices. for obj in cpu.descendants(): obj.eventq_index = 0 cpu.eventq_index = i + 1 test_sys.kvm_vm = KvmVM() return test_sys
from common import MemConfig # This script aims at triggering low power state transitions in the DRAM # controller. The traffic generator is used in DRAM mode and traffic # states target a different levels of bank utilization and strides. # At the end after sweeping through bank utilization and strides, we go # through an idle state with no requests to enforce self-refresh. parser = argparse.ArgumentParser( formatter_class=argparse.ArgumentDefaultsHelpFormatter) # Use a single-channel DDR4-2400 in 16x4 configuration by default parser.add_argument("--mem-type", default="DDR4_2400_16x4", choices=MemConfig.mem_names(), help="type of memory to use") parser.add_argument("--mem-ranks", "-r", type=int, default=1, help="Number of ranks to iterate across") parser.add_argument("--page-policy", "-p", choices=["close_adaptive", "open_adaptive"], default="close_adaptive", help="controller page policy") parser.add_argument("--itt-list", "-t", default="1 20 100",
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem(test_mem_mode, options.machine_type, np, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory= options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, voltage_domain = test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, voltage_domain = test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) else: print("Error: a kernel must be provided to run in full system mode") sys.exit(1) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np)] if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: bootmem = getattr(test_sys, 'bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, voltage_domain = test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.simpoint_profile: if not CpuConfig.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal("SimPoint generation not supported with more than one CPUs") for i in range(np): if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() if options.bp_type: bpClass = BPConfig.get(options.bp_type) test_sys.cpu[i].branchPred = bpClass() if options.indirect_bp_type: IndirectBPClass = \ BPConfig.get_indirect(options.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) return test_sys
def run_system_with_cpu( process, options, output_dir, warmup_instructions=0, ): warmup = True # Override the -d outdir --outdir option to gem5 m5.options.outdir = output_dir m5.core.setOutputDir(m5.options.outdir) m5.stats.reset() max_tick = options.abs_max_tick if options.rel_max_tick: max_tick = options.rel_max_tick elif options.maxtime: max_tick = int(options.maxtime * 1000 * 1000 * 1000 * 1000) eprint("Simulating until tick=%s" % (max_tick)) # DerivO3CPU is the configurable out-of-order CPU model supplied by gem5 the_cpu = DerivO3CPU(cpu_id=0, switched_out=warmup) icache = L1_ICache(size=options.l1i_size, assoc=options.l1i_assoc) dcache = L1_DCache(size=options.l1d_size, assoc=options.l1d_assoc) the_cpu.branchPred = LocalBP() # Parameter values the_cpu.numROBEntries = options.ROB the_cpu.numIQEntries = options.IQ real_cpus = [the_cpu] mem_mode = real_cpus[0].memory_mode() if warmup: the_w_cpu = TimingSimpleCPU(cpu_id=0) the_w_cpu.branchPred = LocalBP() # Parameter values the_w_cpu[0].addPrivateSplitL1Caches(icache, dcache, None, None) the_w_cpu[0].createInterruptController() warmup_cpus = [the_w_cpu] if warmup_instructions: warmup_cpus[0].max_insts_any_thread = warmup_instructions else: warmup_cpus = real_cpus system = System(cpu=warmup_cpus, mem_mode=mem_mode, mem_ranges=[AddrRange(options.mem_size)], cache_line_size=options.cacheline_size) system.multi_thread = False system.voltage_domain = VoltageDomain(voltage=options.sys_voltage) system.clk_domain = SrcClockDomain(clock=options.sys_clock, voltage_domain=system.voltage_domain) system.cpu_voltage_domain = VoltageDomain() system.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=system.cpu_voltage_domain) system.cache_line_size = options.cacheline_size cache_line_size = options.cacheline_size for cpu in system.cpu: cpu.clk_domain = system.cpu_clk_domain cpu.workload = process if options.prog_interval: cpu.progress_interval = options.prog_interval cpu.createThreads() MemClass = Simulation.setMemClass(options) system.membus = SystemXBar() system.system_port = system.membus.slave system.cpu[0].connectAllPorts(system.membus) MemConfig.config_mem(options, system) root = Root(full_system=False, system=system) if warmup: for cpu in real_cpus: cpu.clk_domain = system.cpu_clk_domain cpu.workload = process cpu.system = system cpu.switched_out = True cpu.createThreads() root.switch_cpus = real_cpus m5.options.outdir = output_dir m5.instantiate(None) # None == no checkpoint if warmup: eprint("Running warmup with warmup CPU class ({} instrs.)".format( warmup_instructions)) eprint("Starting simulation") exit_event = m5.simulate(max_tick) eprint("exit_event: {}".format(exit_event)) if warmup: max_tick -= m5.curTick() m5.stats.reset() eprint("Finished warmup; running real simulation") m5.switchCpus(system, list(zip(warmup_cpus, real_cpus))) exit_event = m5.simulate(max_tick) eprint("Done simulation @ tick = %s: %s" % (m5.curTick(), exit_event.getCause())) m5.stats.dump()
def addNoISAOptions(parser): # Check for extra nvmain configuration override options for arg in sys.argv: if arg[:9] == "--nvmain-": parser.add_option(arg, type="string", default="NULL", help="Set NVMain configuration value for a parameter") parser.add_option("-n", "--num-cpus", type="int", default=1) parser.add_option("--sys-voltage", action="store", type="string", default='1.0V', help = """Top-level voltage for blocks running at system power supply""") parser.add_option("--sys-clock", action="store", type="string", default='1GHz', help = """Top-level clock for blocks running at system speed""") # Memory Options parser.add_option("--list-mem-types", action="callback", callback=_listMemTypes, help="List available memory types") parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", choices=MemConfig.mem_names(), help = "type of memory to use") parser.add_option("--mem-channels", type="int", default=1, help = "number of memory channels") parser.add_option("--mem-ranks", type="int", default=None, help = "number of memory ranks per channel") parser.add_option("--mem-size", action="store", type="string", default="512MB", help="Specify the physical memory size (single memory)") parser.add_option("--memchecker", action="store_true") # Cache Options parser.add_option("--external-memory-system", type="string", help="use external ports of this port_type for caches") parser.add_option("--tlm-memory", type="string", help="use external port for SystemC TLM cosimulation") parser.add_option("--caches", action="store_true") parser.add_option("--l2cache", action="store_true") parser.add_option("--num-dirs", type="int", default=1) parser.add_option("--num-l2caches", type="int", default=1) parser.add_option("--num-l3caches", type="int", default=1) parser.add_option("--l1d_size", type="string", default="64kB") parser.add_option("--l1i_size", type="string", default="32kB") parser.add_option("--l2_size", type="string", default="2MB") parser.add_option("--l3_size", type="string", default="16MB") parser.add_option("--l1d_assoc", type="int", default=2) parser.add_option("--l1i_assoc", type="int", default=2) parser.add_option("--l2_assoc", type="int", default=8) parser.add_option("--l3_assoc", type="int", default=16) parser.add_option("--cacheline_size", type="int", default=64) # Enable Ruby parser.add_option("--ruby", action="store_true") # Run duration options parser.add_option("-m", "--abs-max-tick", type="int", default=m5.MaxTick, metavar="TICKS", help="Run to absolute simulated tick " "specified including ticks from a restored checkpoint") parser.add_option("--rel-max-tick", type="int", default=None, metavar="TICKS", help="Simulate for specified number of" " ticks relative to the simulation start tick (e.g. if " "restoring a checkpoint)") parser.add_option("--maxtime", type="float", default=None, help="Run to the specified absolute simulated time in " "seconds") parser.add_option("-P", "--param", action="append", default=[], help="Set a SimObject parameter relative to the root node. " "An extended Python multi range slicing syntax can be used " "for arrays. For example: " "'system.cpu[0,1,3:8:2].max_insts_all_threads = 42' " "sets max_insts_all_threads for cpus 0, 1, 3, 5 and 7 " "Direct parameters of the root object are not accessible, " "only parameters of its children.")
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], options.ruby, cmdline=cmdline, cossim_enabled=options.cossim, nodeNum=options.nodeNum) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, options.num_cpus, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions, cossim_enabled=options.cossim, nodeNum=options.nodeNum, system_clock=options.sys_clock, dev_clk=options.device_clock) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in xrange(np) ] if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: # Check for timing mode because ruby does not support atomic accesses if not (options.cpu_type == "DerivO3CPU" or options.cpu_type == "TimingSimpleCPU"): print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" sys.exit(1) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.fastmem: if TestCPUClass != AtomicSimpleCPU: fatal("Fastmem can only be used with atomic CPU!") if (options.caches or options.l2cache): fatal("You cannot use fastmem in combination with caches!") if options.simpoint_profile: if not options.fastmem: # Atomic CPU checked with fastmem option already fatal( "SimPoint generation should be done with atomic cpu and fastmem" ) if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in xrange(np): if options.fastmem: test_sys.cpu[i].fastmem = True if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) return test_sys
def run_system_with_cpu( process, options, output_dir, warmup_cpu_class=None, warmup_instructions=0, real_cpu_create_function=lambda cpu_id: DerivO3CPU(cpu_id=cpu_id), ): # Override the -d outdir --outdir option to gem5 m5.options.outdir = output_dir m5.core.setOutputDir(m5.options.outdir) m5.stats.reset() max_tick = options.abs_max_tick if options.rel_max_tick: max_tick = options.rel_max_tick elif options.maxtime: max_tick = int(options.maxtime * 1000 * 1000 * 1000 * 1000) eprint("Simulating until tick=%s" % (max_tick)) real_cpus = [real_cpu_create_function(0)] mem_mode = real_cpus[0].memory_mode() if warmup_cpu_class: warmup_cpus = [warmup_cpu_class(cpu_id=0)] warmup_cpus[0].max_insts_any_thread = warmup_instructions else: warmup_cpus = real_cpus system = System(cpu=warmup_cpus, mem_mode=mem_mode, mem_ranges=[AddrRange(options.mem_size)], cache_line_size=options.cacheline_size) system.multi_thread = False system.voltage_domain = VoltageDomain(voltage=options.sys_voltage) system.clk_domain = SrcClockDomain(clock=options.sys_clock, voltage_domain=system.voltage_domain) system.cpu_voltage_domain = VoltageDomain() system.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=system.cpu_voltage_domain) system.cache_line_size = options.cacheline_size if warmup_cpu_class: for cpu in real_cpus: cpu.clk_domain = system.cpu_clk_domain cpu.workload = process cpu.system = system cpu.switched_out = True cpu.createThreads() system.switch_cpus = real_cpus for cpu in system.cpu: cpu.clk_domain = system.cpu_clk_domain cpu.workload = process if options.prog_interval: cpu.progress_interval = options.prog_interval cpu.createThreads() MemClass = Simulation.setMemClass(options) system.membus = SystemXBar() system.system_port = system.membus.slave system.cpu[0].connectAllPorts(system.membus) MemConfig.config_mem(options, system) root = Root(full_system=False, system=system) m5.options.outdir = output_dir m5.instantiate(None) # None == no checkpoint if warmup_cpu_class: eprint("Running warmup with warmup CPU class (%d instrs.)" % (warmup_instructions)) eprint("Starting simulation") exit_event = m5.simulate(max_tick) if warmup_cpu_class: max_tick -= m5.curTick() m5.stats.reset() debug_print("Finished warmup; running real simulation") m5.switchCpus(system, real_cpus) exit_event = m5.simulate(max_tick) eprint("Done simulation @ tick = %s: %s" % (m5.curTick(), exit_event.getCause())) m5.stats.dump()
def addNoISAOptions(parser): parser.add_option("-n", "--num-cpus", type="int", default=1) parser.add_option("--sys-voltage", action="store", type="string", default='1.0V', help = """Top-level voltage for blocks running at system power supply""") parser.add_option("--sys-clock", action="store", type="string", default='1GHz', help = """Top-level clock for blocks running at system speed""") # Memory Options parser.add_option("--list-mem-types", action="callback", callback=_listMemTypes, help="List available memory types") parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", choices=MemConfig.mem_names(), help = "type of memory to use") parser.add_option("--mem-channels", type="int", default=1, help = "number of memory channels") parser.add_option("--mem-ranks", type="int", default=None, help = "number of memory ranks per channel") parser.add_option("--mem-size", action="store", type="string", default="512MB", help="Specify the physical memory size (single memory)") parser.add_option("--memchecker", action="store_true") # Cache Options parser.add_option("--external-memory-system", type="string", help="use external ports of this port_type for caches") parser.add_option("--tlm-memory", type="string", help="use external port for SystemC TLM cosimulation") parser.add_option("--caches", action="store_true") parser.add_option("--l2cache", action="store_true") parser.add_option("--num-dirs", type="int", default=1) parser.add_option("--num-l2caches", type="int", default=1) parser.add_option("--num-l3caches", type="int", default=1) parser.add_option("--l1d_size", type="string", default="64kB") parser.add_option("--l1i_size", type="string", default="32kB") parser.add_option("--l2_size", type="string", default="2MB") parser.add_option("--l3_size", type="string", default="16MB") parser.add_option("--l1d_assoc", type="int", default=2) parser.add_option("--l1i_assoc", type="int", default=2) parser.add_option("--l2_assoc", type="int", default=8) parser.add_option("--l3_assoc", type="int", default=16) parser.add_option("--cacheline_size", type="int", default=64) # Enable Ruby parser.add_option("--ruby", action="store_true") # Run duration options parser.add_option("-m", "--abs-max-tick", type="int", default=m5.MaxTick, metavar="TICKS", help="Run to absolute simulated tick " "specified including ticks from a restored checkpoint") parser.add_option("--rel-max-tick", type="int", default=None, metavar="TICKS", help="Simulate for specified number of" " ticks relative to the simulation start tick (e.g. if " "restoring a checkpoint)") parser.add_option("--maxtime", type="float", default=None, help="Run to the specified absolute simulated time in " "seconds") parser.add_option("-P", "--param", action="append", default=[], help="Set a SimObject parameter relative to the root node. " "An extended Python multi range slicing syntax can be used " "for arrays. For example: " "'system.cpu[0,1,3:8:2].max_insts_all_threads = 42' " "sets max_insts_all_threads for cpus 0, 1, 3, 5 and 7 " "Direct parameters of the root object are not accessible, " "only parameters of its children.")