Exemple #1
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def test_virt_chn_qos(flavor):
    """
    Test the QoS of VCs in the NoC

    Test ID: 6

    Description:
    In this test, we send a LOW priority (can be vc_id=0 or vc_id=Max, depending upon cfg) pkt with the maximum size of
    payload and a HIGH priority pkt with a single flit size through the NoC. The src routers which it'll be send will be
    router 0 for the HP pkt and router 1 for the LP one, because it'll be executed at the same time with fork(). Both pkts
    will have as destiny the last Router in NoC thus sharing the same datapath. The expectation is that the HP pkt will
    finish earlier than the LP (assert wr_....) using the same datapath, then we read both and check if the respective
    contents are matching.
    """
    module = os.path.splitext(os.path.basename(__file__))[0]
    SIM_BUILD = os.path.join(
        noc_const.TESTS_DIR,
        f"../../run_dir/sim_build_{noc_const.SIMULATOR}_{module}_{flavor}")
    noc_const.EXTRA_ENV['SIM_BUILD'] = SIM_BUILD
    noc_const.EXTRA_ENV['FLAVOR'] = flavor

    extra_args_sim = noc_const._get_cfg_args(flavor)

    run(python_search=[noc_const.TESTS_DIR],
        includes=noc_const.INC_DIR,
        verilog_sources=noc_const.VERILOG_SOURCES,
        toplevel=noc_const.TOPLEVEL,
        module=module,
        sim_build=SIM_BUILD,
        extra_env=noc_const.EXTRA_ENV,
        extra_args=extra_args_sim)
Exemple #2
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def test_irqs(flavor):
    """
    Test that checks the IRQs modes inside the NoC

    Test ID: 8

    Description:
    Once it's possible to customize the way we drive the IRQ signals inside each Router of the NoC, this test
    checks different cfgs for IRQ_MUX/MASK sending/receiving flits from the NoC.
    """
    module = os.path.splitext(os.path.basename(__file__))[0]
    SIM_BUILD = os.path.join(
        noc_const.TESTS_DIR,
        f"../../run_dir/sim_build_{noc_const.SIMULATOR}_{module}_{flavor}")
    noc_const.EXTRA_ENV['SIM_BUILD'] = SIM_BUILD
    noc_const.EXTRA_ENV['FLAVOR'] = flavor

    extra_args_sim = noc_const._get_cfg_args(flavor)

    run(python_search=[noc_const.TESTS_DIR],
        includes=noc_const.INC_DIR,
        verilog_sources=noc_const.VERILOG_SOURCES,
        toplevel=noc_const.TOPLEVEL,
        module=module,
        sim_build=SIM_BUILD,
        extra_env=noc_const.EXTRA_ENV,
        extra_args=extra_args_sim)
Exemple #3
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def test_noc_csr(flavor):
    """
    Check all WR/RD CSRs inside the NoC

    Test ID: 7

    Description:
    Write/Read to all CSRs of the NoC. It's also write in READ only registers and
    check if DWORD operations are answered with errors too.
    """
    module = os.path.splitext(os.path.basename(__file__))[0]
    SIM_BUILD = os.path.join(
        noc_const.TESTS_DIR,
        f"../../run_dir/sim_build_{noc_const.SIMULATOR}_{module}_{flavor}")
    noc_const.EXTRA_ENV['SIM_BUILD'] = SIM_BUILD
    noc_const.EXTRA_ENV['FLAVOR'] = flavor

    extra_args_sim = noc_const._get_cfg_args(flavor)

    run(python_search=[noc_const.TESTS_DIR],
        includes=noc_const.INC_DIR,
        verilog_sources=noc_const.VERILOG_SOURCES,
        toplevel=noc_const.TOPLEVEL,
        module=module,
        sim_build=SIM_BUILD,
        extra_env=noc_const.EXTRA_ENV,
        extra_args=extra_args_sim)
Exemple #4
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def test_all_buffers(flavor):
    """
    Test if all buffers of all routers are able to transfer flits

    Test ID: 5

    Description:
    In this test, it'll be dispatched single random flits to all the routers (also all VCs) up to the maximum
    to fill all the buffers inside the NoC. Then we read back all the random pkts to see if they're matching
    and were transferred correctly. It's important to highlight that the number of buffers per VC is calculated
    using the default parameter in the ravenoc_define.svh (RD_AXI_BFF(x) x<=2?(1<<x):4) if the user change this macro,
    it should change the line 34 to represent the correct function that calculates the buffers.
    """
    module = os.path.splitext(os.path.basename(__file__))[0]
    SIM_BUILD = os.path.join(
        noc_const.TESTS_DIR,
        f"../../run_dir/sim_build_{noc_const.SIMULATOR}_{module}_{flavor}")
    noc_const.EXTRA_ENV['SIM_BUILD'] = SIM_BUILD
    noc_const.EXTRA_ENV['FLAVOR'] = flavor

    extra_args_sim = noc_const._get_cfg_args(flavor)

    run(python_search=[noc_const.TESTS_DIR],
        includes=noc_const.INC_DIR,
        verilog_sources=noc_const.VERILOG_SOURCES,
        toplevel=noc_const.TOPLEVEL,
        module=module,
        sim_build=SIM_BUILD,
        extra_env=noc_const.EXTRA_ENV,
        extra_args=extra_args_sim)
Exemple #5
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def test_throughput(flavor):
    """
    Test to compute the max throughput of the NoC

    Test ID: 4

    Description:
    In this test we send the maximum payload pkt through the NoC from the router 0 to the
    last router (longest datapath), once we receive the first flit in the destination router,
    we start reading it simultaneously, once both operations are over. We then compare the
    data to check the integrity and compute the total throughput of this pkt over the NoC.
    """
    module = os.path.splitext(os.path.basename(__file__))[0]
    SIM_BUILD = os.path.join(
        noc_const.TESTS_DIR,
        f"../../run_dir/sim_build_{noc_const.SIMULATOR}_{module}_{flavor}")
    noc_const.EXTRA_ENV['SIM_BUILD'] = SIM_BUILD
    noc_const.EXTRA_ENV['FLAVOR'] = flavor

    extra_args_sim = noc_const._get_cfg_args(flavor)

    run(python_search=[noc_const.TESTS_DIR],
        includes=noc_const.INC_DIR,
        verilog_sources=noc_const.VERILOG_SOURCES,
        toplevel=noc_const.TOPLEVEL,
        module=module,
        sim_build=SIM_BUILD,
        extra_env=noc_const.EXTRA_ENV,
        extra_args=extra_args_sim)
Exemple #6
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def test_ravenoc_basic(flavor):
    """
    Basic test that sends a packet over the NoC and checks it

    Test ID: 1

    Description:
    The simplest test to send a pkt over the NoC and checks it by reading back the correspondent destination router.
    """
    module = os.path.splitext(os.path.basename(__file__))[0]
    SIM_BUILD = os.path.join(
        noc_const.TESTS_DIR,
        f"../../run_dir/sim_build_{noc_const.SIMULATOR}_{module}_{flavor}")
    noc_const.EXTRA_ENV['SIM_BUILD'] = SIM_BUILD
    noc_const.EXTRA_ENV['FLAVOR'] = flavor

    extra_args_sim = noc_const._get_cfg_args(flavor)

    run(python_search=[noc_const.TESTS_DIR],
        includes=noc_const.INC_DIR,
        verilog_sources=noc_const.VERILOG_SOURCES,
        toplevel=noc_const.TOPLEVEL,
        module=module,
        sim_build=SIM_BUILD,
        extra_env=noc_const.EXTRA_ENV,
        extra_args=extra_args_sim)
Exemple #7
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def test_max_data(flavor):
    """
    Test if the NoC is capable to transfer a pkt with the max. size

    Test ID: 3

    Description: This test exercise the maximum payload that each pkt in the NoC can transfer
    thus, in a 32-bit NoC this value is equal to 1KB and in a 64-bit NoC, this is equal to 2KB
    of data. It's expected that the received pkt will matching with the correspondent sent one.
    """
    module = os.path.splitext(os.path.basename(__file__))[0]
    SIM_BUILD = os.path.join(noc_const.TESTS_DIR,
            f"../../run_dir/sim_build_{noc_const.SIMULATOR}_{module}_{flavor}")
    noc_const.EXTRA_ENV['SIM_BUILD'] = SIM_BUILD
    noc_const.EXTRA_ENV['FLAVOR'] = flavor

    extra_args_sim = noc_const._get_cfg_args(flavor)

    run(
        python_search=[noc_const.TESTS_DIR],
        includes=noc_const.INC_DIR,
        verilog_sources=noc_const.VERILOG_SOURCES,
        toplevel=noc_const.TOPLEVEL,
        module=module,
        sim_build=SIM_BUILD,
        extra_env=noc_const.EXTRA_ENV,
        extra_args=extra_args_sim
    )
def test_wrong_ops(flavor):
    """
    Checks if the AXI-S/NoC is capable of throwing an errors when illegal operations are executed

    Test ID: 2

    Description:
    Different AXI-S txn are request on the routers to check if wrong/illegal txn are not allowed to move forward in the NoC. It's expected
    the NoC/AXI slave interface to refuse the txn throwing an error on the slave interface due to not supported requests. Here's a list of
    all txns that are sent over this test:
    - Write: Invalid memory address - out of range or not mapped
    - Write: Writing on read buffer region
    - Write: Invalid burst type = FIXED
    - Read: Reading from write buffer region
    - Read: Reading from an invalid memory region - out of range or not mapped
    - Read: Just after the reset, reading from empty buffer

    We don't check if the write on full buffer will thrown an error because by uArch the NoC will generate back pressure on the master if the
    buffers are full and more incoming txns are being requested at the w.address channel.
    """
    module = os.path.splitext(os.path.basename(__file__))[0]
    SIM_BUILD = os.path.join(
        noc_const.TESTS_DIR,
        f"../../run_dir/sim_build_{noc_const.SIMULATOR}_{module}_{flavor}")
    noc_const.EXTRA_ENV['SIM_BUILD'] = SIM_BUILD
    noc_const.EXTRA_ENV['FLAVOR'] = flavor

    extra_args_sim = noc_const._get_cfg_args(flavor)

    run(python_search=[noc_const.TESTS_DIR],
        includes=noc_const.INC_DIR,
        verilog_sources=noc_const.VERILOG_SOURCES,
        toplevel=noc_const.TOPLEVEL,
        module=module,
        sim_build=SIM_BUILD,
        extra_env=noc_const.EXTRA_ENV,
        extra_args=extra_args_sim)