def __init__(self):
config = {
"bit_depth": 12,
"pixels_per_cycle": 4,
"LJ92_fifo_depth": 128,
"out_bits": 32,
"converter": 48,
"converter_fifo_depth": 256,
"vbits_to_cbits_buffer_size": 144,
"predictor_function": 1,
"num_of_components": 4,
"axi_lite_debug": False,
"support_axi_lite": False,
}
cons = constraints.Constraints()
# axi stream master
self.m_tvalid = Signal(1)
self.m_tlast = Signal(1)
self.m_tready = Signal(1)
self.m_tdata = Signal(32)
# axi steam slave
self.s_tvalid = Signal(1)
self.s_tlast = Signal(1)
self.s_tready = Signal(1)
self.s_tdata = Signal(64)
self.top = integration_3.Integration3(config, cons)
self.ios = \
[self.m_tvalid, self.m_tlast, self.m_tready, self.m_tdata] + \
[self.s_tvalid, self.s_tlast, self.s_tready, self.s_tdata]
def main(bdtfile,
scoretype='BDeu',
ess=1.0,
outfile=None,
constraint_file="",
cachefile=None):
bn, sc = bnsearch.empty_net(bdtfile,
scoretype,
ess,
cachefile=cachefile)
cstrs = constraints.Constraints(constraint_file)
kruskal(bn, sc, cstrs)
if outfile:
bn.save(outfile)
sc.score_new(bn)
print sc.score()
def __init__(self, maze, debug):
self.domain = []
self.finish = {}
self.start = {}
self.visited = []
self.complete_colors = []
self.debug = ''
if debug is 'True':
self.debug = True
elif debug is 'False':
self.debug = False
self.moves = 0
self.find_s_and_f(maze)
print('Solving:')
mazes.print_maze(maze)
self.c = constraints.Constraints(self.start, self.finish, self.debug)
def __init__(self):
self.config = config = {
"bit_depth": 12,
"pixels_per_cycle": 2,
"LJ92_fifo_depth": 512, #512 x 72 = RAM36
"out_bits": 16,
"converter": 30,
"converter_fifo_depth": 512, #512 x 36 = RAM18
"vbits_to_cbits_buffer_size": 77,
"support_axi_lite": False,
"axi_lite_debug": False,
"predictor_function": 1,
"num_of_components": 4,
}
cons = constraints.Constraints()
#pixels in
self.pixel_in1 = Signal(12)
self.pixel_in2 = Signal(12)
#data out
self.data_out = Signal(16)
#signals
self.valid_in = Signal(1)
self.valid_out = Signal(1)
self.end_out = Signal(1)
self.nready = Signal(1)
self.busy_in = Signal(1)
self.integration_3 = integration_3.Integration3(config, cons)
self.fix_0xff = fix_0xff.Fix0xFF()
self.fix_0xff2 = fix_0xff2.Fix0xFF2()
self.markers = markers.Markers()
self.auto_reset = auto_reset.AutoReset()
self.ios = \
[self.valid_in, self.valid_out, self.end_out] + \
[self.pixel_in1, self.pixel_in2, self.nready] + \
[self.data_out, self.busy_in]
input_handler.in_end.eq(self.in_end),
input_handler.valid_in.eq(self.valid_in),
]
# input_handler and output_handler
m.d.comb += [
input_handler.dec_buff.eq(output_handler.dec_buff_out),
output_handler.buffer.eq(input_handler.buffer),
output_handler.buff_consum.eq(input_handler.buff_consum),
output_handler.new_buff_consum.eq(input_handler.new_buff_consum),
output_handler.end_in.eq(input_handler.end_out),
]
# output_handler and this
m.d.comb += [
self.data_out.eq(output_handler.data_out),
self.valid_out.eq(output_handler.valid_out),
self.end_out.eq(output_handler.end_out),
output_handler.busy_in.eq(self.busy_in),
]
return m
if __name__ == "__main__":
config = {
"out_bits" : 32,
"converter": 48,
"vbits_to_cbits_buffer_size": 144,
}
d = VBitsToCBits(config, constraints.Constraints())
main(d, ports=d.ios)
# lj92 pipeline with fifo
m.d.comb += [
fifo.we.eq(self.valid_in),
fifo.din.eq(Cat(self.enc_in, self.enc_in_ctr, self.in_end)),
]
m.d.comb += [
self.valid_out.eq(fifo.readable),
self.enc_out.eq(fifo.dout[0:self.data_bits]),
self.enc_out_ctr.eq(fifo.dout[self.data_bits:self.total_width -
1]),
self.out_end.eq(fifo.dout[self.total_width - 1:self.total_width]),
fifo.re.eq(self.latch_output),
]
# fifo with close_full
m.d.sync += [
self.close_full.eq(fifo.level >= (self.depth - 10)),
]
return m
if __name__ == "__main__":
config = {
"bit_depth": 16,
"pixels_per_cycle": 2,
"LJ92_fifo_depth": 128,
}
d = LJ92PipelineFifo(config, constraints.Constraints())
main(d, ports=d.ios)
m.d.comb += [
self.data_out.eq(vbits_to_cbits.data_out),
self.valid_out.eq(vbits_to_cbits.valid_out),
self.end_out.eq(vbits_to_cbits.end_out),
]
# self.busy
m.d.comb += [
self.nready.eq(integration_2.nready),
]
return m
if __name__ == "__main__":
config = {
"bit_depth": 12,
"pixels_per_cycle": 4,
"LJ92_fifo_depth": 128,
"out_bits": 32,
"converter": 48,
"converter_fifo_depth": 256,
"vbits_to_cbits_buffer_size": 144,
"predictor_function": 1,
"num_of_components": 4,
"axi_lite_debug": False,
"support_axi_lite": False,
}
cons = constraints.Constraints()
d = Integration3(config, cons)
main(d, ports=d.ios)
# This loop will initiate number of SingleNormalizer-s for every pixel.
for pixel, val_in, val_out, ssss, val_in_mns in zip(
self.pixels, self.vals_in, self.vals_out, self.ssssx,
self.vals_in_mns):
m.d.comb += [
pixel.val_in.eq(val_in),
pixel.valid.eq(self.valid_in),
pixel.end_in.eq(self.end_in),
pixel.val_in_mns.eq(val_in_mns),
]
m.d.comb += [
ssss.eq(pixel.ssss),
val_out.eq(pixel.val_out),
]
#if valid data
m.d.comb += self.valid_out.eq(self.pixels[0].valid_o)
# end
m.d.comb += self.end_out.eq(self.pixels[0].end_out)
return m
if __name__ == "__main__":
config = {
"bit_depth": 16,
"pixels_per_cycle": 1,
}
n = Normalize(config, constraints.Constraints())
main(n, ports=n.ios)
# This loop will initiate number of SingleEncoder-s for every pixel.
for pixel, val_in, enc_out, enc_ctr, ssss, read_port in zip(
self.pixels, self.vals_in, self.encs_out, self.encs_ctr,
self.ssssx, self.read_ports):
m.d.comb += [
pixel.val_in.eq(val_in),
pixel.end_in.eq(self.end_in),
pixel.valid_in.eq(self.valid_in),
pixel.ssss.eq(ssss),
read_port.addr.eq(pixel.rp_addr),
pixel.rp_data.eq(read_port.data),
enc_out.eq(pixel.enc_out),
enc_ctr.eq(pixel.enc_ctr),
]
#if valid data
m.d.comb += self.valid_out.eq(self.pixels[0].valid_out)
m.d.comb += self.end_out.eq(self.pixels[0].end_out)
return m
if __name__ == "__main__":
config = {
"bit_depth": 16,
"pixels_per_cycle": 1,
"support_axi_lite": False,
}
e = Encode(config, constraints.Constraints())
main(e, ports=e.ios)
for predic_out, lbuff in zip(
self.predics_out, lbuffs[i])
]
with m.Else():
with m.Switch(buff_ctr):
for i in range(self.gb):
with m.Case(i):
m.d.sync += [
predic_out.eq(buff)
for predic_out, buff in zip(
self.predics_out, buffs[i])
]
#if valid data
m.d.sync += self.valid_out.eq(self.valid_in)
# end
m.d.sync += self.end_out.eq(self.end_in)
return m
if __name__ == "__main__":
config = {
"bit_depth": 16,
"pixels_per_cycle": 2,
"predictor_function": 1,
"num_of_components": 4,
}
p = PredictorP1C4Pix12(config, constraints.Constraints())
main(p, ports=p.ios)
assert 900 == (yield m.predics_out[3])
assert 1 == (yield m.valid_out)
yield
assert 700 == (yield m.pixels_out[0])
assert 3955 == (yield m.pixels_out[1])
assert 700 == (yield m.pixels_out[2])
assert 750 == (yield m.pixels_out[3])
assert 300 == (yield m.predics_out[0])
assert 3000 == (yield m.predics_out[1])
assert 300 == (yield m.predics_out[2])
assert 350 == (yield m.predics_out[3])
assert 1 == (yield m.valid_out)
print("predictor_test_1: succeeded.")
sim.add_clock(1e-8)
sim.add_sync_process(testbench())
sim.run()
if __name__ == "__main__":
config = {
"bit_depth" : 12,
"pixels_per_cycle": 4,
"predictor_function": 1,
"num_of_components": 4,
}
p = PredictorP1C4Px4(config, constraints.Constraints())
predictor_test_1(p)
main(p, ports=p.ios)
fifo.we.eq(self.valid_in),
fifo.din.eq(Cat(self.enc_in, self.enc_in_ctr, self.in_end)),
]
m.d.comb += [
self.writable.eq(fifo.writable),
self.valid_out.eq(fifo.readable),
self.enc_out.eq(fifo.dout[0:self.data_width]),
self.enc_out_ctr.eq(fifo.dout[self.data_width:self.total_bits -
1]),
self.out_end.eq(fifo.dout[self.total_bits - 1:self.total_bits]),
fifo.re.eq(self.latch_output),
]
# fifo with close_full
m.d.sync += [
self.close_full.eq(fifo.level >= (self.depth - self.steps)),
]
return m
if __name__ == "__main__":
config = {
"bit_depth": 16,
"pixels_per_cycle": 2,
"converter": 36,
"converter_fifo_depth": 128,
}
d = ConverterFifo(config, constraints.Constraints())
main(d, ports=d.ios)
m.d.sync += [
width_temp.eq(self.width),
height_temp.eq(height_temp - 1),
self.new_row.eq(1),
]
with m.Else():
m.d.sync += [
width_temp.eq(width_temp - self.ps),
self.new_row.eq(0),
]
with m.If((height_temp == 0)
& (width_temp == 2 * self.ps)):
m.d.sync += [
self.end_of_frame.eq(1),
]
m.next = "END"
with m.State("END"):
m.d.sync += [
self.end_of_frame.eq(1),
]
return m
if __name__ == "__main__":
config = {
"pixels_per_cycle": 2,
}
m = Signals(config, constraints.Constraints())
main(m, ports=m.ios)
from core_axi_lite import *
import constraints
def core_axi_lite_test_1(m):
vcdf = open(parentdir + "/../simulations/core_axi_lite_test_1.vcd", "w")
with pysim.Simulator(m, vcd_file=vcdf) as sim:
def testbench():
yield m.s_axi_ri.rready.eq(1)
yield m.s_axi_ri.arvalid.eq(1)
yield m.s_axi_ri.araddr.eq(260)
yield
yield m.s_axi_ri.arvalid.eq(0)
for i in range(10):
yield
print("core_axi_lite_test_1: succeeded.")
sim.add_clock(1e-8, domain="full")
sim.add_sync_process(testbench())
sim.run()
if __name__ == "__main__":
config = {
"bit_depth" : 12,
"axi_lite_debug": False,
}
n = CoreAxiLite(config, constraints.Constraints())
core_axi_lite_test_1(n)
main(n, ports=n.ios)
# move to the next one.
state = "STEPS"
start = 0
end = self.conv_bits
for i in range(steps):
with m.State("STEPS_" + str(i)):
m.d.sync += [
self.enc_in.eq(enc_out_latch[start:end]),
self.enc_in_ctr.eq(self.conv_bits),
self.valid_in.eq(1),
]
if i == 0:
m.d.sync += self.in_end.eq(out_end_latch),
try_burst_idle()
else:
m.d.sync += self.in_end.eq(0),
m.next = "STEPS_" + str(i - 1)
start += self.conv_bits
end += self.conv_bits
return m
if __name__ == "__main__":
config = {
"bit_depth": 16,
"pixels_per_cycle": 2,
"converter": 36,
}
d = Converter(config, constraints.Constraints())
main(d, ports=d.ios)
assert 1 == (yield m.valid_out)
assert 0b110000000100 == (yield m.enc_out)
assert 12 == (yield m.enc_out_ctr)
yield
#validate test 3
assert 1 == (yield m.valid_out)
assert 0b1011001101101111000101010101011000011111010110101011111111010010101010101010101010110101010100000111100010010110101010101010 == (
yield m.enc_out)
assert 124 == (yield m.enc_out_ctr)
yield
assert 0 == (yield m.valid_out)
print("merge_test_1: succeeded.")
sim.add_clock(1e-8)
sim.add_sync_process(testbench())
sim.run()
if __name__ == "__main__":
config = {
"bit_depth": 16,
"pixels_per_cycle": 4,
}
m = Merge(config, constraints.Constraints())
merge_test_1(m)
main(m, ports=m.ios)
yield
#test input 2
assert 100 == (yield m.vals_out[0])
assert 1000 == (yield m.vals_out[1])
assert 200 == (yield m.vals_out[2])
assert 0x1FF9C == (yield m.vals_out[3])
assert 1 == (yield m.valid_out)
yield m.valid_in.eq(0)
yield
assert 0 == (yield m.valid_out)
print("diff_test_1: succeeded.")
sim.add_clock(1e-8)
sim.add_sync_process(testbench())
sim.run()
if __name__ == "__main__":
config = {
"bit_depth": 16,
"pixels_per_cycle": 4,
}
d = Difference(config, constraints.Constraints())
diff_test_1(d)
main(d, ports=d.ios)
self.fend = Signal(1)
self.ios = \
[self.valid_in, self.allowed_cycles, self.fend]
def elaborate(self, platform):
m = Module()
counter = Signal(25)
with m.FSM() as fsm:
with m.State("IDLE"):
with m.If(self.valid_in):
m.next = "COUNTING"
with m.State("COUNTING"):
m.d.sync += counter.eq(counter + 1)
with m.If(counter == self.allowed_cycles):
m.next = "END"
with m.State("END"):
m.d.sync += self.fend.eq(1)
return m
if __name__ == "__main__":
m = ForceEnd({}, constraints.Constraints())
main(m, ports=m.ios)
