def run( file ) : ssd = ram.Ram( ) cmd = cpu.Cpu( 0, ssd, verbose ) ssd.loader( file ) #testRam( ssd ) #testCpu( ssd ) cmd.run( )
def test_init_tlb_shared(self):
yaml_config = read_config(FILE_NAME2)
cpui = mCpu.Cpu(yaml_config)
self.assertEqual(yaml_config['cpu']['tlb']['data'][0]['entry'], 16)
self.assertEqual(yaml_config['cpu']['tlb']['data'][0]['entry'],
cpui.dtlb[0].get_set_index() * 4)
self.assertEqual(cpui.dtlb[0].get_set_num(), 4)
self.assertIsNot(cpui.dtlb[0], cpui.itlb[0])
self.assertEqual(yaml_config['cpu']['tlb']['data'][1]['entry'], 16)
self.assertEqual(yaml_config['cpu']['tlb']['data'][1]['entry'],
cpui.dtlb[1].get_set_index() * 4)
self.assertEqual(cpui.dtlb[1].get_set_num(), 4)
self.assertIs(cpui.dtlb[1], cpui.itlb[1])
self.assertEqual(yaml_config['cpu']['tlb']['instruction'][0]['entry'],
16)
self.assertEqual(yaml_config['cpu']['tlb']['instruction'][0]['entry'],
cpui.itlb[0].get_set_index() * 4)
self.assertEqual(cpui.itlb[0].get_set_num(), 4)
self.assertIsNot(cpui.itlb[0], cpui.dtlb[0])
self.assertEqual(yaml_config['cpu']['tlb']['instruction'][1]['entry'],
16)
self.assertEqual(yaml_config['cpu']['tlb']['instruction'][1]['entry'],
cpui.itlb[1].get_set_index() * 4)
self.assertEqual(cpui.itlb[1].get_set_num(), 4)
self.assertIs(cpui.itlb[1], cpui.dtlb[1])
def testCpu( mem ) : cmd = cpu.Cpu( 0, mem ) cmd.run( ) # I wonder how I would test fetch and execute besides running? # I have indirectly tested them but getting the cpu's inernal state # isn't something I want to complicate with. Oh well it works anyway. core = open( "core.txt", 'w' ) mem.coreDump( core ) core.close( )
def __init__(self, endpoints, cert, ca_cert, interval, items, handlers,
defaults):
from urlparse import urlparse
from jinja2 import Environment
env = Environment()
self.items = {
n: (Template(n,
env.from_string(n)), Template(v, env.from_string(v)))
for (n, v) in items
}
self.handlers = {
n: (Template(n,
env.from_string(n)), Template(v, env.from_string(v)))
for (n, v) in handlers
}
self.interval = interval
parsed_endpoints = map(urlparse, endpoints.split(','))
if len(parsed_endpoints) <= 0:
raise ValueError("Endpoint parameter is empty or missing")
scheme = parsed_endpoints[0].scheme
if scheme == "stdout":
self.client = StdoutClient()
else:
self.client = EtcdClient(
tuple(
map(
lambda e: (e.hostname, e.port if e.port else 80
if e.scheme == "http" else 443),
parsed_endpoints)), scheme, cert, ca_cert)
self.defaults = TemplateDict(
{n: Template(v, env.from_string(v))
for (n, v) in defaults})
self.context = Context()
import cpu
import memory
import disk
import host
import systemd
import os_support
self.context.add_module(cpu.Cpu())
self.context.add_module(memory.Memory())
self.context.add_module(disk.Disk())
self.context.add_module(host.Host())
self.context.add_module(systemd.Systemd())
self.context.add_module(os_support.OS())
for n in self.handlers:
self.client.add_handler(self.context, self.defaults, n,
*(self.handlers[n]))
def deitel_version( ) :
print ' *** Welcome to Simpletron! ***\n\
*** Please enter your program one instruction ***\n\
*** (or data word) at a time into the input ***\n\
*** text field. I will display the location ***\n\
*** number and a question mark (?). You then ***\n\
*** type the word for that location. Enter the ***\n\
*** hash twice to stop entering your program. ***'
ssd = ram.Ram( )
addr = 0
while True :
unknown = raw_input( str( addr ) + "_?_" )
if exit( unknown ) :
print "Stopping input. Running Simpletron ..."
break
elif invalid( unknown ) :
print "\tinvalid, use {-9999 - 9999}"
continue
val = int( unknown )
ssd.setAt( addr, val )
addr += 1
cmd = cpu.Cpu( 0, ssd, not verbose )
cmd.run( )
def test_tlb_private(self):
yaml_config = read_config(FILE_NAME3)
cpui = mCpu.Cpu(yaml_config)
# test miss L1/L2
self.assertEqual(cpui.dtlb_lookup(False, 0x408ed4, 0), False)
self.assertEqual(cpui.dtlb[0].content[0][0].tag, int(0x408ed4 / 2))
self.assertEqual(cpui.dtlb[0].content[0][0].dirty, False)
self.assertEqual(cpui.dtlb[1].content[0][0].tag, int(0x408ed4 / 2))
self.assertEqual(cpui.dtlb[1].content[0][0].dirty, False)
self.assertEqual(cpui.get_dtlb_istats(0).get_hit_count(), 0)
self.assertEqual(cpui.get_dtlb_istats(0).get_miss_count(), 1)
self.assertEqual(cpui.get_dtlb_istats(1).get_hit_count(), 0)
self.assertEqual(cpui.get_dtlb_istats(1).get_miss_count(), 1)
# test hit L1 dtlb
self.assertEqual(cpui.dtlb_lookup(True, 0x408ed4, 0), True)
self.assertEqual(cpui.dtlb[0].content[0][0].dirty, True)
self.assertEqual(cpui.dtlb[1].content[0][0].dirty, False)
self.assertEqual(cpui.get_dtlb_istats(0).get_hit_count(), 1)
self.assertEqual(cpui.get_dtlb_istats(0).get_miss_count(), 1)
self.assertEqual(cpui.get_dtlb_istats(1).get_hit_count(), 0)
self.assertEqual(cpui.get_dtlb_istats(1).get_miss_count(), 1)
# test miss L1/L2 dtlb
self.assertEqual(cpui.dtlb_lookup(False, 0x408ed8, 0), False)
self.assertEqual(cpui.dtlb[0].content[0][1].tag, int(0x408ed8 / 2))
self.assertEqual(cpui.dtlb[0].content[0][1].dirty, False)
self.assertEqual(cpui.dtlb[1].content[0][1].tag, int(0x408ed8 / 2))
self.assertEqual(cpui.dtlb[1].content[0][1].dirty, False)
self.assertEqual(cpui.get_dtlb_istats(0).get_hit_count(), 1)
self.assertEqual(cpui.get_dtlb_istats(0).get_miss_count(), 2)
self.assertEqual(cpui.get_dtlb_istats(1).get_hit_count(), 0)
self.assertEqual(cpui.get_dtlb_istats(1).get_miss_count(), 2)
# ITLB
# test miss L1/L2 itlb 0x10019d90
self.assertEqual(cpui.itlb_lookup(0x10019d90, 0), False)
self.assertEqual(cpui.itlb[0].content[0][0].tag, int(0x10019d90 / 2))
self.assertEqual(cpui.itlb[0].content[0][0].dirty, False)
self.assertEqual(cpui.itlb[1].content[0][0].tag, int(0x10019d90 / 2))
self.assertEqual(cpui.itlb[1].content[0][0].dirty, False)
self.assertEqual(cpui.get_itlb_istats(0).get_hit_count(), 0)
self.assertEqual(cpui.get_itlb_istats(0).get_miss_count(), 1)
self.assertEqual(cpui.get_itlb_istats(1).get_hit_count(), 0)
self.assertEqual(cpui.get_itlb_istats(1).get_miss_count(), 1)
# test miss L1/L2 itlb
self.assertEqual(cpui.itlb_lookup(0x10019d94, 0), False)
self.assertEqual(cpui.itlb[0].content[0][1].tag, int(0x10019d94 / 2))
self.assertEqual(cpui.itlb[0].content[0][1].dirty, False)
self.assertEqual(cpui.itlb[1].content[0][1].tag, int(0x10019d94 / 2))
self.assertEqual(cpui.itlb[1].content[0][1].dirty, False)
self.assertEqual(cpui.get_itlb_istats(0).get_hit_count(), 0)
self.assertEqual(cpui.get_itlb_istats(0).get_miss_count(), 2)
self.assertEqual(cpui.get_itlb_istats(1).get_hit_count(), 0)
self.assertEqual(cpui.get_itlb_istats(1).get_miss_count(), 2)
# test hit L1 itlb
self.assertEqual(cpui.itlb_lookup(0x10019d90, 0), True)
self.assertEqual(cpui.itlb[0].content[0][0].dirty, False)
self.assertEqual(cpui.itlb[1].content[0][0].dirty, False)
self.assertEqual(cpui.get_itlb_istats(0).get_hit_count(), 1)
self.assertEqual(cpui.get_itlb_istats(0).get_miss_count(), 2)
self.assertEqual(cpui.get_itlb_istats(1).get_hit_count(), 0)
self.assertEqual(cpui.get_itlb_istats(1).get_miss_count(), 2)
def __init__(
self, tam
): #Construtor da classe SO, parametro de entrada é um objeto da classe Ram
self.ram = ram.Ram()
self.cpu = cpu.Cpu(self.ram, tam, self.ram.palavras)
def setUp(self):
""" Setup performed before each test """
self.cpu = cpu.Cpu()
import gdb
import ktrace
import kdump
import klog
import cpu
import thread
import sync
def addPrettyPrinters():
pp = gdb.printing.RegexpCollectionPrettyPrinter('mimiker')
pp.add_printer('mtx', 'mtx', sync.Mutex)
pp.add_printer('condvar', 'condvar', sync.CondVar)
pp.add_printer('thread', 'thread', thread.Thread)
pp.add_printer('timeval', 'timeval', klog.TimeVal)
gdb.printing.register_pretty_printer(gdb.current_objfile(), pp)
addPrettyPrinters()
ktrace.Ktrace()
thread.Kthread()
cpu.Cpu()
kdump.Kdump()
klog.Klog()
file_name = '_'.join([get_filename(INPUT_FILE), "tag-distribution.jpg"])
file_dir = os.path.join(save_dir, file_name)
plt.savefig(file_dir)
plt.show()
def read_config(file_name):
file_path = get_absolute_path(CONFIG_FILE)
file_config = open(file_path, 'r')
yaml_config = yaml.load(file_config)
file_config.close()
return yaml_config
if __name__ == "__main__":
print("----------------------------------------------------\n\n")
yconfig = read_config(CONFIG_FILE)
cpu1 = cpu.Cpu(yconfig)
tag_data = list()
tag_instruction = list()
with open(get_absolute_path(INPUT_FILE), 'rt') as input_file:
line_num = 0
for line in input_file:
mem_request = MemRequest(line)
tag = constants.get_tag(mem_request.get_virtual_address())
print(str(line_num) + " " + str(mem_request) + " tag: " + hex(tag))
res = False
if mem_request.get_operation() == Operation.DATA_READ or \
mem_request.get_operation() == Operation.DATA_WRITE:
tag_data.append(tag)
if mem_request.get_operation() == Operation.DATA_READ:
res = cpu1.dtlb_lookup(False, tag, line_num)
def __init__(self):
"""Creates and initializes the system components."""
self._cpu = cpu.Cpu()
self._memory_controller = memory.MemoryController()
self._video_controller = video.VideoController()
