def can_be_applied(self, graph, expr_index, sdfg, permissive=False):
# Avoid import loops
from dace.transformation.interstate import FPGATransformState
# Condition match depends on matching FPGATransformState for each state
for state_id, state in enumerate(sdfg.nodes()):
fps = FPGATransformState(sdfg, graph.sdfg_id, -1,
{FPGATransformState.state: state_id}, 0)
if not fps.can_be_applied(sdfg, expr_index, sdfg):
return False
return True
def apply(self, sdfg):
# Avoid import loops
from dace.transformation.interstate import NestSDFG
from dace.transformation.interstate import FPGATransformState
sdfg_id = sdfg.sdfg_list.index(sdfg)
nesting = NestSDFG(sdfg_id, -1, {}, self.expr_index)
nesting.promote_global_trans = True
nesting.apply(sdfg)
fpga_transform = FPGATransformState(
sdfg_id, -1, {FPGATransformState._state: 0}, self.expr_index)
fpga_transform.apply(sdfg)
def apply(self, _, sdfg):
# Avoid import loops
from dace.transformation.interstate import NestSDFG
from dace.transformation.interstate import FPGATransformState
sdfg_id = sdfg.sdfg_id
nesting = NestSDFG(sdfg, sdfg_id, -1, {}, self.expr_index)
nesting.promote_global_trans = self.promote_global_trans
nesting.apply(sdfg, sdfg)
# The state ID is zero since we applied NestSDFG and have only one state in the new SDFG
fpga_transform = FPGATransformState(sdfg, sdfg_id, -1,
{FPGATransformState.state: 0},
self.expr_index)
fpga_transform.apply(sdfg, sdfg)
def can_be_applied(graph, candidate, expr_index, sdfg, strict=False):
# Avoid import loops
from dace.transformation.interstate import FPGATransformState
# Condition match depends on matching FPGATransformState for each state
for state_id, state in enumerate(sdfg.nodes()):
candidate = {FPGATransformState._state: state_id}
if not FPGATransformState.can_be_applied(sdfg, candidate,
expr_index, sdfg):
return False
return True