def get_spice_lib(self):
''' return spice lib definition '''
try:
return interpolate_env(self.cfg_model[self._tenv.splib],
self._logger)
except:
return None
def __init__(self,
test_name,
unit_test_cfg,
port_xref='',
logger_id='logger_id'):
self._logger = DaVELogger.get_logger(
'%s.%s.%s' % (logger_id, __name__, self.__class__.__name__))
self._tenvs = EnvTestcfgSection()
self._tenvtp = EnvTestcfgPort()
self._tenvr = EnvTestcfgOption()
self._tenvts = EnvTestcfgSimTime()
self._tenvtb = EnvTestcfgTestbench()
self._tenvp = EnvPortName()
self._tenvsim = EnvSimcfg()
self._portref_filename = interpolate_env(port_xref)
self._logger.info(mcode.INFO_055 % test_name)
_tmpcfg = dict([(test_name,
dict([(self._tenvs.test_name, test_name)] +
dict(unit_test_cfg).items()))])
cfg = ConfigObj(_tmpcfg)
schema_testcfg = SchemaTestConfig(cfg)
schema_testcfg.raise_vdterror()
self._test_cfg = schema_testcfg.get_cfg()[test_name]
self._test_cfg.update(self._compile_test(unit_test_cfg))
def get_circuits(self):
''' return dictionary {circuit name:filename} for circuit netlist '''
try:
return dict([
(k, interpolate_env(v, self._logger))
for k, v in self.cfg_model[self._tenv.circuit].items()
])
except:
return None
def _compile_postprocessor(self, testbench, port):
''' return a list of post process script files
'''
pp = testbench[self._tenvs.post_processor]
pp_script = pp[self._tenvtb.pp_script]
pp_cmd = pp[self._tenvtb.pp_command]
if pp_script != [''] and pp_cmd != '':
#pp_scr = [get_abspath(v, False) for v in pp_script]
pp_scr = [interpolate_env(v, self._logger) for v in pp_script]
else:
pp_scr = [None]
return filter(None, pp_scr), pp_cmd
def get_ams_control_filename(self):
try:
return interpolate_env(self.cfg_model[self._tenv.ams_control_file],
self._logger)
except:
return None
def get_hdl_include_files(self):
''' return a list of files being included using `include directive '''
return [
interpolate_env(s, self._logger)
for s in self.cfg_model[self._tenv.hdl_include_files]
]
def get_hdl_files(self):
''' return a list of Verilog files '''
return [
interpolate_env(s, self._logger)
for s in self.cfg_model[self._tenv.hdl_files]
]
def get_ncams_connrules(self):
''' return ams connrules '''
return interpolate_env(self.cfg_model[self._tenv.ams_connrules],
self._logger)
def get_simulator_option(self):
''' return HDL simulator option '''
return interpolate_env(self.cfg_model[self._tenv.simulator_option],
self._logger)