def __init__(self, name):
design.__init__(self, "top")
# Instantiate a GDS cell with the design
gds_file = "{0}/{1}.gds".format(
os.path.dirname(os.path.realpath(__file__)), name)
cell = gds_cell(name, gds_file)
self.add_inst(name=name, mod=cell, offset=[0, 0])
self.connect_inst([])
layer_stack = ("metal1", "via1", "metal2")
r = router(layer_stack, self, gds_file)
connections = [('out_0_2', 'a_0_0'), ('out_0_3', 'b_0_0'),
('out_0_0', 'a_0_1'), ('out_1_2', 'a_1_0'),
('out_1_3', 'b_1_0'), ('out_1_0', 'a_1_1'),
('out_2_1', 'a_2_0'), ('out_2_2', 'b_2_0'),
('out_3_1', 'a_3_0'), ('out_3_2', 'b_3_0'),
('out_4_6', 'a_4_0'), ('out_4_7', 'b_4_0'),
('out_4_8', 'a_4_2'), ('out_4_9', 'b_4_2'),
('out_4_10', 'a_4_4'), ('out_4_11', 'b_4_4'),
('out_4_0', 'a_4_1'), ('out_4_2', 'b_4_1'),
('out_4_4', 'a_4_5'), ('out_4_1', 'a_4_3'),
('out_4_5', 'b_4_3')]
for (src, tgt) in connections:
self.assertTrue(r.route(src=src, dest=tgt))
def __init__(self, name):
design.__init__(self, "top")
# Instantiate a GDS cell with the design
gds_file = "{0}/{1}.gds".format(
os.path.dirname(os.path.realpath(__file__)), name)
cell = gds_cell(name, gds_file)
self.add_inst(name=name, mod=cell, offset=[0, 0])
self.connect_inst([])
r = router(gds_file)
layer_stack = ("metal1", "via1", "metal2")
# This should be infeasible because it is blocked without a detour.
self.assertFalse(
r.route(self,
layer_stack,
src="A",
dest="B",
detour_scale=1))
# This should be feasible because we allow it to detour
self.assertTrue(
r.route(self,
layer_stack,
src="A",
dest="B",
detour_scale=3))
def __init__(self, name, gds_file):
self.name = name
self.gds_file = gds_file
self.sp_file = None
design.__init__(self, name)
# The dimensions will not be defined, so do this...
self.width=0
self.height=0
def __init__(self, name, sram_config):
design.__init__(self, name)
self.sram_config = sram_config
sram_config.set_local_config(self)
self.total_write = OPTS.num_rw_ports + OPTS.num_w_ports
self.total_read = OPTS.num_rw_ports + OPTS.num_r_ports
self.total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
self.bank_insts = []
def __init__(self, obj, layer_stack, path):
name = "route_{0}".format(route.unique_route_id)
route.unique_route_id += 1
design.__init__(self, name)
debug.info(3, "create route obj {0}".format(name))
self.obj = obj
self.layer_stack = layer_stack
self.path = path
self.setup_layers()
self.create_wires()
def __init__(self, name, sram_config):
design.__init__(self, name)
lef.__init__(self, ["metal1", "metal2", "metal3"])
verilog.__init__(self)
self.sram_config = sram_config
sram_config.set_local_config(self)
self.bank_insts = []
#For logical effort delay calculations.
self.all_mods_except_control_done = False
def __init__(self, name):
design.__init__(self, "top")
# Instantiate a GDS cell with the design
gds_file = "{0}/{1}.gds".format(
os.path.dirname(os.path.realpath(__file__)), name)
cell = gds_cell(name, gds_file)
self.add_inst(name=name, mod=cell, offset=[0, 0])
self.connect_inst([])
layer_stack = ("metal1", "via1", "metal2")
r = router(layer_stack, self, gds_file)
self.assertTrue(r.route(src="A", dest="B"))
def __init__(self, name):
design.__init__(self, "top")
# Instantiate a GDS cell with the design
gds_file = "{0}/{1}.gds".format(
os.path.dirname(os.path.realpath(__file__)), name)
cell = gds_cell(name, gds_file)
self.add_inst(name=name, mod=cell, offset=[0, 0])
self.connect_inst([])
layer_stack = ("metal1", "via1", "metal2")
r = router(layer_stack, self, gds_file)
# these are user coordinates and layers
src_pin = [[0.52, 4.099], 11]
tgt_pin = [[3.533, 1.087], 11]
#r.route(layer_stack,src="A",dest="B")
self.assertTrue(r.route(src=src_pin, dest=tgt_pin))
def __init__(self, name, sram_config):
design.__init__(self, name)
lef.__init__(self, ["m1", "m2", "m3", "m4"])
verilog.__init__(self)
self.sram_config = sram_config
sram_config.set_local_config(self)
self.bank_insts = []
if self.write_size:
self.num_wmasks = int(ceil(self.word_size / self.write_size))
else:
self.num_wmasks = 0
if not self.num_spare_cols:
self.num_spare_cols = 0
def __init__(self, name, sram_config):
design.__init__(self, name)
lef.__init__(self, ["m1", "m2", "m3", "m4"])
verilog.__init__(self)
self.sram_config = sram_config
sram_config.set_local_config(self)
self.bank_insts = []
if self.write_size:
self.num_wmasks = int(self.word_size / self.write_size)
else:
self.num_wmasks = 0
#For logical effort delay calculations.
self.all_mods_except_control_done = False
def __init__(self, name):
design.__init__(self, "top")
# Instantiate a GDS cell with the design
globals.setup_paths()
from control_logic import control_logic
cell = control_logic(16)
#from pinv import pinv
#cell = pinv()
#gds_file = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),"control_logic")
#cell = gds_cell(name, gds_file)
self.add_inst(name=name,
mod=cell,
offset=[0,0])
self.connect_inst(cell.pin_map.keys())
r=router(module=cell)
layer_stack =("metal3","via2","metal2")
self.assertTrue(r.route(self,layer_stack))
