def dp_system(mux_dp_bus, reset, clock):

    bg0_dp_bus = DPBus(data_w=2)
    bg1_dp_bus = DPBus(data_w=2)

    bg0_dp_bus.ready = True
    bg1_dp_bus.ready = True

    bg0 = dp_block_gen(bg0_dp_bus, clock, reset, g_count_max=4)
    bg1 = dp_block_gen(bg1_dp_bus, clock, reset, g_count_max=4)
    my_mux = dp_mux(mux_dp_bus, bg0_dp_bus, bg1_dp_bus)

    return bg0, bg1, my_mux
def tb_dp_block_gen():
    dp_block_gen_dp_bus = DPBus(data_w=2)

    clock  = Signal(intbv(0))

    reset = ResetSignal(0, active=ACTIVE_LOW, async=True)

    bg = dp_block_gen(dp_block_gen_dp_bus, clock, reset, g_count_max=4)

    HALF_PERIOD = delay(10)

    @always(HALF_PERIOD)
    def clockGen():
        clock.next = not clock

    @instance
    def stimulus():
        reset.next = ACTIVE_LOW
        yield clock.negedge
        reset.next = INACTIVE_HIGH
        for i in range(12):
            dp_block_gen_dp_bus.ready.next = bool(min(1, randrange(3)))
            yield clock.negedge
        raise StopSimulation

    @instance
    def monitor():
        print "ready  data  valid    sop     eop"
        yield reset.posedge
        while 1:
            yield clock.posedge
            yield delay(1)
            print "   %s     %s    %s     %s     %s" % (dp_block_gen_dp_bus.ready, dp_block_gen_dp_bus.data, dp_block_gen_dp_bus.valid, dp_block_gen_dp_bus.sop, dp_block_gen_dp_bus.eop)

    return clockGen, stimulus, bg, monitor
def dp_system(mux_src_out, reset, clock):

    mux_sel = Signal(bool(0))

    bg0_src_in = DP_SISO()
    bg1_src_in = DP_SISO()

    bg0_src_in.ready = 1
    bg1_src_in.ready = 1

    bg0_src_out = DP_SOSI(data_w=2)
    bg1_src_out = DP_SOSI(data_w=2)

    bg0 = dp_block_gen(bg0_src_out, bg0_src_in, clock, reset, g_count_max=4)
    bg1 = dp_block_gen(bg1_src_out, bg1_src_in, clock, reset, g_count_max=4)
    my_mux = dp_mux(mux_src_out, bg0_src_out, bg1_src_out, mux_sel)

    return bg0, bg1, my_mux