def help_main(Env):
Mod = Env.Current
Env.donesx = 0
if not '-file' in sys.argv:
print('i need -file <COMMAND_FILE')
return
X = sys.argv.index('-file')
Cmdfilename = sys.argv[X + 1]
File = open(Cmdfilename)
Cmdlines = File.readlines()
File.close()
executeLines(Mod, Cmdlines, Env)
execute_line('dump_verilog %s.modv' % Env.Current.Module, Env)
logs.log_info('Done %d modification commands, failed %d ' %
(Env.donesx, logs.Errors))
def do_something(params):
lines = []
print(Env.Current)
if '-dofile' in params:
for Scenario in params['-dofile']:
Fin = open(Scenario, 'r')
lines += Fin.readlines()
Fin.close()
if ('-do' in params):
for line in params['-do']:
lines += [line]
if ('-top' in params):
for line in params['-top']:
lines += ['top %s' % (line)]
if ('-import' in params):
for line in params['-import']:
lines += ['import %s' % (line)]
if ('-help_main' in params):
lines += ['help_main']
if (len(lines) > 0):
# print('LINES',lines,params)
for line in lines:
logs.log_info('do line: %s' % line)
execute_line(line, Env)
else:
print(Env.Current)
if ('-o' in params):
Foutname = params['-o'][0]
else:
Foutname = 'dumpver.v'
if dbx:
logs.log_err(
'no "-do scenario_filename" given,so i proceed to dump verilog'
)
dbx.dump_all_verilog(Foutname)
logs.log_ending('exiting')
def excecuteLine(Mod, wrds, Env):
wrds = scanFunctions(wrds, Env, Mod)
if (wrds[0] == 'source'):
Fname = wrds[1]
os.system(Fname)
return
if (wrds[0] == 'new'):
newModule = wrds[1]
Env.Current = module_class.module_class(newModule)
Env.Modules[newModule] = Env.Current
return
if (wrds[0] == 'load'):
Fname = wrds[1]
Env.read_verilog_file(Fname, Env.rundir, Env)
return
if (wrds[0] == 'assign'):
Mod.add_hard_assign(wrds[1], wrds[2])
if (wrds[0] == 'add_inout'):
add_wires(Mod, 'inout', wrds[1:])
return
if (wrds[0] == 'add_input'):
add_wires(Mod, 'input', wrds[1:])
return
if (wrds[0] == 'add_output'):
add_wires(Mod, 'output', wrds[1:])
return
if (wrds[0] == 'copy_params'):
From = wrds[1]
Other = Env.Modules[From]
for Param in Other.parameters:
Mod.parameters[Param] = Other.parameters[Param]
for Param in Other.localparams:
Mod.localparams[Param] = Other.localparams[Param]
return
if (wrds[0] == 'copy_inst'):
From = wrds[1]
TypeInst = wrds[2]
if From not in Env.Modules:
Env.try_and_load_module(From, Env)
if From not in Env.Modules:
logs.log_error('failed to load "%s" module' % (From))
return
Other = Env.Modules[From]
for Inst in Other.insts:
found = False
if (Inst == TypeInst):
Type = Other.insts[Inst].Type
Mod.add_inst(Other.insts[Inst].Type, Inst)
found = True
elif (Other.insts[Inst].Type == TypeInst):
Mod.add_inst(TypeInst, Inst)
found = True
if found:
Oobj = Other.insts[Inst]
for Pin in Oobj.conns:
Sig = Oobj.conns[Pin]
if (type(Sig) is str) and (Sig in Other.nets):
_, WW = Other.nets[Sig]
if (type(WW) is tuple) and (len(WW) == 2):
Sig = '%s%s' % (Sig, module_class.pr_wid(WW))
Sup = module_class.support_set(WW[0])
for Param in Sup:
if Param in Other.parameters:
Mod.parameters[Param] = Other.parameters[
Param]
elif Param in Other.localparams:
Mod.localparams[Param] = Other.localparams[
Param]
Mod.add_conn(Inst, Pin, module_class.pr_expr(Sig))
for Param in Oobj.params:
Mod.insts[Inst].params[Param] = Oobj.params[Param]
return
if (wrds[0] == 'unconn'):
Inst = wrds[1]
if Inst not in Mod.insts:
logs.log_error('instance %s is not in module' % Inst)
return
Obj = Mod.insts[Inst]
for Pin in wrds[2:]:
if Pin in Obj.conns:
Obj.conns[Pin] = False
Env.donesx += 1
else:
Obj.conns[Pin] = False
return
if (wrds[0] == 'del_conn'):
Inst = wrds[1]
if Inst not in Mod.insts:
logs.log_error('instance %s is not in module' % Inst)
return
Obj = Mod.insts[Inst]
for Pin in wrds[2:]:
if Pin in Obj.conns:
Obj.conns.pop(Pin)
else:
logs.log_error('del_conn isnt=%s pin=%s failed' % (Inst, Pin))
return
if (wrds[0] == 'add_conn'):
Inst = wrds[1]
if Inst not in Mod.insts:
logs.log_error('instance %s is not in module' % Inst)
return
add_conns(Mod, Inst, wrds[2:], Env)
return
if (wrds[0] == 'del_inst'):
for Inst in wrds[1:]:
if Inst in Mod.insts:
Mod.insts.pop(Inst)
Env.donesx += 1
else:
logs.log_error('del instance %s is not in module' % Inst)
return
if (wrds[0] == 'del_wire'):
for Net in wrds[1:]:
if Net in Mod.nets:
Mod.nets.pop(Net)
Env.donesx += 1
else:
logs.log_error('net %s is not in module' % Net)
return
if (wrds[0] == 'add_inst'):
Type = wrds[1]
Inst = wrds[2]
Mod.add_inst(Type, Inst)
add_conns(Mod, Inst, wrds[3:], Env)
return
if (wrds[0] == 'add_param'):
Inst = wrds[1]
for PrmVal in wrds[2:]:
Prm, Val = PrmVal.split('=')
Mod.add_inst_param(Inst, Prm, Val)
return
if (wrds[0] == 'add_wire'):
Dir = wrds[1]
Wid = eval(wrds[2])
for Net in wrds[3:]:
Mod.add_sig(Net, Dir, Wid)
return
if (wrds[0] == 'rename_inst'):
Old = wrds[1]
New = wrds[2]
if Old not in Mod.insts:
logs.log_error('inst %s is not in module' % (Old))
return
Obj = Mod.insts.pop(Old)
Obj.Name = New
Mod.insts[New] = Obj
return
if (wrds[0] == 'retype_inst'):
Old = wrds[1]
Type = wrds[2]
if len(wrds) >= 4:
New = wrds[3]
else:
New = Old
if Old not in Mod.insts:
logs.log_error('inst %s / %s is not in module' % (Type, Old))
return
Obj = Mod.insts[Old]
Obj.Type = Type
Obj.Name = New
if Old != New:
Mod.insts.pop(Old)
Mod.insts[New] = Obj
Env.donesx += 1
return
if (wrds[0] == 'report_connectivity'):
report_connectivity(Mod, Env)
pairsTable(Mod)
singlesTable(Mod)
return
if (wrds[0] == 'remove_unused_wires'):
removeUnused(Mod)
return
if (wrds[0] == 'elaborateSimpleAssigns'):
elaborateSimpleAssigns(Mod)
return
if (wrds[0] == 'assign'):
treatAssigns(Env, Mod, wrds[1], wrds[2])
return
if (wrds[0] == 'save'):
Fname = wrds[1]
execute_line('dump_verilog %s' % Fname, Env)
return
if wrds[0].startswith('remove_gen'):
Mod.generates = []
return
if wrds[0] == 'new_hierarchy':
Mod.prepareNetTable()
Mod.mergeNetTableBusses()
Name = wrds[1]
New = module_class.module_class(Name)
Env.Modules[Name] = New
Insts = wrds[2:]
for Inst in wrds[2:]:
if Inst in Mod.insts:
Obj = Mod.insts[Inst]
New.insts[Inst] = Obj
Mod.insts.pop(Inst)
Nets = list(Mod.nets.keys())
Mod.insts[Name] = module_class.instance_class(Name, Name)
for Net in Nets:
if Net in Mod.netTable:
List = Mod.netTable[Net]
In, Out = False, False
for (Pin, Inst, Type) in List:
if Inst in Insts: In = True
if Inst in Mod.insts: Out = True
if In and not Out:
New.nets[Net] = Mod.nets[Net]
Mod.nets.pop(Net)
elif In and Out:
Dir, Wid = Mod.nets[Net]
New.nets[Net] = 'inout', Wid
Mod.insts[Name].conns[Net] = Net
Fout = open('%s.v' % Name, 'w')
New.dump_verilog(Fout)
Fout.close()
logs.log_error('bad command line %s' % ' '.join(wrds))