def get_build_env(kind, target_clk_ns):
"""Get board-related build environment for testing.
- kind = either zynq or alveo.
"""
ret = {}
if kind == "zynq":
ret["board"] = os.getenv("PYNQ_BOARD", default="Pynq-Z1")
ret["part"] = pynq_part_map[ret["board"]]
ret["ip"] = os.getenv("PYNQ_IP", "")
ret["username"] = os.getenv("PYNQ_USERNAME", "xilinx")
ret["password"] = os.getenv("PYNQ_PASSWORD", "xilinx")
ret["port"] = os.getenv("PYNQ_PORT", 22)
ret["target_dir"] = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn")
ret["build_fxn"] = ZynqBuild(ret["board"], target_clk_ns)
elif kind == "alveo":
ret["board"] = os.getenv("ALVEO_BOARD", default="U250")
ret["part"] = alveo_part_map[ret["board"]]
ret["platform"] = alveo_default_platform[ret["board"]]
ret["ip"] = os.getenv("ALVEO_IP", "")
ret["username"] = os.getenv("ALVEO_USERNAME", "")
ret["password"] = os.getenv("ALVEO_PASSWORD", "")
ret["port"] = os.getenv("ALVEO_PORT", 22)
ret["target_dir"] = os.getenv("ALVEO_TARGET_DIR", "/tmp/finn_alveo_deploy")
ret["build_fxn"] = VitisBuild(
ret["part"],
target_clk_ns,
ret["platform"],
strategy=VitisOptStrategy.BUILD_SPEED,
)
else:
raise Exception("Unknown test build environment spec")
return ret
def step_synthesize_bitfile(model: ModelWrapper, cfg: DataflowBuildConfig):
"""Synthesize a bitfile for the using the specified shell flow, using either
Vivado or Vitis, to target the specified board."""
if DataflowOutputType.BITFILE in cfg.generate_outputs:
bitfile_dir = cfg.output_dir + "/bitfile"
os.makedirs(bitfile_dir, exist_ok=True)
report_dir = cfg.output_dir + "/report"
os.makedirs(report_dir, exist_ok=True)
partition_model_dir = cfg.output_dir + "/intermediate_models/kernel_partitions"
if cfg.shell_flow_type == ShellFlowType.VIVADO_ZYNQ:
model = model.transform(
ZynqBuild(
cfg.board,
cfg.synth_clk_period_ns,
cfg.enable_hw_debug,
partition_model_dir=partition_model_dir,
)
)
copy(model.get_metadata_prop("bitfile"), bitfile_dir + "/finn-accel.bit")
copy(model.get_metadata_prop("hw_handoff"), bitfile_dir + "/finn-accel.hwh")
copy(
model.get_metadata_prop("vivado_synth_rpt"),
report_dir + "/post_synth_resources.xml",
)
vivado_pynq_proj_dir = model.get_metadata_prop("vivado_pynq_proj")
timing_rpt = (
"%s/finn_zynq_link.runs/impl_1/top_wrapper_timing_summary_routed.rpt"
% vivado_pynq_proj_dir
)
copy(timing_rpt, report_dir + "/post_route_timing.rpt")
elif cfg.shell_flow_type == ShellFlowType.VITIS_ALVEO:
model = model.transform(
VitisBuild(
cfg._resolve_fpga_part(),
cfg.synth_clk_period_ns,
cfg.vitis_platform,
strategy=cfg._resolve_vitis_opt_strategy(),
enable_debug=cfg.enable_hw_debug,
floorplan_file=cfg.vitis_floorplan_file,
partition_model_dir=partition_model_dir,
)
)
copy(model.get_metadata_prop("bitfile"), bitfile_dir + "/finn-accel.xclbin")
copy(
model.get_metadata_prop("vivado_synth_rpt"),
report_dir + "/post_synth_resources.xml",
)
else:
raise Exception("Unrecognized shell_flow_type: " + str(cfg.shell_flow_type))
print("Bitfile written into " + bitfile_dir)
return model
def test_fpgadataflow_ipstitch_zynqbuild(board):
model = create_two_fc_model()
if model.graph.node[0].op_type == "StreamingDataflowPartition":
sdp_node = getCustomOp(model.graph.node[0])
assert sdp_node.__class__.__name__ == "StreamingDataflowPartition"
assert os.path.isfile(sdp_node.get_nodeattr("model"))
model = load_test_checkpoint_or_skip(sdp_node.get_nodeattr("model"))
# bitfile using ZynqBuild
model = model.transform(ZynqBuild(board, 10))
model.save(ip_stitch_model_dir +
"/test_fpgadataflow_ipstitch_customzynq.onnx")
bitfile_name = model.get_metadata_prop("bitfile")
assert bitfile_name is not None
assert os.path.isfile(bitfile_name)
def test_fpgadataflow_ipstitch_zynqbuild(board):
model = create_two_fc_model()
if model.graph.node[0].op_type == "StreamingDataflowPartition":
sdp_node = getCustomOp(model.graph.node[0])
assert sdp_node.__class__.__name__ == "StreamingDataflowPartition"
assert os.path.isfile(sdp_node.get_nodeattr("model"))
model = load_test_checkpoint_or_skip(sdp_node.get_nodeattr("model"))
# generate inputs for remote exec
iname = "inp"
idt = model.get_tensor_datatype(iname)
ishape = model.get_tensor_shape(iname)
x = gen_finn_dt_tensor(idt, ishape)
# bitfile using ZynqBuild
model = model.transform(ZynqBuild(board, 10))
model.save(ip_stitch_model_dir +
"/test_fpgadataflow_ipstitch_customzynq.onnx")
bitfile_name = model.get_metadata_prop("bitfile")
assert bitfile_name is not None
assert os.path.isfile(bitfile_name)
# deployment
try:
ip = os.environ[
"PYNQ_IP"] # no default for this one; skip if not defined
if ip == "":
pytest.skip("PYNQ board IP address not specified")
username = os.getenv("PYNQ_USERNAME", "xilinx")
password = os.getenv("PYNQ_PASSWORD", "xilinx")
port = os.getenv("PYNQ_PORT", 22)
target_dir = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn")
model = model.transform(
DeployToPYNQ(ip, port, username, password, target_dir))
deployment_dir = model.get_metadata_prop("pynq_deploy_dir")
assert deployment_dir is not None
assert os.path.isdir(deployment_dir)
# remote exec
input_dict = {"global_in": x}
outp = execute_onnx(model, input_dict)
assert np.isclose(outp["global_out"], x).all()
except KeyError:
pytest.skip("PYNQ board IP address not specified")
def create_IP_and_synthesis(model, platform, period_ns):
log("Creating Project and synthesis")
model = model.transform(ZynqBuild(platform=platform, period_ns=period_ns))
log("Synthesis completed!")
save(model, "7_post_synthesis")
return model