def test_fir_impulse():
load_coeff_ram_addr = coeff_ram.port['b'].addr
load_coeff_ram_blk = coeff_ram.port['b'].blk
load_coeff_ram_wen = coeff_ram.port['b'].wen
fir_0 = fir(s.clearn,
s.clock,
s.input,
s.output,
coeff_ram.port['a'].addr,
coeff_ram.port['a'].din,
coeff_ram.port['a'].blk,
coeff_ram.port['a'].wen,
coeff_ram.port['a'].dout,
delay_line_i_ram.port['a'].addr,
delay_line_i_ram.port['a'].din,
delay_line_i_ram.port['a'].blk,
delay_line_i_ram.port['a'].wen,
delay_line_i_ram.port['a'].dout,
delay_line_q_ram.port['a'].addr,
delay_line_q_ram.port['a'].din,
delay_line_q_ram.port['a'].blk,
delay_line_q_ram.port['a'].wen,
delay_line_q_ram.port['a'].dout,
enable,
bank1,
bank0,
N,
sim=s)
return fir_0, coeff_ram_inst, delay_line_i_ram_inst, delay_line_q_ram_inst
def test_fir_design():
load_coeff_ram_addr = coeff_ram.port['b'].addr
load_coeff_ram_blk = coeff_ram.port['b'].blk
load_coeff_ram_wen = coeff_ram.port['b'].wen
fir_0 = fir(s.clearn, s.clock, s.input, s.output,
coeff_ram.port['a'].addr,
coeff_ram.port['a'].din[0],
coeff_ram.port['a'].din[1],
coeff_ram.port['a'].blk,
coeff_ram.port['a'].wen,
coeff_ram.port['a'].dout[0],
coeff_ram.port['a'].dout[1],
delay_line_i_ram.port['a'].addr,
delay_line_i_ram.port['a'].din,
delay_line_i_ram.port['a'].blk,
delay_line_i_ram.port['a'].wen,
delay_line_i_ram.port['a'].dout,
delay_line_q_ram.port['a'].addr,
delay_line_q_ram.port['a'].din,
delay_line_q_ram.port['a'].blk,
delay_line_q_ram.port['a'].wen,
delay_line_q_ram.port['a'].dout,
bypass, bank1, bank0, N,
sim=s)
return fir_0, coeff_ram.rama, coeff_ram.ramb, delay_line_i_ram.ram, delay_line_q_ram.ram
def test_fir_design():
load_coeff_ram_addr = coeff_ram.port['b'].addr
load_coeff_ram_blk = coeff_ram.port['b'].blk
load_coeff_ram_wen = coeff_ram.port['b'].wen
fir_0 = fir(s.clearn, s.clock, s.input, s.output,
coeff_ram.port['a'].addr,
coeff_ram.port['a'].din,
coeff_ram.port['a'].blk,
coeff_ram.port['a'].wen,
coeff_ram.port['a'].dout,
delay_line_i_ram.port['a'].addr,
delay_line_i_ram.port['a'].din,
delay_line_i_ram.port['a'].blk,
delay_line_i_ram.port['a'].wen,
delay_line_i_ram.port['a'].dout,
delay_line_q_ram.port['a'].addr,
delay_line_q_ram.port['a'].din,
delay_line_q_ram.port['a'].blk,
delay_line_q_ram.port['a'].wen,
delay_line_q_ram.port['a'].dout,
enable, bank1, bank0, N,
sim=s)
coeff_ram_inst = coeff_ram.instance_type()(**coeff_ram.instance_signals())
delay_line_i_ram_inst = delay_line_i_ram.instance_type()(**delay_line_i_ram.instance_signals())
delay_line_q_ram_inst = delay_line_q_ram.instance_type()(**delay_line_q_ram.instance_signals())
return fir_0, coeff_ram_inst, delay_line_i_ram_inst, delay_line_q_ram_inst
def timing(): # Test removes overhead of pyb function calls
t = pyb.micros()
fir(data, coeffs, 100)
t1 = pyb.elapsed_micros(t)
t = pyb.micros()
fir(data, coeffs, 100)
fir(data, coeffs, 100)
t2 = pyb.elapsed_micros(t)
print(t2-t1,"uS")
def test_fir_design():
load_coeff_ram_addr = coeff_ram.port['b'].addr
load_coeff_ram_blk = coeff_ram.port['b'].blk
load_coeff_ram_wen = coeff_ram.port['b'].wen
fir_0 = fir(s.clearn,
s.clock,
s.input,
s.output,
coeff_ram.port['a'].addr,
coeff_ram.port['a'].din,
coeff_ram.port['a'].blk,
coeff_ram.port['a'].wen,
coeff_ram.port['a'].dout,
delay_line_i_ram.port['a'].addr,
delay_line_i_ram.port['a'].din,
delay_line_i_ram.port['a'].blk,
delay_line_i_ram.port['a'].wen,
delay_line_i_ram.port['a'].dout,
delay_line_q_ram.port['a'].addr,
delay_line_q_ram.port['a'].din,
delay_line_q_ram.port['a'].blk,
delay_line_q_ram.port['a'].wen,
delay_line_q_ram.port['a'].dout,
enable,
bank1,
bank0,
N,
sim=s)
coeff_ram_inst = coeff_ram.instance_type()(
**coeff_ram.instance_signals())
delay_line_i_ram_inst = delay_line_i_ram.instance_type()(
**delay_line_i_ram.instance_signals())
delay_line_q_ram_inst = delay_line_q_ram.instance_type()(
**delay_line_q_ram.instance_signals())
return fir_0, coeff_ram_inst, delay_line_i_ram_inst, delay_line_q_ram_inst
def test_fir_impulse():
load_coeff_ram_addr = coeff_ram.port['b'].addr
load_coeff_ram_blk = coeff_ram.port['b'].blk
load_coeff_ram_wen = coeff_ram.port['b'].wen
fir_0 = fir(s.clearn, s.clock, s.input, s.output,
coeff_ram.port['a'].addr,
coeff_ram.port['a'].din,
coeff_ram.port['a'].blk,
coeff_ram.port['a'].wen,
coeff_ram.port['a'].dout,
delay_line_i_ram.port['a'].addr,
delay_line_i_ram.port['a'].din,
delay_line_i_ram.port['a'].blk,
delay_line_i_ram.port['a'].wen,
delay_line_i_ram.port['a'].dout,
delay_line_q_ram.port['a'].addr,
delay_line_q_ram.port['a'].din,
delay_line_q_ram.port['a'].blk,
delay_line_q_ram.port['a'].wen,
delay_line_q_ram.port['a'].dout,
enable, bank1, bank0, N,
sim=s)
return fir_0, coeff_ram_inst, delay_line_i_ram_inst, delay_line_q_ram_inst
# optimization - no need to upsample, less mempry, less multiplications
dd2 = fir3_opt(dt_in, coef_fir3)
dd2 = np.around(dd2)
#print(dd2[0:50])
util.write_complex(dd2, "fir_up3.out")
# comparing to scypy FIR function
# upsemple by 3
l = 3 * len(dt_in)
dt_up = np.zeros(l, np.complex)
dt_up[::3] = dt_in
#dt_ref = lfilter(coef_fir3, 1.0, dt_up) / 2**15
#dt_ref = fir.fir_s(dt_up, coef_fir3, 15)
dt_ref = fir.fir(dt_up, coef_fir3, 15)
dt_ref = np.around(dt_ref)
print("Compare to scipy FIR")
diff = dd2 - dt_ref
diff = np.absolute(diff)
diff = diff[diff > 0]
print(f"Values count with difference: {len(diff)}")
dd2 = np.append(np.zeros(64, np.complex), dd2)
# comparing to ref file
fn_ref = "fir_up3.ref"
dt_ref = util.load_complex(fn_ref, ", ")
##print(dt_ref[6200:])
print("Compare to REF")
def cb(timer):
val = fir(data, coeffs, adc.read()) // 16 # Filter amd scale
dac2.write(max(0, min(
255, val))) # Constrain, shift (no DC from bandpass) and output
def cb1(timer): # For filters with 0 DC response
val = fir(data, coeffs, adc.read()) // 256 # Filter amd scale
dac2.write(max(0, min(255, val+128))) # Constrain, shift (no DC from bandpass) and output
def cb(timer):
dac2.write(fir(data, coeffs, adc.read()) // 1000000)
def test(): # Impulse response replays coeffs*impulse_size >> scale
print(fir(data, coeffs, 100))
for n in range(len(coeffs)+3):
print(fir(data, coeffs, 0))
res = np.array(res, np.complex) / 2**15
return res
if __name__ == '__main__':
fn_inp = "fir_up2.inp"
dt_in = util.load_complex(fn_inp, ", ")
# upsemple by 2
l = 2 * len(dt_in)
dt_up = np.zeros(l, np.complex)
dt_up[::2] = dt_in
out = fir.fir(dt_up, np.array(fir_up2_coef, np.int), 15)
#out = fir.fir_s(dt_up, np.array(fir_up2_coef, np.int), 15);
#out = fir.fir_t(dt_up, np.array(fir_up2_coef, np.int), 15);
out = np.around(out)
# comparing to ref file
fn_ref = "fir_up2.ref"
dt_ref = util.load_complex(fn_ref, ", ")
diff = out - dt_ref
diff = np.absolute(diff)
diff = diff[diff > 1.5]
print(f"Values count with difference more than 1 + 1j: {len(diff)}")
# comparing to scypy FIR function
dt_ref = lfilter(fir_up2_coef, 1.0, dt_up) / 2**15
dt_ref = np.around(dt_ref)
enable.next = True
inP.next = intbv(1)
else:
inP.next = intbv(0)
i.next = i + 1
if out_enable == 1:
if outP != j + 1 and j < 16:
print("ERROR: outP = ", outP, " not same as j = ", j)
if outP != 0 and j > 16:
print("ERROR: outP = ", outP, " not same as j = ", j)
j.next = j + 1
return check
clk = Signal(0)
resetn = Signal(0)
enable = Signal(0)
inP = Signal(intbv(0)[16:])
outP = Signal(intbv(0)[16:])
out_enable = Signal(0)
clk_driver_inst = clk_driver(clk)
dut = fir(clk, resetn, enable, inP, outP, out_enable)
check = checker(clk, resetn, enable, inP, outP, out_enable)
sim = Simulation(clk_driver_inst, dut, check)
sim.run(2000)
