def add_module_owire_port(self, name, eqd): """ Add the specified eqd as an output wire port of the module. """ a = Attrib(names.give('ow_{0}'.format(name)), None) a.set_eqdef(eqd) self.add_eqs([a]) wp = ModWirePort(ModWirePort.OUT, name, NId(a.get_core())) self.all_modwireports.append(wp)
def add_port_to(self, pname, eqval): """ Add new port named 'pname', input to the instance, driven by eqval. """ # an attribute through which the output signal is routed at = Attrib(names.give('ow_{0}_{1}'.format(self.iname, pname)), None) if eqval: at.set_eqdef(eqval) self.mod.add_eqs([at]) at.get_core().mark_as_necessary() # create the wire port of the instance wp = ModWirePort(ModWirePort.IN, pname, NId(at.get_core())) self.wireports.append(wp) return at.get_core()
class PipeBase: """ A base class for pipe heads and tails. They are also used for element ports. """ def __init__(self, elm, idx, nm = None, dtype = None): assert isinstance(elm, Element) assert type(idx) == int if nm is None: nm = elm.get_name() # the Element this pipe part belongs self.element = elm # the port index in the element self.prt_idx = idx # name of the port/pipe self.name = nm # the stage this pipe belongs to self.stage = Stage(self) # the P and R attributes of the pipe self.attr_F = Attrib('F%s%d' % (nm, idx), types.Bool_t, AttrKind.Flows) self.attr_F.set_eqdef( NPrf(Prf.AND, []) ) self.attr_D = Attrib('D%s%d' % (nm, idx), dtype, AttrKind.Data) self.attr_FI = None # driver for F, only in module ports # companions self.attr_D.get_core().set_companion(AttrKind.Flows, self.attr_F) # self.attr_D.set_companion(AttrKind.Ready, self.attr_R) # the type of boundary wrt stages self.stage_bound = Stage.INTRA def get_elmport(self): return (self.element, self.prt_idx) def get_aD(self): return self.attr_D def get_aF(self): return self.attr_F def get_aFI(self): return self.attr_FI def get_D_core(self): return self.attr_D.get_core() def get_F_core(self): return self.attr_F.get_core() def get_FI_core(self): return self.attr_FI.get_core() def get_stage(self): return self.stage def get_stage_bound(self): return self.stage_bound def rename(self, new_nm): self.name = new_nm self.attr_F.rename('F{0}{1}'.format(new_nm, self.prt_idx)) self.attr_D.rename('D{0}{1}'.format(new_nm, self.prt_idx)) def set_stage_bound(self, b): self.stage_bound = b def vhdl_print_modport__impl(self, drct, idrct): sl = ['{0}_P : {1} {2}'.format(self.element.get_name(), drct, PrintAsVhdlTrav().run_on(self.get_FP_core().get_actype())), '{0}_R : {1} {2}'.format(self.element.get_name(), idrct, PrintAsVhdlTrav().run_on(self.get_FR_core().get_actype())), '{0}_D : {1} {2}'.format(self.element.get_name(), drct, PrintAsVhdlTrav().run_on(self.get_D_core().get_actype())) ] return sl def mark_attribs_necessary(self): # self.get_P_core().mark_as_necessary() # self.get_R_core().mark_as_necessary() self.get_F_core().mark_as_necessary() self.get_D_core().mark_as_necessary() def merge_stages(self, other): """ Merge the stage of 'other' to self. """ if self.stage is not other.stage: # remember the other's stage o_stage = other.stage self.stage.merge(o_stage) # print 'merge_stages: merged into Stage {0}, emptied Stage {1}'.format(self.stage.id, o_stage.id) def __str__(self): return '{0}.{1}'.format(self.name, self.prt_idx)