def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
encoder_port = self.sdram.crossbar.get_port(mode="read", dw=128)
self.submodules.encoder_reader = EncoderDMAReader(encoder_port)
encoder_cdc = stream.AsyncFIFO([("data", 128)], 4)
encoder_cdc = ClockDomainsRenamer({
"write": "sys",
"read": "encoder"
})(encoder_cdc)
encoder_buffer = ClockDomainsRenamer("encoder")(EncoderBuffer())
encoder = Encoder(platform)
encoder_streamer = USBStreamer(platform, platform.request("fx2"))
self.submodules += encoder_cdc, encoder_buffer, encoder, encoder_streamer
self.comb += [
self.encoder_reader.source.connect(encoder_cdc.sink),
encoder_cdc.source.connect(encoder_buffer.sink),
encoder_buffer.source.connect(encoder.sink),
encoder.source.connect(encoder_streamer.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]), encoder.bus)
self.add_memory_region("encoder",
self.mem_map["encoder"] + self.shadow_base,
0x2000)
self.platform.add_period_constraint(encoder_streamer.cd_usb.clk, 10.0)
encoder_streamer.cd_usb.clk.attr.add("keep")
self.crg.cd_encoder.clk.attr.add("keep")
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.crg.cd_encoder.clk,
encoder_streamer.cd_usb.clk)
def __init__(self, platform, **kwargs):
VideomixerSoC.__init__(self, platform, **kwargs)
lasmim = self.sdram.crossbar.get_master()
self.submodules.encoder_reader = EncoderDMAReader(lasmim)
self.submodules.encoder_cdc = RenameClockDomains(
AsyncFIFO([("data", 128)], 4), {
"write": "sys",
"read": "encoder"
})
self.submodules.encoder_buffer = RenameClockDomains(
EncoderBuffer(), "encoder")
self.submodules.encoder_fifo = RenameClockDomains(
SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 16),
"encoder")
self.submodules.encoder = Encoder(platform)
encoder_port = self.ethcore.udp.crossbar.get_port(8000, 8)
self.submodules.encoder_streamer = UDPStreamer(
convert_ip("192.168.1.15"), 8000)
self.comb += [
platform.request("user_led", 0).eq(self.encoder_reader.source.stb),
platform.request("user_led", 1).eq(self.encoder_reader.source.ack),
Record.connect(self.encoder_reader.source, self.encoder_cdc.sink),
Record.connect(self.encoder_cdc.source, self.encoder_buffer.sink),
Record.connect(self.encoder_buffer.source, self.encoder_fifo.sink),
Record.connect(self.encoder_fifo.source, self.encoder.sink),
Record.connect(self.encoder.source, self.encoder_streamer.sink),
Record.connect(self.encoder_streamer.source, encoder_port.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]),
self.encoder.bus)
self.add_memory_region("encoder",
self.mem_map["encoder"] + self.shadow_base,
0x2000)
def __init__(self, platform, **kwargs):
VideomixerSoC.__init__(self, platform, **kwargs)
lasmim = self.sdram.crossbar.get_master()
self.submodules.encoder_reader = EncoderDMAReader(lasmim)
self.submodules.encoder_cdc = RenameClockDomains(AsyncFIFO([("data", 128)], 4),
{"write": "sys", "read": "encoder"})
self.submodules.encoder_buffer = RenameClockDomains(EncoderBuffer(), "encoder")
self.submodules.encoder_fifo = RenameClockDomains(SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 16), "encoder")
self.submodules.encoder = Encoder(platform)
self.submodules.usb_streamer = USBStreamer(platform, platform.request("fx2"))
self.comb += [
Record.connect(self.encoder_reader.source, self.encoder_cdc.sink),
Record.connect(self.encoder_cdc.source, self.encoder_buffer.sink),
Record.connect(self.encoder_buffer.source, self.encoder_fifo.sink),
Record.connect(self.encoder_fifo.source, self.encoder.sink),
Record.connect(self.encoder.source, self.usb_streamer.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]), self.encoder.bus)
self.add_memory_region("encoder", self.mem_map["encoder"]+self.shadow_base, 0x2000)
platform.add_platform_command("""
NET "{usb_clk}" TNM_NET = "GRPusb_clk";
TIMESPEC "TSise_sucks11" = FROM "GRPusb_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSise_sucks12" = FROM "GRPsys_clk" TO "GRPusb_clk" TIG;
""", usb_clk=platform.lookup_request("fx2").ifclk)
def __init__(self, platform, **kwargs):
base_cls.__init__(self, platform, **kwargs)
self.submodules.encoder_reader = EncoderDMAReader(self.sdram.crossbar.get_port())
self.submodules.encoder_cdc = ClockDomainsRenamer({"write": "sys", "read": "encoder"})(stream.AsyncFIFO([("data", 128)], 4))
self.submodules.encoder_buffer = ClockDomainsRenamer("encoder")(EncoderBuffer())
self.submodules.encoder = Encoder(platform)
fx2_pads = platform.request("fx2")
self.submodules.encoder_streamer = USBStreamer(platform, fx2_pads)
self.comb += [
self.encoder_reader.source.connect(self.encoder_cdc.sink),
self.encoder_cdc.source.connect(self.encoder_buffer.sink),
self.encoder_buffer.source.connect(self.encoder.sink),
self.encoder.source.connect(self.encoder_streamer.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]), self.encoder.bus)
self.add_memory_region("encoder", self.mem_map["encoder"] + self.shadow_base, 0x2000)
self.platform.add_period_constraint(self.encoder_streamer.cd_usb.clk, 10.0)
self.specials += Keep(self.encoder_streamer.cd_usb.clk)
self.specials += Keep(self.crg.cd_encoder.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.crg.cd_encoder.clk,
self.encoder_streamer.cd_usb.clk)
def __init__(self, platform, **kwargs):
base_cls.__init__(self, platform, **kwargs)
self.submodules.encoder_reader = EncoderDMAReader(self.sdram.crossbar.get_port())
self.submodules.encoder = Encoder(platform)
fx2_pads = platform.request("fx2")
self.submodules.encoder_streamer = USBStreamer(platform, fx2_pads)
self.comb += [
self.encoder_reader.source.connect(self.encoder.sink),
self.encoder.source.connect(self.encoder_streamer.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]), self.encoder.bus)
self.add_memory_region("encoder", self.mem_map["encoder"] + self.shadow_base, 0x2000)
self.platform.add_period_constraint(self.encoder_streamer.cd_usb.clk, 10.0)
self.specials += Keep(self.encoder_streamer.cd_usb.clk)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.encoder_streamer.cd_usb.clk)
