Python reg_write32b Exemples

Exemple #1

Fichier : gbt_config_errclr_sf5.py Projet : alacrities/GBT4FELIX

#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,1)
#reg_write1b(RegAddr.REG_RXSLIDE,0x400000,0)

ch = 22 + 4
a = reg_read1b(RegAddr.REG_TOPBOT, ch)
reg_write1b(RegAddr.REG_TOPBOT, ch, 1 - a)

reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)
reg_write32b(RegAddr.REG_RXSLIDE, 2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0)

Exemple #2

Fichier : gbt_config_errclr.py Projet : alacrities/GBT4FELIX

    print "aaa"
    reg_write64b(RegAddr.REG_TX_CXP1_FORMAT, 0x55555500555555)

    reg_write64b(RegAddr.REG_RX_CXP1_FORMAT, 0x55555500555555)

elif mod == 2:
    reg_write64b(RegAddr.REG_TX_CXP1_FORMAT, 0x00000000555555)

    reg_write64b(RegAddr.REG_RX_CXP1_FORMAT, 0x00000000555555)

else:
    print "bbb"
    reg_write64b(RegAddr.REG_TX_CXP1_FORMAT, 0x00000000000000)
    reg_write64b(RegAddr.REG_RX_CXP1_FORMAT, 0x00000000000000)

reg_write32b(RegAddr.REG_TXOPT_CXP1_LOW, 0x000000)
reg_write32b(RegAddr.REG_TXOPT_CXP2_LOW, 0x000000)
reg_write32b(RegAddr.REG_RXOPT_CXP1_LOW, 0x000000)
reg_write32b(RegAddr.REG_RXOPT_CXP2_LOW, 0x000000)
print "GBT TX reset..."
reg_write32b(RegAddr.REG_GBTTXRST, 0xFFF0FFF)
time.sleep(0.5)
reg_write32b(RegAddr.REG_GBTTXRST, 0)
time.sleep(1)

print "GBT RX reset..."
reg_write32b(RegAddr.REG_GBTRXRST, 0xFFF0FFF)
time.sleep(0.5)
reg_write32b(RegAddr.REG_GBTRXRST, 0)
time.sleep(1)

Exemple #3

Fichier : gbt_config.py Projet : alacrities/GBT4FELIX

topbot_final=-1

if ch<12:
    ch=ch
else:
    ch=ch+4



# set TOPBOT & ODDEVEN to 0
reg_write1b(RegAddr.REG_TOPBOT,ch,0)
reg_write1b(RegAddr.REG_ODDEVEN,ch,0)

# check alignment status
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,1)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,0)
time.sleep(timewait)
ret=reg_read1b(RegAddr.REG_RX_ALIGNMENT_DONE,ch)
# ret=1 means alignment is finished

phase_cnt=10
oddeven=0

while phase_cnt != 0:
  #  for each topbot oddeven, there are 10 phases, totally 40 phases.
  #  print ret
    if ret==0:
        if phase_cnt>1:
	    phase_cnt = phase_cnt - 1
            # shift 1 phase

Exemple #4

Fichier : gbt_config_errclr.py Projet : alacrities/GBT4FELIX

    reg_write64b(RegAddr.REG_TX_CXP1_FORMAT,0x55555500555555)

    reg_write64b(RegAddr.REG_RX_CXP1_FORMAT,0x55555500555555)

elif mod==2:
    reg_write64b(RegAddr.REG_TX_CXP1_FORMAT,0x00000000555555)

    reg_write64b(RegAddr.REG_RX_CXP1_FORMAT,0x00000000555555)


else:
    print "bbb"
    reg_write64b(RegAddr.REG_TX_CXP1_FORMAT,0x00000000000000)
    reg_write64b(RegAddr.REG_RX_CXP1_FORMAT,0x00000000000000)

reg_write32b(RegAddr.REG_TXOPT_CXP1_LOW,0xFFFFFF)
reg_write32b(RegAddr.REG_TXOPT_CXP2_LOW,0xFFFFFF)
reg_write32b(RegAddr.REG_RXOPT_CXP1_LOW,0x000000)
reg_write32b(RegAddr.REG_RXOPT_CXP2_LOW,0x000000)
print "GBT TX reset..."
reg_write32b(RegAddr.REG_GBTTXRST,0xFFF0FFF)
time.sleep(0.5)
reg_write32b(RegAddr.REG_GBTTXRST,0)
time.sleep(1)
print "GBT RX reset..."
reg_write32b(RegAddr.REG_GBTRXRST,0xFFF0FFF)
time.sleep(0.5)
reg_write32b(RegAddr.REG_GBTRXRST,0)
time.sleep(1)

OUTSEL=reg_read32b(RegAddr.REG_OUTSEL_CALC)

Exemple #5

Fichier : gbt_config_top.py Projet : alacrities/GBT4FELIX

import os
from gbt_config_lib import reg_write1b, reg_read32b, reg_read1b, reg_write32b, reg_read64b, reg_write64b
from gbt_config_lib import RegAddrTable
import numpy as np
import sys 
import time

RegAddr=RegAddrTable()

print "configure I2C chips..."
reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,8)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,0)
time.sleep(2)


reg_write32b(RegAddr.REG_TXUSRRDY,0xFFF0FFF)
#reg_write32b(RegAddr.REG_TXUSRRDY,0)
reg_write32b(RegAddr.REG_RXUSRRDY,0xFFF0FFF)
#reg_write32b(RegAddr.REG_RXUSRRDY,0)
print "Quad Softreset..."
# Quad SoftRst
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST,0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST,0)
time.sleep(2)

print "Quad SoftTxreset..."
# Quad SoftTxRst
reg_write32b(RegAddr.REG_SOFTTXRST,0x70007000)
time.sleep(0.5)

Exemple #6

Fichier : gbt_config_top.py Projet : alacrities/GBT4FELIX

import os
from gbt_config_lib import reg_write1b, reg_read32b, reg_read1b, reg_write32b, reg_read64b, reg_write64b
from gbt_config_lib import RegAddrTable
import numpy as np
import sys 
import time

RegAddr=RegAddrTable()
'''

reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,8)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,0)
time.sleep(2)
'''

reg_write32b(RegAddr.REG_TXUSRRDY,0xFFF0FFF)
#reg_write32b(RegAddr.REG_TXUSRRDY,0)
reg_write32b(RegAddr.REG_RXUSRRDY,0xFFF0FFF)
#reg_write32b(RegAddr.REG_RXUSRRDY,0)

# Quad SoftRst
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST,0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST,0)
time.sleep(2)

# Quad SoftTxRst
reg_write32b(RegAddr.REG_SOFTTXRST,0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTTXRST,0)

Exemple #7

Fichier : gbt_config_RecRxUsrClk_SW.py Projet : alacrities/GBT4FELIX

import datetime

RegAddr=RegAddrTable()
timewait=0.1
#print "configure I2C chips..."
#reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,8)
#time.sleep(0.5)
#reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,0)
#time.sleep(2)

#Choose TX and RX sources
#reg_write32b(RegAddr.REG_TX_SEL,0x0)
#reg_write32b(RegAddr.REG_RX_SEL,0x0)

print "Set Rx Alignment Mode to Firmware control"
reg_write32b(RegAddr.REG_MOD_SEL,0x2)

print "Set TXUSRRDY & RXUSRRDY..."
reg_write32b(RegAddr.REG_TXUSRRDY,0xFFF0FFF)
#reg_write32b(RegAddr.REG_TXUSRRDY,0)
reg_write32b(RegAddr.REG_RXUSRRDY,0xFFF0FFF)
#reg_write32b(RegAddr.REG_RXUSRRDY,0)

print "Set TX Timedomain Crossing method..."
reg_write32b(RegAddr.REG_TXTC_SEL,0x00000000)

print "Quad Softreset for all quads..."
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST,0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST,0)
time.sleep(2)

Exemple #8

Fichier : gbt_config_latopt.py Projet : alacrities/GBT4FELIX

timewait=0.1

print "Set the TX & RX GBT encoding mode for all channels..."
reg_write64b(RegAddr.REG_TX_CXP1_FORMAT,0x0000000000000000)
reg_write64b(RegAddr.REG_RX_CXP1_FORMAT,0x0000000000000000)

print "Set TX Timedomain Crossing method..."


## 1: can gurantee a fixed latency
#reg_write32b(RegAddr.REG_TXTC_SEL,0x0FFF0FFF)

## When using this option, the 0x2580 and 0x2590 need to be configured, to select a best phase from 0-5, make the data transferred from 40M to 240M is right, and has the lowest latency.

## 0:
reg_write32b(RegAddr.REG_TXTC_SEL,0x00000000)

print "GBT TX Latency Optimization for all channels... "
reg_write64b(RegAddr.REG_TXOPT_LOW,0xFFFFFFFFFFFF)

print "GBT TX Reset for all channels..."
reg_write32b(RegAddr.REG_GBTTXRST,0xFFF0FFF)
time.sleep(0.5)
reg_write32b(RegAddr.REG_GBTTXRST,0)
time.sleep(1)


print "GBT RX Latency Optimization for all channels..."
reg_write64b(RegAddr.REG_RXOPT_LOW,0xFFFFFF)

Exemple #9

import datetime

RegAddr = RegAddrTable()
timewait = 0.1
#print "configure I2C chips..."
#reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,8)
#time.sleep(0.5)
#reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,0)
#time.sleep(2)

#Choose TX and RX sources
#reg_write32b(RegAddr.REG_TX_SEL,0x0)
#reg_write32b(RegAddr.REG_RX_SEL,0x0)

print "Set Rx Alignment Mode to Firmware control"
reg_write32b(RegAddr.REG_MOD_SEL, 0x0)

print "Set TXUSRRDY & RXUSRRDY..."
reg_write32b(RegAddr.REG_TXUSRRDY, 0xFFF0FFF)
#reg_write32b(RegAddr.REG_TXUSRRDY,0)
reg_write32b(RegAddr.REG_RXUSRRDY, 0xFFF0FFF)
#reg_write32b(RegAddr.REG_RXUSRRDY,0)

print "Set TX Timedomain Crossing method..."
reg_write32b(RegAddr.REG_TXTC_SEL, 0x00000000)

print "Quad Softreset for all quads..."
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST, 0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST, 0)
time.sleep(2)

Exemple #10

Fichier : gbt_config_latopt.py Projet : alacrities/GBT4FELIX

timewait = 0.1

print "Set the TX & RX GBT encoding mode for all channels..."
reg_write64b(RegAddr.REG_TX_CXP1_FORMAT, 0x0000000000000000)
reg_write64b(RegAddr.REG_RX_CXP1_FORMAT, 0x0000000000000000)

print "Set TX Timedomain Crossing method..."

## 1: can gurantee a fixed latency
#reg_write32b(RegAddr.REG_TXTC_SEL,0x0FFF0FFF)

## When using this option, the 0x2580 and 0x2590 need to be configured, to select a best phase from 0-5, make the data transferred from 40M to 240M is right, and has the lowest latency.

## 0:
reg_write32b(RegAddr.REG_TXTC_SEL, 0x00000000)

print "GBT TX Latency Optimization for all channels... "
reg_write64b(RegAddr.REG_TXOPT_LOW, 0xFFFFFFFFFFFF)

print "GBT TX Reset for all channels..."
reg_write32b(RegAddr.REG_GBTTXRST, 0xFFF0FFF)
time.sleep(0.5)
reg_write32b(RegAddr.REG_GBTTXRST, 0)
time.sleep(1)

print "GBT RX Latency Optimization for all channels..."
reg_write64b(RegAddr.REG_RXOPT_LOW, 0xFFFFFF)

print "GBT RX reset for all channels..."
reg_write32b(RegAddr.REG_GBTRXRST, 0xFFF0FFF)

Exemple #11

Fichier : gbt_config_top_tx.py Projet : alacrities/GBT4FELIX

import time

RegAddr=RegAddrTable()

#print "configure I2C chips..."
#reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,8)
#time.sleep(0.5)
#reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,0)
#time.sleep(2)

#Choose TX and RX sources
#reg_write32b(RegAddr.REG_TX_SEL,0x0)
#reg_write32b(RegAddr.REG_RX_SEL,0x0)

print "Set TXUSRRDY & RXUSRRDY..."
reg_write32b(RegAddr.REG_TXUSRRDY,0xFFF0FFF)
#reg_write32b(RegAddr.REG_TXUSRRDY,0)
reg_write32b(RegAddr.REG_RXUSRRDY,0xFFF0FFF)
#reg_write32b(RegAddr.REG_RXUSRRDY,0)

print "Quad Softreset for all quads..."
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST,0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST,0)
time.sleep(2)

print "Quad SoftTxreset for all quads..."
reg_write32b(RegAddr.REG_SOFTTXRST,0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTTXRST,0)
time.sleep(2)

Exemple #12

## anytime when cable length or board, or firmware is changed, let TOPBOT_MODE=0 to run one time
## If use software to Rx align, after the alignment, save 0x2510 to the database for this board
## If use FSM to Rx align, after the alignment, read 0x2760, save it to the database.
TOPBOT_DATA_BASE = 0x00060F42

DESMUX_MODE = 0

RegAddr = RegAddrTable()

timewait = 0.1

print "GBT RX Latency Optimization for all channels..."
reg_write64b(RegAddr.REG_RXOPT_LOW, 0x000000)

print "GTH RX reset for all channels..."
reg_write32b(RegAddr.REG_GTHRXRST, 0xFFF0FFF)
time.sleep(0.1)
reg_write32b(RegAddr.REG_GTHRXRST, 0x0000000)

print "Set the RX GBT encoding mode for all channels..."

reg_write64b(RegAddr.REG_RX_CXP1_FORMAT, 0x0000000000000000)

if RX_ALIGN_MODE == 0:
    if TOPBOT_MODE == 0:
        reg_write32b(RegAddr.REG_MODESEL, (0x0 + DESMUX_MODE))
        time.sleep(1)

    else:
        reg_write32b(RegAddr.REG_TOPBOT, TOPBOT_DATA_BASE)
        reg_write32b(RegAddr.REG_MODESEL, (0x4 + DESMUX_MODE))

Exemple #13

Fichier : gbt_config_top_rx.py Projet : alacrities/GBT4FELIX

## If use FSM to Rx align, after the alignment, read 0x2760, save it to the database.
TOPBOT_DATA_BASE=0x00060F42


DESMUX_MODE=0


RegAddr=RegAddrTable()

timewait=0.1

print "GBT RX Latency Optimization for all channels..."
reg_write64b(RegAddr.REG_RXOPT_LOW,0x000000)

print "GTH RX reset for all channels..."
reg_write32b(RegAddr.REG_GTHRXRST,0xFFF0FFF)
time.sleep(0.1)
reg_write32b(RegAddr.REG_GTHRXRST,0x0000000)

print "Set the RX GBT encoding mode for all channels..."

reg_write64b(RegAddr.REG_RX_CXP1_FORMAT,0x0000000000000000)



if RX_ALIGN_MODE==0:
    if TOPBOT_MODE==0:
        reg_write32b(RegAddr.REG_MODESEL,(0x0+DESMUX_MODE))
        time.sleep(1)    

    else:

Exemple #14

Fichier : gbt_config_top.py Projet : alacrities/GBT4FELIX

import os
from gbt_config_lib import reg_write1b, reg_read32b, reg_read1b, reg_write32b, reg_read64b, reg_write64b
from gbt_config_lib import RegAddrTable
import numpy as np
import sys
import time

RegAddr = RegAddrTable()

print "configure I2C chips..."
reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK, 8)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK, 0)
time.sleep(2)

reg_write32b(RegAddr.REG_TXUSRRDY, 0xFFF0FFF)
#reg_write32b(RegAddr.REG_TXUSRRDY,0)
reg_write32b(RegAddr.REG_RXUSRRDY, 0xFFF0FFF)
#reg_write32b(RegAddr.REG_RXUSRRDY,0)
print "Quad Softreset..."
# Quad SoftRst
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST, 0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST, 0)
time.sleep(2)

print "Quad SoftTxreset..."
# Quad SoftTxRst
reg_write32b(RegAddr.REG_SOFTTXRST, 0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTTXRST, 0)

Exemple #15

import os
from gbt_config_lib import reg_write1b, reg_read32b, reg_read1b, reg_write32b, reg_read64b, reg_write64b
from gbt_config_lib import RegAddrTable
import numpy as np
import sys
import time

RegAddr = RegAddrTable()
'''

reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,8)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,0)
time.sleep(2)
'''

reg_write32b(RegAddr.REG_TXUSRRDY, 0xFFF0FFF)
#reg_write32b(RegAddr.REG_TXUSRRDY,0)
reg_write32b(RegAddr.REG_RXUSRRDY, 0xFFF0FFF)
#reg_write32b(RegAddr.REG_RXUSRRDY,0)

# Quad SoftRst
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST, 0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST, 0)
time.sleep(2)

# Quad SoftTxRst
reg_write32b(RegAddr.REG_SOFTTXRST, 0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTTXRST, 0)

Exemple #16

import time

RegAddr = RegAddrTable()

#print "configure I2C chips..."
#reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,8)
#time.sleep(0.5)
#reg_write32b(RegAddr.REG_SPI_I2C_TRIG_ERRCHK,0)
#time.sleep(2)

#Choose TX and RX sources
#reg_write32b(RegAddr.REG_TX_SEL,0x0)
#reg_write32b(RegAddr.REG_RX_SEL,0x0)

print "Set TXUSRRDY & RXUSRRDY..."
reg_write32b(RegAddr.REG_TXUSRRDY, 0xFFF0FFF)
#reg_write32b(RegAddr.REG_TXUSRRDY,0)
reg_write32b(RegAddr.REG_RXUSRRDY, 0xFFF0FFF)
#reg_write32b(RegAddr.REG_RXUSRRDY,0)

print "Quad Softreset for all quads..."
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST, 0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTRST_GTHTXRST, 0)
time.sleep(2)

print "Quad SoftTxreset for all quads..."
reg_write32b(RegAddr.REG_SOFTTXRST, 0x70007000)
time.sleep(0.5)
reg_write32b(RegAddr.REG_SOFTTXRST, 0)
time.sleep(2)