def netlistToVhdlStr(name: str, netlist: RtlNetlist,
interfaces: Dict[RtlSignal, DIRECTION]):
name_scope = NameScope(None, name, True)
buff = StringIO()
store_manager = SaveToStream(Vhdl2008Serializer, buff)
netlist.create_HdlModuleDec(name, store_manager, {})
netlist.interfaces = interfaces
for s, d in interfaces.items():
s._interface = True
pi = portItemfromSignal(s, netlist, d)
# port of current top component
s.name = name_scope.checked_name(s.name, s)
pi.connectInternSig(s)
netlist.ent.ports.append(pi)
netlist.ent.ports.sort(key=lambda x: x.name)
netlist.create_HdlModuleDef(DummyPlatform(), store_manager)
store_manager.write(netlist.arch)
return buff.getvalue()
def checked_name(self, actualName, actualObj):
actualName = self.RE_MANY_UNDERSCORES.sub(r"_", actualName)
return NameScope.checked_name(self, actualName, actualObj)
def checked_name(self, actualName, actualObj):
actualName = self.RE_MANY_UNDERSCORES.sub(r"_", actualName)
if actualName[0] == "_":
actualName = "u" + actualName
return NameScope.checked_name(self, actualName, actualObj)