def convert_tlsf_or_acacia_to_acacia(spec_file_name: str, is_moore_=None) -> (str, str, bool): if spec_file_name.endswith('.ltl'): ltl_text, part_text = readfile(spec_file_name), readfile( spec_file_name.replace('.ltl', '.part')) return ltl_text, part_text, is_moore_ rc, out, err = execute_shell('{syfco} -ins {spec_file_name}'.format( syfco=SYFCO_PATH, spec_file_name=spec_file_name)) assert_exec_strict(rc, out, err) part_text = '.inputs ' + ' '.join(_parse_tuple_str( out.lower())) # syfco lowers all signal names in props rc, out, err = execute_shell('{syfco} -outs {spec_file_name}'.format( syfco=SYFCO_PATH, spec_file_name=spec_file_name)) assert_exec_strict(rc, out, err) part_text += '\n.outputs ' + ' '.join(_parse_tuple_str( out.lower())) # syfco lowers all signal names in props # rc, out, err = execute_shell('{syfco} -f acacia -m fully -os Moore {spec_file_name}' # .format(syfco=SYFCO_PATH, spec_file_name=spec_file_name)) # rc, out, err = execute_shell('{syfco} -f acacia -m fully {spec_file_name}' # .format(syfco=SYFCO_PATH, spec_file_name=spec_file_name)) rc, out, err = execute_shell( '{syfco} -f lily -m fully -nr {spec_file_name}'.format( syfco=SYFCO_PATH, spec_file_name=spec_file_name)) assert_exec_strict(rc, out, err) ltl_text = out return ltl_text, part_text, get_spec_type(spec_file_name)
def verilog_to_aiger(verilog:str) -> str: verilog_file_name = create_unique_file(verilog, suffix='.v') aiger_file_name = create_unique_file(suffix='.aag') script = """ read_verilog {verilog_file} synth -flatten -auto-top abc -g AND write_aiger -ascii -symbols -zinit {aiger_file}""".format(aiger_file=aiger_file_name, verilog_file=verilog_file_name) script_file_name = create_unique_file(text=script, suffix='.ys') files_to_remove = (aiger_file_name, verilog_file_name, script_file_name) # tmp files stay if smth goes wrong # on some examples yosys fails with a standard stack limit, so we raise it hard_limit = resource.getrlimit(resource.RLIMIT_STACK)[1] resource.setrlimit(resource.RLIMIT_STACK, (hard_limit, hard_limit)) rc, out, err = execute_shell('{yosys} -Q -s {script}'.format( yosys=YOSYS_PATH, script=script_file_name)) assert_exec_strict(rc, out, err) logging.debug('yosys stdout:\n' + out) res = readfile(aiger_file_name) [os.remove(f) for f in files_to_remove] return res
def verilog_to_aiger(verilog:str) -> str: input_verilog_file = create_tmp_file(verilog, suffix='v') file_blif_mv = create_tmp_file(suffix='.mv') file_aiger_tmp = create_tmp_file(suffix='.aag') file_output_aiger = create_tmp_file(suffix='.aag') files_to_remove = (input_verilog_file, file_blif_mv, file_aiger_tmp, file_output_aiger) # tmp files stay if smth goes wrong # vl2mv # on some examples vl2mv fails with a standard stack limit, so we raise it hard_limit = resource.getrlimit(resource.RLIMIT_STACK)[1] resource.setrlimit(resource.RLIMIT_STACK, (hard_limit, hard_limit)) rc, out, err = execute_shell('{vl2mv} {file_input_verilog} -o {file_blif_mv}'.format( vl2mv=VL2MV_PATH, file_input_verilog=input_verilog_file, file_blif_mv=file_blif_mv)) if rc == -11: logging.warning('vl2mv caught SIGSEGV: ha-ha! Re-run me on this example, or manually convert into aiger') logging.debug('verilog was: ' + readfile(input_verilog_file)) assert rc == 0, rc_out_err_to_str(rc, out, err) # no check that stderr='' because vl2mv outputs the input file name # abc rc, out, err = execute_shell('{abc} -c ' '"read_blif_mv {file_blif_mv}; ' 'strash; refactor; rewrite; dfraig; rewrite; dfraig; ' 'write_aiger -s {file_aiger_tmp}"'.format( file_blif_mv=file_blif_mv, abc=ABC_PATH, file_aiger_tmp=file_aiger_tmp)) assert_exec_strict(rc, out, err) # aigtoaig rc, out, err = execute_shell('{aigtoaig} {file_aiger_tmp} {file_output_aiger}'.format( aigtoaig=AIGTOAIG_PATH, file_aiger_tmp=file_aiger_tmp, file_output_aiger=file_output_aiger)) assert_exec_strict(rc, out, err) res = readfile(file_output_aiger) [os.remove(f) for f in files_to_remove] return res
def main(): parser = argparse.ArgumentParser( description='Convert Verilog to AIGER', formatter_class=argparse.ArgumentDefaultsHelpFormatter) parser.add_argument('verilog', metavar='verilog', type=str, help='input verilog file') parser.add_argument('-v', '--verbose', action='count', default=0) args = parser.parse_args() setup_logging(args.verbose) args = parser.parse_args() v_file = args.verilog print(verilog_to_aiger(readfile(v_file)))
def main(): parser = argparse.ArgumentParser( description='I remove `bad` output and ' 'remove prefix `controllable` from output names,' 'Such models are produced by tool `sdf`.', formatter_class=argparse.ArgumentDefaultsHelpFormatter) parser.add_argument('aiger', metavar='aiger', type=str, help='input AIGER file') parser.add_argument('bad', metavar='bad', type=str, help='name of the bad output') args = parser.parse_args() file = args.aiger bad = args.bad print(convert_aiger_model_to_tlsf_model(readfile(file), bad))
def main(): """ :return: 1 if model is found, 0 otherwise """ parser = argparse.ArgumentParser( description="Bounded Synthesis Tool", formatter_class=argparse.ArgumentDefaultsHelpFormatter ) parser.add_argument("spec", metavar="spec", type=str, help="the specification file (acacia+ format)") group = parser.add_mutually_exclusive_group() # default: moore=False, mealy=True group.add_argument("--moore", action="store_true", default=False, help="system is Moore") group.add_argument("--mealy", action="store_false", default=True, help="system is Mealy") group = parser.add_mutually_exclusive_group() group.add_argument( "--bound", metavar="bound", type=int, default=128, required=False, help="upper bound on the size of the model (for unreal this specifies size of env model)", ) group.add_argument( "--size", metavar="size", type=int, default=0, required=False, help="search the model of this size (for unreal this specifies size of env model)", ) parser.add_argument("--incr", action="store_true", required=False, default=False, help="use incremental solving") parser.add_argument("--tmp", action="store_true", required=False, default=False, help="keep temporary smt2 files") parser.add_argument("--dot", metavar="dot", type=str, required=False, help="write the output into a dot graph file") parser.add_argument("--log", metavar="log", type=str, required=False, default=None, help="name of the log file") parser.add_argument( "--unreal", action="store_true", required=False, help="simple check of unrealizability: " "invert the spec, system type, (in/out)puts, " "and synthesize the model for env " "(a more sophisticated check could search for env that disproves systems of given size)" "(note that the inverted spec will NOT be strengthened)", ) parser.add_argument("-v", "--verbose", action="count", default=0) args = parser.parse_args() setup_logging(args.verbose, args.log) logging.info(args) if args.incr and args.tmp: logging.warning( "--tmp --incr: incremental queries do not produce smt2 files, " "so I won't save any temporal files." ) with tempfile.NamedTemporaryFile(dir="./") as smt_file: smt_files_prefix = smt_file.name ltl3ba, solver_factory = create_spec_converter_z3(UFLRA(), args.incr, False, smt_files_prefix, not args.tmp) if args.size == 0: min_size, max_size = 1, args.bound else: min_size, max_size = args.size, args.size ltl_text, part_text = readfile(args.spec), readfile(args.spec.replace(".ltl", ".part")) if not args.unreal: model = check_real(ltl_text, part_text, args.moore, ltl3ba, solver_factory, min_size, max_size) else: model = check_unreal(ltl_text, part_text, args.moore, ltl3ba, solver_factory, min_size, max_size) logging.info( "{status} model for {who}".format(status=("FOUND", "NOT FOUND")[model is None], who=("sys", "env")[args.unreal]) ) if model: dot_model_str = lts_to_dot(model, ARG_MODEL_STATE, (not args.moore) ^ args.unreal) if args.dot: with open(args.dot, "w") as out: out.write(dot_model_str) logging.info( "{model_type} model is written to {file}".format( model_type=["Mealy", "Moore"][args.moore], file=out.name ) ) else: logging.info(dot_model_str) solver_factory.down_solvers() return UNKNOWN if model is None else (REALIZABLE, UNREALIZABLE)[args.unreal]
parser.add_argument('--maxsize', metavar='maxsize', type=int, default=4, required=False, help='stop at this size') parser.add_argument('-v', '--verbose', action='count', default=0) args = parser.parse_args() assert args.minsize <= args.maxsize logger = setup_logging(args.verbose) logger.info(args) with tempfile.NamedTemporaryFile(dir='./') as smt_file: smt_files_prefix = smt_file.name ltl_to_automaton = translator_via_spot.LTLToAtmViaSpot() solver_factory = Z3SolverFactory(smt_files_prefix, Z3_PATH, # we don't really need this False, True, True) elli.check_real(readfile(args.spec), readfile(args.spec.replace('.ltl', '.part')), args.moore, ltl_to_automaton, solver_factory.create(), 0, args.minsize, args.maxsize) solver_factory.down_solvers() exit(0)
help='assume a Mealy model') parser.add_argument('--minsize', metavar='minsize', type=int, default=1, required=False, help='start from size') parser.add_argument('--maxsize', metavar='maxsize', type=int, default=4, required=False, help='stop at this size') parser.add_argument('-v', '--verbose', action='count', default=0) args = parser.parse_args() assert args.minsize <= args.maxsize logger = setup_logging(args.verbose) logger.info(args) with tempfile.NamedTemporaryFile(dir='./') as smt_file: smt_files_prefix = smt_file.name ltl3ba, solver_factory = create_spec_converter_z3(UFLRA(), False, True, smt_files_prefix, True) elli.check_real(readfile(args.spec), readfile(args.spec.replace('.ltl', '.part')), args.moore, ltl3ba, solver_factory, args.minsize, args.maxsize) solver_factory.down_solvers() exit(0)