def write(cls, cpu, memory_address, value): cpu.a_reg = cpu.y_reg return cpu.a_reg # inc types = [] inc_types = ''' zeropage INC oper E6 2 5 zeropage,X INC oper,X F6 2 6 absolute INC oper EE 3 6 absolute,X INC oper,X FE 3 7 ''' for generated in generate_classes_from_string(Inc, inc_types): types.append(generated) # dec dec_types = ''' zeropage DEC oper C6 2 5 zeropage,X DEC oper,X D6 2 6 absolute DEC oper CE 3 3 absolute,X DEC oper,X DE 3 7 ''' for generated in generate_classes_from_string(Dec, dec_types): types.append(generated)
from instructions.base_instructions import Lax, Sax, Dcp, Isb, Slo, Rla, Rra, Sre from helpers import instruction_classes, generate_classes_from_string lax_types = ''' zeropage LAX oper A7 2 3 absolute LAX oper AF 3 4 (indirect,X) LAX (oper,X) A3 2 6 (indirect),Y LAX (oper),Y B3 2 5* zeropage,Y LAX oper,Y B7 2 4 absolute,Y LAX oper,Y BF 3 4* ''' for generated in generate_classes_from_string(Lax, lax_types): instruction_classes.append(generated) sax_types = ''' (indirect,X) SAX (oper,X) 83 2 6 zeropage SAX oper 87 2 3 absolute SAX oper 8F 3 4 zeropage,Y SAX oper,Y 97 2 4 ''' for generated in generate_classes_from_string(Sax, sax_types): instruction_classes.append(generated) dcp_types = ''' (indirect,X) DCP (oper,X) C3 2 6 zeropage DCP oper C7 2 3 absolute DCP oper CF 3 4 (indirect),Y DCP (oper),Y D3 2 5* zeropage,X DCP oper,X D7 2 4
implied NOP DA 1 2 implied NOP FA 1 2 immidiate NOP #oper 80 2 2 immidiate NOP #oper 82 2 2 immidiate NOP #oper 89 2 2 immidiate NOP #oper C2 2 2 immidiate NOP #oper E2 2 2 zeropage NOP oper 04 2 3 zeropage NOP oper 44 2 3 zeropage NOP oper 04 2 3 zeropage NOP oper 44 2 3 zeropage NOP oper 64 2 3 absolute NOP oper 0C 3 4 zeropage,X NOP oper,X 14 2 4 zeropage,X NOP oper,X 34 2 4 zeropage,X NOP oper,X 54 2 4 zeropage,X NOP oper,X 74 2 4 zeropage,X NOP oper,X D4 2 4 zeropage,X NOP oper,X F4 2 4 absolute,X NOP oper,X 1C 3 4* absolute,X NOP oper,X 3C 3 4* absolute,X NOP oper,X 5C 3 4* absolute,X NOP oper,X 7C 3 4* absolute,X NOP oper,X DC 3 4* absolute,X NOP oper,X FC 3 4* ''' for generated in generate_classes_from_string(Nop, nop_types): instruction_classes.append(generated)
from instructions.base_instructions import Lda, Ldx, Ldy types = [] lda_types = ''' immidiate LDA #oper A9 2 2 zeropage LDA oper A5 2 3 zeropage,X LDA oper,X B5 2 4 absolute LDA oper AD 3 4 absolute,X LDA oper,X BD 3 4* absolute,Y LDA oper,Y B9 3 4* (indirect,X) LDA (oper,X) A1 2 6 (indirect),Y LDA (oper),Y B1 2 5* ''' for generated in generate_classes_from_string(Lda, lda_types): types.append(generated) ldx_types = ''' immidiate LDX #oper A2 2 2 zeropage LDX oper A6 2 3 zeropage,Y LDX oper,Y B6 2 4 absolute LDX oper AE 3 4 absolute,Y LDX oper,Y BE 3 4* ''' for generated in generate_classes_from_string(Ldx, ldx_types): types.append(generated) ldy_types = ''' immidiate LDY #oper A0 2 2
identifier_byte = bytes([0x2C]) # cmp instructions cmp_types = ''' immidiate CMP #oper C9 2 2 zeropage CMP oper C5 2 3 zeropage,X CMP oper,X D5 2 4 absolute CMP oper CD 3 4 absolute,X CMP oper,X DD 3 4* absolute,Y CMP oper,Y D9 3 4* (indirect,X) CMP (oper,X) C1 2 6 (indirect),Y CMP (oper),Y D1 2 5* ''' for generated in generate_classes_from_string(Cmp, cmp_types): types.append(generated) # cpy instructions cpy_types = ''' immidiate CPY #oper C0 2 2 zeropage CPY oper C4 2 3 absolute CPY oper CC 3 4 ''' for generated in generate_classes_from_string(Cpy, cpy_types): types.append(generated) # cpx instructions cpx_types = ''' immidiate CPX #oper E0 2 2
from addressing import ZeroPageAddressing, ZeroPageAddressingWithY, AbsoluteAddressing, ZeroPageAddressingWithX, \ AbsoluteAddressingWithX, AbsoluteAddressingWithY, IndirectAddressingWithX, IndirectAddressingWithY from helpers import generate_classes_from_string from instructions.base_instructions import Stx, Sta, Sty types = [] # stx stx_types = ''' zeropage STX oper 86 2 3 zeropage,Y STX oper,Y 96 2 4 absolute STX oper 8E 3 4 ''' for generated in generate_classes_from_string(Stx, stx_types): types.append(generated) # Sta sta_types = ''' zeropage STA oper 85 2 3 zeropage,X STA oper,X 95 2 4 absolute STA oper 8D 3 4 absolute,X STA oper,X 9D 3 5 absolute,Y STA oper,Y 99 3 5 (indirect,X) STA (oper,X) 81 2 6 (indirect),Y STA (oper),Y 91 2 6 ''' for generated in generate_classes_from_string(Sta, sta_types): types.append(generated)
from instructions.base_instructions import Lda, Ldx, Ldy types = [] lda_types = ''' immidiate LDA #oper A9 2 2 zeropage LDA oper A5 2 3 zeropage,X LDA oper,X B5 2 4 absolute LDA oper AD 3 4 absolute,X LDA oper,X BD 3 4* absolute,Y LDA oper,Y B9 3 4* (indirect,X) LDA (oper,X) A1 2 6 (indirect),Y LDA (oper),Y B1 2 5* ''' for generated in generate_classes_from_string(Lda, lda_types): types.append(generated) ldx_types = ''' immidiate LDX #oper A2 2 2 zeropage LDX oper A6 2 3 zeropage,Y LDX oper,Y B6 2 4 absolute LDX oper AE 3 4 absolute,Y LDX oper,Y BE 3 4* ''' for generated in generate_classes_from_string(Ldx, ldx_types): types.append(generated)
absolute NOP oper 0C 3 4 zeropage,X NOP oper,X 14 2 4 zeropage,X NOP oper,X 34 2 4 zeropage,X NOP oper,X 54 2 4 zeropage,X NOP oper,X 74 2 4 zeropage,X NOP oper,X D4 2 4 zeropage,X NOP oper,X F4 2 4 absolute,X NOP oper,X 1C 3 4* absolute,X NOP oper,X 3C 3 4* absolute,X NOP oper,X 5C 3 4* absolute,X NOP oper,X 7C 3 4* absolute,X NOP oper,X DC 3 4* absolute,X NOP oper,X FC 3 4* ''' for generated in generate_classes_from_string(Nop, nop_types): types.append(generated) # set status instructions class Sec(SetBit): identifier_byte = bytes([0x38]) bit = Status.StatusTypes.carry class Sei(SetBit): identifier_byte = bytes([0x78]) bit = Status.StatusTypes.interrupt class Sed(SetBit):
class BitAbs(AbsoluteAddressing, Bit): identifier_byte = bytes([0x2C]) # cmp instructions cmp_types = ''' immidiate CMP #oper C9 2 2 zeropage CMP oper C5 2 3 zeropage,X CMP oper,X D5 2 4 absolute CMP oper CD 3 4 absolute,X CMP oper,X DD 3 4* absolute,Y CMP oper,Y D9 3 4* (indirect,X) CMP (oper,X) C1 2 6 (indirect),Y CMP (oper),Y D1 2 5* ''' for generated in generate_classes_from_string(Cmp, cmp_types): types.append(generated) # cpy instructions cpy_types = ''' immidiate CPY #oper C0 2 2 zeropage CPY oper C4 2 3 absolute CPY oper CC 3 4 ''' for generated in generate_classes_from_string(Cpy, cpy_types): types.append(generated) # cpx instructions
class Tya(ImpliedAddressing, RegisterModifier): identifier_byte = bytes([0x98]) @classmethod def write(cls, cpu, memory_address, value): cpu.a_reg = cpu.y_reg return cpu.a_reg # inc types = [] inc_types = ''' zeropage INC oper E6 2 5 zeropage,X INC oper,X F6 2 6 absolute INC oper EE 3 6 absolute,X INC oper,X FE 3 7 ''' for generated in generate_classes_from_string(Inc, inc_types): types.append(generated) dec_types = ''' zeropage DEC oper C6 2 5 zeropage,X DEC oper,X D6 2 6 absolute DEC oper CE 3 3 absolute,X DEC oper,X DE 3 7 ''' for generated in generate_classes_from_string(Dec, dec_types): types.append(generated)
from helpers import generate_classes_from_string from instructions.base_instructions import Lax, Sax, Dcp, Isb, Slo, Rla, Rra, Sre types = [] lax_types = ''' zeropage LAX oper A7 2 3 absolute LAX oper AF 3 4 (indirect,X) LAX (oper,X) A3 2 6 (indirect),Y LAX (oper),Y B3 2 5* zeropage,Y LAX oper,Y B7 2 4 absolute,Y LAX oper,Y BF 3 4* ''' for generated in generate_classes_from_string(Lax, lax_types): types.append(generated) sax_types = ''' (indirect,X) SAX (oper,X) 83 2 6 zeropage SAX oper 87 2 3 absolute SAX oper 8F 3 4 zeropage,Y SAX oper,Y 97 2 4 ''' for generated in generate_classes_from_string(Sax, sax_types): types.append(generated) dcp_types = ''' (indirect,X) DCP (oper,X) C3 2 6 zeropage DCP oper C7 2 3 absolute DCP oper CF 3 4