def _getitem__val_slice(self, key):
updateTime = max(self.updateTime, key.updateTime)
assert key._isFullVld()
size = key._size()
firstBitNo = key.val[1].val
val = selectBitRange(self.val, firstBitNo, size)
vld = selectBitRange(self.vldMask, firstBitNo, size)
retT = self._dtype.__class__(size, signed=self._dtype.signed)
return self.__class__(val, retT, vld, updateTime=updateTime)
def getBits(self, start, end):
"""
Gets value of bits between selected range from memory
:param start: bit address of start of bit of bits
:param end: bit address of first bit behind bits
:return: instance of BitsVal (derived from SimBits type) which contains copy of selected bits
"""
wordWidth = self.cellSize * 8
inFieldOffset = 0
allMask = mask(wordWidth)
value = simBitsT(end - start, None).fromPy(None)
while start != end:
assert start < end, (start, end)
dataWordIndex = start // wordWidth
v = self.data.get(dataWordIndex, None)
endOfWord = (dataWordIndex + 1) * wordWidth
width = min(end, endOfWord) - start
offset = start % wordWidth
if v is None:
val = 0
vldMask = 0
updateTime = -1
elif isinstance(v, int):
val = selectBitRange(v, offset, width)
vldMask = allMask
updateTime = -1
else:
val = selectBitRange(v.val, offset, width)
vldMask = selectBitRange(v.vldMask, offset, width)
updateTime = v.updateTime
m = mask(width)
value.val |= (val & m) << inFieldOffset
value.vldMask |= (vldMask & m) << inFieldOffset
value.updateMask = max(value.updateTime, updateTime)
inFieldOffset += width
start += width
return value
def getBits_from_array(array,
wordWidth,
start,
end,
reinterpretElmToType=None):
"""
Gets value of bits between selected range from memory
:param start: bit address of start of bit of bits
:param end: bit address of first bit behind bits
:return: instance of BitsVal (derived from SimBits type) which contains
copy of selected bits
"""
inPartOffset = 0
value = Bits(end - start, None).fromPy(None)
while start != end:
assert start < end, (start, end)
dataWordIndex = start // wordWidth
v = array[dataWordIndex]
if reinterpretElmToType is not None:
v = v._reinterpret_cast(reinterpretElmToType)
endOfWord = (dataWordIndex + 1) * wordWidth
width = min(end, endOfWord) - start
offset = start % wordWidth
val = selectBitRange(v.val, offset, width)
vldMask = selectBitRange(v.vldMask, offset, width)
updateTime = v.updateTime
m = mask(width)
value.val |= (val & m) << inPartOffset
value.vldMask |= (vldMask & m) << inPartOffset
value.updateMask = max(value.updateTime, updateTime)
inPartOffset += width
start += width
return value
def _getitem__val(self, key):
updateTime = max(self.updateTime, key.updateTime)
keyVld = key._isFullVld()
val = 0
vld = 0
if isinstance(key._dtype, Integer):
if keyVld:
val = selectBit(self.val, key.val)
vld = selectBit(self.vldMask, key.val)
return BitsVal(val, BIT, vld, updateTime=updateTime)
elif key._dtype == SLICE:
if keyVld:
firstBitNo = key.val[1].val
size = key._size()
val = selectBitRange(self.val, firstBitNo, size)
vld = selectBitRange(self.vldMask, firstBitNo, size)
retT = vecT(size, signed=self._dtype.signed)
return BitsVal(val, retT, vld, updateTime=updateTime)
else:
raise TypeError(key)
def _impl(self) -> None:
if len(self._masters) > 1:
raise NotImplementedError()
m_offset, _ = self._masters[0]
if m_offset != 0:
raise NotImplementedError()
m = self.s[0]
err = hBit(0)
rdack = hBit(0)
wrack = hBit(0)
AW = int(self.ADDR_WIDTH)
wdata = []
for i, (s, (s_offset, s_size, _)) in enumerate(zip(self.m, self._slaves)):
connect(m.bus2ip_addr, s.bus2ip_addr, fit=True)
s.bus2ip_be(m.bus2ip_be)
s.bus2ip_rnw(m.bus2ip_rnw)
s.bus2ip_data(m.bus2ip_data)
bitsOfSubAddr = int(log2ceil(s_size - 1))
prefix = selectBitRange(
s_offset, bitsOfSubAddr, AW - bitsOfSubAddr)
cs = self._sig("m_cs_%d" % i)
cs(m.bus2ip_addr[AW:bitsOfSubAddr]._eq(prefix))
s.bus2ip_cs(m.bus2ip_cs & cs)
err = err | (cs & s.ip2bus_error)
rdack = rdack | (cs & s.ip2bus_rdack)
wrack = wrack | (cs & s.ip2bus_wrack)
wdata.append((cs, s.ip2bus_data))
m.ip2bus_error(err)
m.ip2bus_rdack(rdack)
m.ip2bus_wrack(wrack)
SwitchLogic(
[(sel, m.ip2bus_data(data)) for sel, data in wdata],
default=m.ip2bus_data(None)
)
def _impl(self) -> None:
if len(self._masters) > 1:
raise NotImplementedError()
m_offset, _ = self._masters[0]
if m_offset != 0:
raise NotImplementedError()
m = self.s[0]
err = hBit(0)
rdack = hBit(0)
wrack = hBit(0)
AW = int(self.ADDR_WIDTH)
wdata = []
for i, (s, (s_offset, s_size,
_)) in enumerate(zip(self.m, self._slaves)):
connect(m.bus2ip_addr, s.bus2ip_addr, fit=True)
s.bus2ip_be(m.bus2ip_be)
s.bus2ip_rnw(m.bus2ip_rnw)
s.bus2ip_data(m.bus2ip_data)
bitsOfSubAddr = int(log2ceil(s_size - 1))
prefix = selectBitRange(s_offset, bitsOfSubAddr,
AW - bitsOfSubAddr)
cs = self._sig("m_cs_%d" % i)
cs(m.bus2ip_addr[AW:bitsOfSubAddr]._eq(prefix))
s.bus2ip_cs(m.bus2ip_cs & cs)
err = err | (cs & s.ip2bus_error)
rdack = rdack | (cs & s.ip2bus_rdack)
wrack = wrack | (cs & s.ip2bus_wrack)
wdata.append((cs, s.ip2bus_data))
m.ip2bus_error(err)
m.ip2bus_rdack(rdack)
m.ip2bus_wrack(wrack)
SwitchLogic([(sel, m.ip2bus_data(data)) for sel, data in wdata],
default=m.ip2bus_data(None))
def packData(self, data):
"""
Pack data into list of BitsVal of specified dataWidth
:param data: dict of values for struct fields {fieldName: value}
:return: list of BitsVal which are representing values of words
"""
typeOfWord = simBitsT(self.wordWidth, None)
fieldToVal = self._fieldToTPart
if fieldToVal is None:
fieldToVal = self._fieldToTPart = self.fieldToDataDict(
self.origin.dtype, data, {})
for _, transParts in self.walkWords(showPadding=True):
actualVldMask = 0
actualVal = 0
for tPart in transParts:
high, low = tPart.getBusWordBitRange()
fhigh, flow = tPart.getFieldBitRange()
if not tPart.isPadding:
val = fieldToVal.get(tPart.tmpl.origin, None)
else:
val = None
if val is None:
newBits = 0
vld = 0
else:
newBits = selectBitRange(val, flow, fhigh - flow)
vld = mask(high - low) << low
actualVal = setBitRange(actualVal, low, high - low, newBits)
actualVldMask = setBitRange(actualVal, low, high - low, vld)
yield typeOfWord.getValueCls()(actualVal, typeOfWord,
actualVldMask, -1)