def _impl(self):
propagateClkRstn(self)
self.regsConventor.bus(self.cntrlBus)
axi = self.axi
# disable read channel
c(0, *where(axi.ar._interfaces, lambda x: x is not axi.ar.ready))
axi.r.ready(0)
axi.b.ready(1) # we do ignore write confirmations
st_t = HEnum("state_type", ["fullIdle", "writeAddr", "writeData",
"writeDataLast"])
onoff = self._reg("on_off_reg", defVal=0)
baseAddr = self._reg("baseAddr_reg", Bits(self.ADDR_WIDTH), 0)
st = self._reg("state_reg", st_t, st_t.fullIdle)
actualAddr = self._reg("actualAddr_reg", Bits(self.ADDR_WIDTH))
lenRem = self._reg("lenRem_reg",
Bits(int(self.DATA_LEN).bit_length() + 1),
self.DATA_LEN)
actualLenRem = self._reg("actualLenRem_reg", axi.aw.len._dtype)
self.connectRegisters(st, onoff, baseAddr)
self.axiWAddrHandler(st, baseAddr, actualAddr, lenRem)
self.mainFsm(st, onoff, lenRem, actualLenRem)
self.dataWFeed(st, lenRem, actualLenRem)
def tsWaitLogic(ifNoTsRd):
return If(sd0 & sd1,
c(stT.lenExtr, st)
).Elif(sd0,
c(stT.ts1Wait, st)
).Else(
ifNoTsRd
)
def test_basicSwitch(self):
a = self.n.sig('a', dtype=INT)
b = self.n.sig('b', dtype=INT)
obj = Switch(a).addCases([(i, c(i, b)) for i in range(4)])
cont, io_change = obj._try_reduce()
self.assertFalse(io_change)
self.assertEqual(len(cont), 1)
cont = cont[0]
tmpl = SwitchContainer(a, [(i, c(i, b)) for i in range(3)]
+ [(None, c(3, b))])
self.compareStructure(tmpl, cont)
def _impl_latency(self, inVld, inRd, inData, outVld, outRd, prefix):
isOccupied = self._reg(prefix + "isOccupied", defVal=0)
regs_we = self._sig(prefix + 'reg_we')
outData = []
for iin in inData:
r = self._reg(prefix + 'reg_' + iin._name, iin._dtype)
If(regs_we,
r(iin)
)
outData.append(r)
If(isOccupied,
If(outRd & ~inVld,
isOccupied(0)
)
).Else(
If(inVld,
isOccupied(1)
)
)
If(isOccupied,
c(outRd, inRd),
outVld(1),
regs_we(inVld & outRd)
).Else(
inRd(1),
outVld(0),
regs_we(inVld)
)
return outData
def connectRegisters(self, st, onoff, baseAddr):
"""
connection of axilite registers
"""
idle = st._eq(st._dtype.fullIdle)
regs = self.regsConventor.decoded
regs.control.din(Concat(onoff, idle,
vec(0, self.DATA_WIDTH - 2)))
If(regs.control.dout.vld,
onoff(regs.control.dout.data[0])
)
c(baseAddr, regs.baseAddr.din)
If(regs.baseAddr.dout.vld,
baseAddr(regs.baseAddr.dout.data)
)
def connectRegIntfAlways(regIntf, _addr):
return (
c(bus.din, regIntf.dout.data) +
c(bus.we & bus.en & bus.addr._eq(_addr), regIntf.dout.vld)
)
def tsWaitLogic(ifNoTsRd):
return If(sd0 & sd1, c(stT.lenExtr,
st)).Elif(sd0, c(stT.ts1Wait,
st)).Else(ifNoTsRd)
def tsWaitLogic():
return If(sd0 & sd1,
c(stT.lenExtr, st)
).Else(
c(stT.ts1Wait, st)
)
def test_ifsInSwitch(self):
n = self.n
stT = HEnum('t_state', ["idle", "tsWait", "ts0Wait",
"ts1Wait", "lenExtr"])
clk = n.sig('clk')
rst = n.sig("rst")
st = n.sig('st', stT, clk=clk, syncRst=rst, defVal=stT.idle)
sd0 = n.sig('sd0')
sd1 = n.sig('sd1')
cntrlFifoVld = n.sig('ctrlFifoVld')
cntrlFifoLast = n.sig('ctrlFifoLast')
def tsWaitLogic():
return If(sd0 & sd1,
c(stT.lenExtr, st)
).Else(
c(stT.ts1Wait, st)
)
obj = Switch(st)\
.Case(stT.idle,
tsWaitLogic()
).Case(stT.tsWait,
tsWaitLogic()
).Case(stT.ts0Wait,
If(sd0,
c(stT.lenExtr, st)
).Else(
c(st, st)
)
).Case(stT.ts1Wait,
If(sd1,
c(stT.lenExtr, st)
).Else(
c(st, st)
)
).Case(stT.lenExtr,
If(cntrlFifoVld & cntrlFifoLast,
c(stT.idle, st)
).Else(
c(st, st)
)
)
cont, io_change = obj._try_reduce()
self.assertFalse(io_change)
self.assertEqual(len(cont), 1)
cont = cont[0]
tmpl = """
CASE st IS
WHEN idle =>
IF (sd0 AND sd1) = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= ts1Wait;
END IF;
WHEN tsWait =>
IF (sd0 AND sd1) = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= ts1Wait;
END IF;
WHEN ts0Wait =>
IF sd0 = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= st;
END IF;
WHEN ts1Wait =>
IF sd1 = '1' THEN
st_next <= lenExtr;
ELSE
st_next <= st;
END IF;
WHEN OTHERS =>
IF (ctrlFifoVld AND ctrlFifoLast) = '1' THEN
st_next <= idle;
ELSE
st_next <= st;
END IF;
END CASE
"""
self.strStructureCmp(cont, tmpl)
