def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.m_axi = self._axiCls()._m()
with self._paramsShared(prefix="CNTRL_"):
self.cntrl = self._cntrlCls()
self._add_ep()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
# interface which sending requests to download data
# and interface which is collecting all data and only data with specified id are processed
self.rDatapump = AxiRDatapumpIntf()._m()
self.rDatapump.MAX_BYTES = self.BUFFER_CAPACITY // 2 * self.DATA_WIDTH // 8
self.dataOut = Handshaked()._m()
# (how much of items remains in block)
self.inBlockRemain = VectSignal(log2ceil(self.ITEMS_IN_BLOCK + 1))._m()
# interface to control internal register
a = self.baseAddr = RegCntrl()
a.DATA_WIDTH = self.ADDR_WIDTH
self.rdPtr = RegCntrl()
self.wrPtr = RegCntrl()
for ptr in [self.rdPtr, self.wrPtr]:
ptr.DATA_WIDTH = self.PTR_WIDTH
f = self.dataFifo = HandshakedFifo(Handshaked)
f.EXPORT_SIZE = True
f.DATA_WIDTH = self.DATA_WIDTH
f.DEPTH = self.BUFFER_CAPACITY
def _declr(self):
addClkRstn(self)
# addr of start of array
self.base = VectSignal(self.ADDR_WIDTH)
# input index of item to get
self.index = Handshaked()
self.index.DATA_WIDTH.set(log2ceil(self.ITEMS))
# output item from array
self.item = Handshaked()._m()
self.item.DATA_WIDTH.set(self.ITEM_WIDTH)
self.ITEMS_IN_DATA_WORD = int(self.DATA_WIDTH) // int(self.ITEM_WIDTH)
with self._paramsShared():
# interface for communication with datapump
self.rDatapump = AxiRDatapumpIntf()._m()
self.rDatapump.MAX_LEN.set(1)
if self.ITEMS_IN_DATA_WORD > 1:
assert isPow2(self.ITEMS_IN_DATA_WORD)
f = self.itemSubIndexFifo = HandshakedFifo(Handshaked)
f.DATA_WIDTH.set(log2ceil(self.ITEMS_IN_DATA_WORD))
f.DEPTH.set(self.MAX_TRANS_OVERLAP)
def _declr(self):
if self.ID_WIDTH:
raise NotImplementedError(self.ID_WIDTH)
if self.DEST_WIDTH:
raise NotImplementedError(self.DEST_WIDTH)
addClkRstn(self)
t = self._structT
if isinstance(t, HStruct):
intfCls = StructIntf
elif isinstance(t, HUnion):
intfCls = UnionSource
else:
raise TypeError(t)
# input stream
with self._paramsShared():
self.dataIn = self.intfCls()
if self.SHARED_READY:
self.dataOut_ready = Signal()
# parsed data
if is_only_padding(t):
self.dataOut = None
else:
self.dataOut = intfCls(t, tuple(), self._mkFieldIntf)._m()
self.parseTemplate()
if self.OVERFLOW_SUPPORT:
# flag which is 1 if we are behind the data which
# we described by type in configuration
# :note: if the data is unaligned this may be 1 in last parsed word
# as well
self.parsing_overflow = Signal()._m()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
# read interface for datapump
# interface which sending requests to download addr of next block
self.rDatapump = AxiRDatapumpIntf()._m()
# because we are downloading only addres of next block
self.rDatapump.MAX_LEN = 1
# write interface for datapump
self.wDatapump = AxiWDatapumpIntf()._m()
self.wDatapump.MAX_LEN = self.BUFFER_CAPACITY // 2
assert self.BUFFER_CAPACITY <= self.ITEMS_IN_BLOCK
# interface for items which should be written into list
self.dataIn = Handshaked()
# interface to control internal register
a = self.baseAddr = RegCntrl()
a.DATA_WIDTH = self.ADDR_WIDTH
self.rdPtr = RegCntrl()
self.wrPtr = RegCntrl()
for ptr in [self.rdPtr, self.wrPtr]:
ptr.DATA_WIDTH = self.PTR_WIDTH
f = self.dataFifo = HandshakedFifo(Handshaked)
f.EXPORT_SIZE = True
f.DATA_WIDTH = self.DATA_WIDTH
f.DEPTH = self.BUFFER_CAPACITY
self.ALIGN_BITS = log2ceil(self.DATA_WIDTH // 8)
def _declr(self):
with self._paramsShared():
addClkRstn(self)
self.first = RegCntrl()
self.second = RegCntrl()
self.select_sig = Signal()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.a0 = VldSynced()
self.a1 = VldSynced()
self.a2 = VldSynced()
self.b = HObjList(VldSynced() for _ in range(int(self.LEN)))._m()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.a = HObjList(VldSynced() for _ in range(self.LEN))
self.b0 = VldSynced()._m()
self.b1 = VldSynced()._m()
self.b2 = VldSynced()._m()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.subunit0 = SimpleUnitAxiStream()
self.a0 = AxiStream()
self.b0 = AxiStream()._m()
def _declr(self):
addClkRstn(self)
self.dataIn = self.intfCls()
self._inIntfConfigFn(self.dataIn)
self.dataOut = self.intfCls()._m()
self._outIntfConfigFn(self.dataOut)
def _declr(self):
self._compute_constants()
addClkRstn(self)
# used to initialize the LRU data (in the case of cache reset)
# while set port is active all other ports are blocked
s = self.set = AddrDataHs()
s.ADDR_WIDTH = self.INDEX_W
s.DATA_WIDTH = self.LRU_WIDTH
# used to increment the LRU data in the case of hit
self.incr = HObjList(IndexWayHs() for _ in range(self.INCR_PORT_CNT))
for i in self.incr:
i.INDEX_WIDTH = self.INDEX_W
i.WAY_CNT = self.WAY_CNT
# get a victim for a selected cacheline index
# The cacheline returned as a victim is also marked as used just now
vr = self.victim_req = AddrHs()
vr.ADDR_WIDTH = self.INDEX_W
vr.ID_WIDTH = 0
vd = self.victim_data = Handshaked()._m()
vd.DATA_WIDTH = log2ceil(self.WAY_CNT - 1)
m = self.lru_mem = RamXorSingleClock()
m.ADDR_WIDTH = self.INDEX_W
m.DATA_WIDTH = self.LRU_WIDTH
m.PORT_CNT = (
# victim_req preload, victim_req write back or set,
READ, WRITE,
# incr preload, incr write back...
*flatten((READ, WRITE) for _ in range(self.INCR_PORT_CNT))
)
def _declr(self):
with self._paramsShared():
addClkRstn(self)
self.doIncr = Signal()
self.doFlip = HandshakeSync()
self.data = RegCntrl()
self.cntr = FlipRegister()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.s = Axi4Lite()
self.toMi32 = Axi4Lite_to_Mi32()
self.toAxi = Mi32_to_Axi4Lite()
self.m = Axi4Lite()._m()
def _declr(self):
addClkRstn(self)
self.a = Handshaked()
self.a_0 = Handshaked()._m()
self.a_1 = Handshaked()._m()
self.a_2 = Handshaked()._m()
self.b = Handshaked()
self.b_0 = Handshaked()._m()
self.b_1 = Handshaked()._m()
self.b_2 = Handshaked()._m()
self.b_selected = Handshaked()._m()
self.b_selected.DATA_WIDTH.set(3)
self.c = Handshaked()
self.c_0 = Handshaked()._m()
self.c_1 = Handshaked()._m()
self.d = Handshaked()
self.d_0 = Handshaked()._m()
self.d_1 = Handshaked()._m()
self.d_2 = Handshaked()._m()
self.e = Handshaked()
self.e_0 = Handshaked()._m()
self.e_1 = Handshaked()._m()
self.e_2 = Handshaked()._m()
self.e_select = Handshaked()
self.e_select.DATA_WIDTH.set(3)
def _declr(self):
if self.USE_STRB:
raise NotImplementedError(self.USE_STRB)
if self.USE_KEEP:
raise NotImplementedError(self.USE_KEEP)
if self.ID_WIDTH:
raise NotImplementedError(self.ID_WIDTH)
if self.DEST_WIDTH:
raise NotImplementedError(self.DEST_WIDTH)
addClkRstn(self)
if isinstance(self._structT, HStruct):
intfCls = StructIntf
elif isinstance(self._structT, HUnion):
intfCls = UnionSource
else:
raise TypeError(self._structT)
self.dataOut = intfCls(self._structT, self._mkFieldIntf)._m()
with self._paramsShared():
self.dataIn = self.intfCls()
if self.SHARED_READY:
self.dataOut_ready = Signal()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
# interface which sending requests to download data
# and interface which is collecting all data and only data with specified id are processed
self.rDatapump = AxiRDatapumpIntf()._m()
self.rDatapump.MAX_LEN.set(self.BUFFER_CAPACITY // 2 - 1)
self.dataOut = Handshaked()._m()
# (how much of items remains in block)
self.inBlockRemain = VectSignal(log2ceil(self.ITEMS_IN_BLOCK + 1))._m()
# interface to control internal register
a = self.baseAddr = RegCntrl()
a._replaceParam(a.DATA_WIDTH, self.ADDR_WIDTH)
self.rdPtr = RegCntrl()
self.wrPtr = RegCntrl()
for ptr in [self.rdPtr, self.wrPtr]:
ptr._replaceParam(ptr.DATA_WIDTH, self.PTR_WIDTH)
f = self.dataFifo = HandshakedFifo(Handshaked)
f.EXPORT_SIZE.set(True)
f.DATA_WIDTH.set(self.DATA_WIDTH)
f.DEPTH.set(self.BUFFER_CAPACITY)
def _declr(self) -> None:
self._normalize_config()
addClkRstn(self)
slavePorts = HObjList()
for _ in self.MASTERS:
s = Mi32()
s._updateParamsFrom(self)
slavePorts.append(s)
self.s = slavePorts
masterPorts = HObjList()
for _, size in self.SLAVES:
m = Mi32()._m()
m.ADDR_WIDTH = log2ceil(size - 1)
m.DATA_WIDTH = self.DATA_WIDTH
masterPorts.append(m)
self.m = masterPorts
# fifo which keeps index of slave for master read transaction
# so the interconnect can delivery the read data to master
# which asked for it
f = self.r_data_order = HandshakedFifo(Handshaked)
f.DEPTH = self.MAX_TRANS_OVERLAP
f.DATA_WIDTH = log2ceil(len(self.SLAVES))
def _declr(self):
addClkRstn(self)
self.clk.FREQ = self.FREQ
with self._paramsShared(prefix="LCD_"):
self.dataOut = Hd44780Intf()._m()
self.dataIn = Handshaked()
self.dataIn.DATA_WIDTH = 8
def _declr(self):
addClkRstn(self)
self.a = Handshaked()
self.a_0 = Handshaked()._m()
self.a_1 = Handshaked()._m()
self.a_2 = Handshaked()._m()
self.b = Handshaked()
self.b_0 = Handshaked()._m()
self.b_1 = Handshaked()._m()
self.b_2 = Handshaked()._m()
self.b_selected = Handshaked()._m()
self.b_selected.DATA_WIDTH = 3
self.c = Handshaked()
self.c_0 = Handshaked()._m()
self.c_1 = Handshaked()._m()
self.d = Handshaked()
self.d_0 = Handshaked()._m()
self.d_1 = Handshaked()._m()
self.d_2 = Handshaked()._m()
self.e = Handshaked()
self.e_0 = Handshaked()._m()
self.e_1 = Handshaked()._m()
self.e_2 = Handshaked()._m()
self.e_select = Handshaked()
self.e_select.DATA_WIDTH = 3
def _declr(self):
addClkRstn(self)
self.input = VectSignal(self.DATAIN_WIDTH, signed=True)
self.output = VectSignal(self.DATAIN_WIDTH, signed=True)._m()
self.target = VectSignal(self.DATAIN_WIDTH, signed=True)
self.coefs = HObjList(
VectSignal(self.COEF_WIDTH, signed=True) for _ in range(4))
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.a0 = VldSynced()
self.a1 = VldSynced()
self.a2 = VldSynced()
self.b = HObjList(VldSynced() for _ in range(int(self.LEN)))._m()
def _declr(self):
with self._paramsShared():
addClkRstn(self)
self.first = RegCntrl()
self.second = RegCntrl()
self.select_sig = Signal()
def _declr(self):
assert self.CACHE_LINE_CNT > 0, self.CACHE_LINE_CNT
assert self.WAY_CNT > 0, self.WAY_CNT
assert self.CACHE_LINE_CNT % self.WAY_CNT == 0, (self.CACHE_LINE_CNT,
self.WAY_CNT)
self._compupte_tag_index_offset_widths()
addClkRstn(self)
with self._paramsShared():
self.s = Axi4()
self.m = Axi4()._m()
rc = self.read_cancel = AddrHs()._m()
rc.ID_WIDTH = 0
self.tag_array = AxiCacheTagArray()
self.lru_array = AxiCacheLruArray()
for a in [self.tag_array, self.lru_array]:
a.PORT_CNT = 2 # r+w
# self.flush = HandshakeSync()
# self.init = HandshakeSync()
data_array = self.data_array = RamSingleClock()
data_array.MAX_BLOCK_DATA_WIDTH = self.MAX_BLOCK_DATA_WIDTH
data_array.DATA_WIDTH = self.DATA_WIDTH
data_array.ADDR_WIDTH = log2ceil(
self.CACHE_LINE_CNT *
ceil(self.CACHE_LINE_SIZE * 8 / self.DATA_WIDTH))
data_array.PORT_CNT = (READ, WRITE)
data_array.HAS_BE = True
def _declr(self):
addClkRstn(self)
with self._paramsShared():
# read interface for datapump
# interface which sending requests to download addr of next block
self.rDatapump = AxiRDatapumpIntf()._m()
self.rDatapump.MAX_LEN.set(1) # because we are downloading only addres of next block
# write interface for datapump
self.wDatapump = AxiWDatapumpIntf()._m()
self.wDatapump.MAX_LEN.set(self.BUFFER_CAPACITY // 2)
assert self.BUFFER_CAPACITY <= self.ITEMS_IN_BLOCK
# interface for items which should be written into list
self.dataIn = Handshaked()
# interface to control internal register
a = self.baseAddr = RegCntrl()
a._replaceParam(a.DATA_WIDTH, self.ADDR_WIDTH)
self.rdPtr = RegCntrl()
self.wrPtr = RegCntrl()
for ptr in [self.rdPtr, self.wrPtr]:
ptr._replaceParam(ptr.DATA_WIDTH, self.PTR_WIDTH)
f = self.dataFifo = HandshakedFifo(Handshaked)
f.EXPORT_SIZE.set(True)
f.DATA_WIDTH.set(self.DATA_WIDTH)
f.DEPTH.set(self.BUFFER_CAPACITY)
self.ALIGN_BITS = log2ceil(self.DATA_WIDTH // 8).val
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.dataIn = AxiStream()
self.conv0 = AxiSToLocalLink()
self.conv1 = LocalLinkToAxiS()
self.dataOut = AxiStream()._m()
def _declr(self):
addClkRstn(self)
self.dataOut = VldSynced()._m()
self.dataOut.DATA_WIDTH.set(8)
self.rxd = Signal()
def _declr(self):
addClkRstn(self)
self.a = VectSignal(8)
self.b = VectSignal(8)._m()
self.c = VectSignal(8)
self.d = VectSignal(8)._m()
def _declr(self):
addClkRstn(self)
self.dataOut = VldSynced()._m()
self.dataOut.DATA_WIDTH.set(8)
self.rxd = Signal()
def _declr(self):
addClkRstn(self)
self.dataIn = self.intfCls()
self._inIntfConfigFn(self.dataIn)
self.dataOut = self.intfCls()._m()
self._outIntfConfigFn(self.dataOut)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.m_axi = self._axiCls()._m()
with self._paramsShared(prefix="CNTRL_"):
self.cntrl = self._cntrlCls()
self._add_ep()
def _declr(self):
addClkRstn(self)
BCD_DIGITS = self.BCD_DIGITS
bcd = self.din = Handshaked() # BCD data to convert
bcd.DATA_WIDTH = 4 * BCD_DIGITS
bin_ = self.dout = Handshaked()._m()
bin_.DATA_WIDTH = log2ceil(10 ** BCD_DIGITS - 1) # Converted output. Retained until next conversion
def _declr(self):
""""
Parse template and decorate with interfaces
"""
t = self._structT
s_t = _get_only_stream(t)
if s_t is None:
self.sub_t = [_t for _, _t in separate_streams(t)]
if len(self.sub_t) == 1:
# we process all the fields in this component
self.parseTemplate()
# else each child will parse it's own part
# and we join output frames together
else:
# only instantiate a component which aligns the stream
# to correct output format
self.sub_t = [
s_t,
]
addClkRstn(self)
with self._paramsShared():
self.dataOut = self.intfCls()._m()
if isinstance(self._structT, HStruct):
intfCls = StructIntf
elif isinstance(self._structT, HUnion):
intfCls = UnionSink
else:
raise TypeError(self._structT)
self.dataIn = intfCls(self._structT, tuple(), self._mkFieldIntf)
def _declr(self):
addClkRstn(self)
# addr of start of array
self.base = VectSignal(self.ADDR_WIDTH)
# input index of item to get
self.index = Handshaked()
self.index.DATA_WIDTH.set(log2ceil(self.ITEMS))
# output item from array
self.item = Handshaked()._m()
self.item.DATA_WIDTH.set(self.ITEM_WIDTH)
self.ITEMS_IN_DATA_WORD = int(self.DATA_WIDTH) // int(self.ITEM_WIDTH)
with self._paramsShared():
# interface for communication with datapump
self.rDatapump = AxiRDatapumpIntf()._m()
self.rDatapump.MAX_LEN.set(1)
if self.ITEMS_IN_DATA_WORD > 1:
assert isPow2(self.ITEMS_IN_DATA_WORD)
f = self.itemSubIndexFifo = HandshakedFifo(Handshaked)
f.DATA_WIDTH.set(log2ceil(self.ITEMS_IN_DATA_WORD))
f.DEPTH.set(self.MAX_TRANS_OVERLAP)
def _declr(self):
with self._paramsShared():
addClkRstn(self)
self.doIncr = Signal()
self.doFlip = HandshakeSync()
self.data = RegCntrl()
self.cntr = FlipRegister()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
if self.MASK_GRANULARITY is None:
self.dataIn = VldSynced()
else:
self.dataIn = DataMaskLastHs()
self.dataOut = VectSignal(self.POLY_WIDTH)._m()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.bus = self._intfCls()
self.decoded = StructIntf(
self.STRUCT_TEMPLATE, instantiateFieldFn=self._mkFieldInterface)._m()
def _declr(self):
addClkRstn(self)
self.clk_cnt_initVal = VectSignal(16)
self.i2c = I2c()._m()
self.cntrl = I2cBitCntrlCmd()
self.arbitrationLost = Signal()._m() # arbitration lost
self.dout = Signal()._m()
def _declr(self):
addClkRstn(self)
self.a = VectSignal(8)
self.b = VectSignal(11)
self.c = VectSignal(12)._m()
self.d = VectSignal(8)._m()
def _declr(self):
if self.USER_WIDTH:
raise NotImplementedError(self.USER_WIDTH)
addClkRstn(self)
with self._paramsShared():
# address channel to axi
self.a = self._axiAddrCls()._m()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.a0 = AxiStream()
self.b0 = AxiStream()._m()
self.u0 = Simple2withNonDirectIntConnection()
self.u1 = Simple2withNonDirectIntConnection()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.din = Handshaked()
self.dout = VldSynced()._m()
self.tx = UartTx()
self.rx = UartRx()
def _declr(self):
if self.USER_WIDTH:
raise NotImplementedError(self.USER_WIDTH)
addClkRstn(self)
with self._paramsShared():
# address channel to axi
self.a = self._axiAddrCls()._m()
def _declr(self):
addClkRstn(self)
self.period = VectSignal(10)
self.en = Signal()
self.rstCntr = Signal()
self.cntr0 = Signal()._m()
self.cntr1 = Signal()._m()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.match = Handshaked()
self.write = AddrDataBitMaskHs()
self.write.ADDR_WIDTH.set(log2ceil(self.ITEMS - 1))
o = self.out = VldSynced()._m()
o._replaceParam(o.DATA_WIDTH, self.ITEMS)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.din = Handshaked()
self.dout = VldSynced()._m()
self.tx = UartTx()
self.rx = UartRx()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.bus = Ipif()
self.reg = IpifReg()
self.ep = IpifEndpoint(self.STRUCT_TEMPLATE)
self.decoded = StructIntf(self.STRUCT_TEMPLATE,
self.ep._mkFieldInterface)._m()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.r = RamHsR()
self.w = AddrDataHs()
self.conv = RamAsHs()
self.ram = RamSingleClock()
def _declr(self):
addClkRstn(self)
self.cntrl = HandshakeSync()
self.COUNTER_WIDTH = log2ceil(self.ITERATIONS)
self.index = VectSignal(self.COUNTER_WIDTH)._m()
self.body = HandshakeSync()._m()
self.bodyBreak = Signal()
def _declr(self):
addClkRstn(self)
LEN = 2
with self._paramsShared():
self.a = HObjList(AxiStream() for _ in range(LEN))
self.b = HObjList(AxiStream() for _ in range(LEN))._m()
self.u0 = SimpleSubunit()
self.u1 = SimpleSubunit()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.a = AxiStream()
self.b = AxiStream()._m()
self.u0 = Simple2withNonDirectIntConnection()
self.u1 = Simple2withNonDirectIntConnection()
self.u2 = Simple2withNonDirectIntConnection()
def _declr(self):
assert self.USE_STRB
addClkRstn(self)
with self._paramsShared():
self.dataIn = AxiStream()
with self._paramsShared(exclude=[self.DATA_WIDTH]):
o = self.dataOut = AxiStream()._m()
o._replaceParam(o.DATA_WIDTH, self.OUT_DATA_WIDTH)
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.dp = Axi_wDatapump(axiAddrCls=Axi3_addr)
self.ic = WStrictOrderInterconnect()
self.aw = Axi3_addr()._m()
self.w = Axi4_w()._m()
self.b = Axi4_b()
self.drivers = HObjList(AxiWDatapumpIntf() for _ in range(int(self.DRIVER_CNT)))
def _declr(self):
addClkRstn(self)
self.myIp = Signal(dtype=ipv4_t)
with self._paramsShared(exclude={self.USE_STRB}):
self.rx = AxiStream()
with self._paramsShared():
self.tx = AxiStream()._m()
def _declr(self):
LEN = 2
addClkRstn(self)
with self._paramsShared():
self.a = HObjList(VldSynced() for _ in range(LEN))
self.b = HObjList(VldSynced() for _ in range(LEN))._m()
self.u0 = SimpleSubunit()
self.u1 = SimpleSubunit()
def _declr(self):
addClkRstn(self)
self.a_en = Signal()
self.b_en = Signal()
self.eq = Signal()._m()
self.ne = Signal()._m()
self.lt = Signal()._m()
self.gt = Signal()._m()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.din = AxiStream()
self.export = AxiStream()._m()
self.cfg = Axi4Lite()
self.hfe = HeadFieldExtractor()
self.patternMatch = PatternMatch()
self.filter = Filter()
self.exporter = Exporter()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.a = AxiStream()
self.b0 = AxiStream()._m()
self.b1 = AxiStream()._m()
self.u0 = Simple2withNonDirectIntConnection()
self.u1 = UnitWithArrIntf()
self.u2_0 = Simple2withNonDirectIntConnection()
self.u2_1 = Simple2withNonDirectIntConnection()
def _declr(self):
addClkRstn(self)
self.a = HObjList(
StructIntf(
struct0,
instantiateFieldFn=self._mkFieldInterface)
for _ in range(3))
self.b = HObjList(
StructIntf(
struct0,
instantiateFieldFn=self._mkFieldInterface)
for _ in range(3))._m()
