def _test_read(self, id_addr_tuples, randomize=False, REF_DATA=0x1000, time_multiplier=2):
u = self.u
mem = AxiSimRam(u.m)
WORD_SIZE = self.WORD_SIZE
trans_len = ceil(u.CACHE_LINE_SIZE / WORD_SIZE)
for trans_id, addr in id_addr_tuples:
for i in range(trans_len):
mem.data[addr // WORD_SIZE + i] = addr + i + REF_DATA
trans = u.s._ag.create_addr_req(addr, trans_len - 1, _id=trans_id)
u.s.ar._ag.data.append(trans)
t = ceil((len(id_addr_tuples) * trans_len + 10) * time_multiplier * CLK_PERIOD )
if randomize:
self.randomize_all()
t *= 3
self.runSim(t)
ref_data = sorted(flatten([
[(_id, addr + i + REF_DATA, RESP_OKAY, int(i == trans_len - 1))
for i in range(trans_len)]
for _id, addr in id_addr_tuples],
level=1))
data = sorted(allValuesToInts(u.s.r._ag.data))
# print("")
# print(ref_data)
# print(data)
self.assertSequenceEqual(data, ref_data)
def __repr__(self, scale=1):
buff = []
s = f"<{self.__class__.__name__:s} start:{self.startBitAddr:d}, end:{self.endBitAddr:d}"
buff.append(s)
padding = 5
DW = self.wordWidth
width = int(DW * scale)
buff.append(
'{0: <{padding}}{1: <{halfLineWidth}}{2: >{halfLineWidth}}'.format(
"", DW - 1, 0, padding=padding, halfLineWidth=width // 2))
line = '{0: <{padding}}{1:-<{lineWidth}}'.format(
"", "", padding=padding, lineWidth=width + 1)
buff.append(line)
for w, transParts in self.walkWords(showPadding=True):
wStr, partsWithChoice = self.__repr__word(
w, width, padding, transParts)
buff.append(wStr)
while partsWithChoice:
for parts in zip_longest(*partsWithChoice):
parts = list(flatten(parts, level=1))
wStr, _partsWithChoice = self.__repr__word(
w, width, padding, parts)
buff.append(wStr)
partsWithChoice = _partsWithChoice
buff.append(line)
buff.append(">")
return "\n".join(buff)
def _declr(self):
self._compute_constants()
addClkRstn(self)
# used to initialize the LRU data (in the case of cache reset)
# while set port is active all other ports are blocked
s = self.set = AddrDataHs()
s.ADDR_WIDTH = self.INDEX_W
s.DATA_WIDTH = self.LRU_WIDTH
# used to increment the LRU data in the case of hit
self.incr = HObjList(IndexWayHs() for _ in range(self.INCR_PORT_CNT))
for i in self.incr:
i.INDEX_WIDTH = self.INDEX_W
i.WAY_CNT = self.WAY_CNT
# get a victim for a selected cacheline index
# The cacheline returned as a victim is also marked as used just now
vr = self.victim_req = AddrHs()
vr.ADDR_WIDTH = self.INDEX_W
vr.ID_WIDTH = 0
vd = self.victim_data = Handshaked()._m()
vd.DATA_WIDTH = log2ceil(self.WAY_CNT - 1)
m = self.lru_mem = RamXorSingleClock()
m.ADDR_WIDTH = self.INDEX_W
m.DATA_WIDTH = self.LRU_WIDTH
m.PORT_CNT = (
# victim_req preload, victim_req write back or set,
READ, WRITE,
# incr preload, incr write back...
*flatten((READ, WRITE) for _ in range(self.INCR_PORT_CNT))
)
def test_write(self):
u = self.mySetUp(32)
MAGIC = 100
MAGIC2 = 300
m = mask(32 // 8)
N = 4
a = self.aTrans
u.bus.aw._ag.data.extend([a(i * 0x4) for i in range(N * 2 + 1)])
expected = [
[(MAGIC + i + 1, m) for i in range(N)],
[(MAGIC2 + i + 1, m) for i in range(N)]
]
u.bus.w._ag.data.extend(flatten(zip(expected[0], expected[1]), level=1))
u.bus.w._ag.data.append((123, m))
self.randomizeAll()
self.runSim(800 * Time.ns)
for i, a in enumerate(u.decoded.arr):
# [index of field][index in arr][data index]
self.assertValSequenceEqual(a.field0._ag.dout, [expected[0][i][0]])
self.assertValSequenceEqual(a.field1._ag.dout, [expected[1][i][0]])
self.assertValSequenceEqual(u.bus.b._ag.data,
[RESP_OKAY for _ in range(2 * N)] + [RESP_SLVERR])
def _register_stements(self, statements: List["HdlStatement"],
target: List["HdlStatement"]):
"""
Append statements to this container
"""
for stm in flatten(statements):
assert stm.parentStm is None, (
"HdlStatement instance has to have only a single parent", stm)
stm._set_parent_stm(self)
target.append(stm)
def _appendStatements(self, condSet, statements):
"""
Append statements to this container under conditions specified by condSet
"""
for stm in flatten(statements):
stm.isEventDependent = stm.isEventDependent or self.nowIsEventDependent
for c in condSet:
c.endpoints.append(stm)
stm.cond.update(condSet)
self.append(stm)
def _register_stements(self, statements: List["HdlStatement"],
target: List["HdlStatement"]):
"""
Append statements to this container under conditions specified
by condSet
"""
for stm in flatten(statements):
assert stm.parentStm is None, stm
stm._set_parent_stm(self)
target.append(stm)
def test_read(self):
u = self.mySetUp(32)
MAGIC = 100
MAGIC2 = 300
a = self.aTrans
u.bus.ar._ag.data.extend([a(i * 0x4) for i in range(4 * 2 + 1)])
for i, a in enumerate(u.decoded.arr):
a.field0._ag.din.extend([MAGIC + i])
a.field1._ag.din.extend([MAGIC2 + i])
self.randomizeAll()
self.runSim(500 * Time.ns)
expected = list(flatten([[(MAGIC + i, RESP_OKAY), (MAGIC2 + i, RESP_OKAY)]
for i in range(4)], level=1)
) + [(None, RESP_SLVERR)]
self.assertValSequenceEqual(u.bus.r._ag.data, expected)
def getMonitors(self):
return list(
flatten((i._ag.getMonitors() if i._direction
== INTF_DIRECTION.MASTER else i._ag.getDrivers()
for i in self.intf._interfaces),
level=1))