def strStructureCmp(self, cont, tmpl):
if not isinstance(cont, str):
cont = VhdlSerializer.asHdl(cont, VhdlSerializer.getBaseContext())
_tmpl = rmWhitespaces.sub(" ", tmpl).strip()
_cont = rmWhitespaces.sub(" ", cont).strip()
self.assertEqual(_tmpl, _cont)
def strStructureCmp(self, cont, tmpl):
if not isinstance(cont, str):
cont = VhdlSerializer.asHdl(cont, VhdlSerializer.getBaseContext())
_tmpl = rmWhitespaces.sub(" ", tmpl).strip()
_cont = rmWhitespaces.sub(" ", cont).strip()
self.assertEqual(_tmpl, _cont)
def netlistToVhdlStr(name, netlist, interfaces):
for s in interfaces:
s._interface = True
ctx = VhdlSerializer.getBaseContext()
return "\n".join([VhdlSerializer.asHdl(o, ctx)
for o in netlist.synthesize(name, interfaces, DummyPlatform())
])
def netlistToVhdlStr(name, netlist, interfaces):
for s in interfaces:
s._interface = True
ctx = VhdlSerializer.getBaseContext()
return "\n".join([
VhdlSerializer.asHdl(o, ctx)
for o in netlist.synthesize(name, interfaces, DummyPlatform())
])
def __repr__(self):
from hwt.serializer.vhdl.serializer import VhdlSerializer, onlyPrintDefaultValues
c = self.constrain
if isinstance(c, int):
constr = "width:%d" % c
elif isinstance(c, Unconstrained):
try:
constr = "derivedWidth:%d" % (c.derivedWidth)
except AttributeError:
constr = ""
else:
constr = VhdlSerializer.asHdl(self.constrain, onlyPrintDefaultValues) +\
(", %dbits" % self.bit_length())
return "<HdlType %s, %s>" % (self.__class__.__name__, constr)
def __repr__(self, indent=0, withAddr=None, expandStructs=False):
"""
:param indent: number of indentation
:param withAddr: if is not None is used as a additional
information about on which address this type is stored
(used only by HStruct)
:param expandStructs: expand HStructTypes (used by HStruct and HArray)
"""
c = self.width
if isinstance(c, int):
constr = "%dbits" % c
else:
from hwt.serializer.vhdl.serializer import VhdlSerializer
ctx = VhdlSerializer.getBaseContext()
constr = VhdlSerializer.asHdl(self.width, ctx)
constr = "%s, %dbits" % (constr, self.bit_length())
if self.signed:
constr += ", signed"
elif self.signed is False:
constr += ", unsigned"
return "%s<%s, %s>" % (getIndent(indent), self.__class__.__name__,
constr)
def assertStrEq(self, first, second, msg=None):
ctx = VhdlSerializer.getBaseContext()
first = VhdlSerializer.asHdl(first, ctx).replace(" ", "")
unittest.TestCase.assertEqual(self, first, second, msg=msg)
def assertStrEq(self, first, second, msg=None):
ctx = VhdlSerializer.getBaseContext()
first = VhdlSerializer.asHdl(first, ctx).replace(" ", "")
unittest.TestCase.assertEqual(self, first, second, msg=msg)
def SignalItem(si, declaration=False):
assert (declaration == False)
if si.hidden:
return VhdlSerializer.asHdl(si.origin)
else:
return "spirit:decode(id('MODELPARAM_VALUE.%s'))" % (si.name)