def _config(self): self.SPI_FREQ_PESCALER = Param(32) self.SS_WAIT_CLK_TICKS = Param(4) self.HAS_TX = Param(True) self.HAS_RX = Param(True) self.SPI_DATA_WIDTH = Param(1) Spi._config(self)
def _copyParamsAndInterfaces(self): for p in self._baseUnit._params: myP = Param(p.get_value()) self._registerParameter(p._name, myP) myP.set_value(p.get_value()) origToWrapInfMap = {} for intf in self.baseUnit._interfaces: # clone interface myIntf = intf.__copy__() # sub-interfaces are not instantiated yet # myIntf._direction = intf._direction myIntf._direction = INTF_DIRECTION.opposite(intf._direction) self._registerInterface(intf._name, myIntf) object.__setattr__(self, intf._name, myIntf) origToWrapInfMap[intf] = myIntf ei = self._ctx.interfaces for i in self._interfaces: self._loadInterface(i, True) assert i._isExtern i._signalsForInterface(self._ctx, ei, self._store_manager.name_scope, reverse_dir=True) return origToWrapInfMap
def _config(self): self.LCD_ROWS = Param(2) self.LCD_COLS = Param(16) self.LCD_DATA_WIDTH = Param(8) self.LCD_FREQ = Param(int(270e3)) # frequency of this component to compute timing for LCD control self.FREQ = Param(int(100e6))
def _config(self): self.intfCls._config(self) self.S_ADDR_STEP = Param(64) self.S_ADDR_WIDTH = Param(self.ADDR_WIDTH) self.S_DATA_WIDTH = Param(self.DATA_WIDTH) self.M_ADDR_OFFSET = Param(0) self.MAX_TRANS_OVERLAP = Param(64)
def _config(self): AxiSCompBase._config(self) self.USE_STRB = True self.T = Param(self._structT) self.TRANSACTION_TEMPLATE = Param(self._tmpl) self.FRAME_TEMPLATES = Param( None if self._frames is None else tuple(self._frames))
def _config(self) -> None: AvalonMM._config(self) self.MAX_BURST = 512 self.ID_WIDTH = Param(4) self.RW_PRIORITY = Param(READ) self.R_DATA_FIFO_DEPTH = Param(16) self.R_SIZE_FIFO_DEPTH = Param(16)
def paramToIpValue(self, idPrefix: str, g: Param, resolve) -> Value: val = Value() val.id = idPrefix + g.hdl_name val.resolve = resolve v = g.get_hdl_value() t = v._dtype def getVal(): if v.vld_mask: return v.val else: return 0 def bitString(w): val.format = "bitString" digits = math.ceil(w / 4) val.text = ('0x%0' + str(digits) + 'X') % getVal() val.bitStringLength = str(w) if t == BOOL: val.format = "bool" val.text = str(bool(getVal())).lower() elif t == INT: val.format = "long" val.text = str(getVal()) elif t == STR: val.format = "string" val.text = str(g.get_value()) elif isinstance(t, Bits): bitString(v._dtype.bit_length()) else: raise NotImplementedError( "Not implemented for datatype %s" % repr(t)) return val
def _config(self): self.INTF_CLS = Param(self.intfCls) self.intfCls._config(self) self.DATA_RESET_VAL = Param(None) self.IN_FREQ = Param(int(100e6)) self.OUT_FREQ = Param(int(100e6)) self.IGNORE_DATA_LOSE = Param(False)
def _config(self): self.PORT_CNT = Param(2) self.UPDATE_PORT_CNT = Param(1) self.ID_WIDTH = Param(4) AxiCacheTagArrayUpdateIntf._config(self) CacheAddrTypeConfig._config(self) self.LOOKUP_LATENCY = 1 self.MAX_BLOCK_DATA_WIDTH = Param(None)
def _config(self): AddrSizeHs._config(self) self.ID = Param(3) self.MAX_LEN = 15 self.ITEM_WIDTH = Param(16) self.BUFF_DEPTH = Param(16) self.TIMEOUT = Param(1024) self.ITEMS = Param(4096 // 8)
def _config(self): self.IS_BIGENDIAN = Param(False) self.USE_STRB = Param(False) self.USE_KEEP = Param(False) Axi_id._config(self) self.DEST_WIDTH = Param(0) self.DATA_WIDTH = Param(64) Axi_user._config(self)
def _config(self): self.intfCls._config(self) # if this is true field interfaces will be of type VldSynced # and single ready signal will be used for all # else every interface will be instance of Handshaked and it will # have it's own ready(rd) signal self.SHARED_READY = Param(False) # synchronize by last from input axi stream # or use internal counter for synchronization self.SYNCHRONIZE_BY_LAST = Param(True)
def _config(self): self.T = Param(HStruct( (HStream(Bits(8), frame_len=(1, inf), start_offsets=[0]), "f0"), (HStream(Bits(16), frame_len=(1, 1)), "f1"), )) AxiStream._config(self) self.DATA_WIDTH = 16 self.USE_KEEP = True self.OUT_OFFSET = Param(0)
def _config(self): self.ADDR_WIDTH = Param(32) self.DATA_WIDTH = Param(32) self.CNTRL_AW = Param(5) # size of data which should be transfered in worlds self.DATA_LEN = Param(33) self.MAX_BUTST_LEN = Param(16) self.REGISTER_MAP = HStruct((uint32_t, "control"), (uint32_t, "baseAddr"))
def _config(self): # number of items in main array is resolved from ADDR_WIDTH and size of STATE_T # number of concurent thread is resolved as 2**ID_WIDTH self.MAIN_STATE_T = Param(uint32_t) self.TRANSACTION_STATE_T = Param(uint8_t) self.PIPELINE_CONFIG = Param( OutOfOrderCummulativeOpPipelineConfig.new_config( WRITE_HISTORY_SIZE=4 + 1) ) Axi4._config(self)
def _config(self): self.PARAM_0 = Param(0) self.PARAM_10 = Param(10) try: self.PARAM_1_sll_512 = Param(1 << 512) raise AssertionError( "Parameter with int value which is" "too big to fit in integer type of target hdl language") except TypeError: # portable type for large int, generally int in verilog/vhdl is 32b wide self.PARAM_1_sll_512 = Param(vec(1 << 512, width=512 + 1))
def _config(self): self.DATA_WIDTH = Param(8) self.FORMAT = Param( ("AxiS_strFormat" ": hex: 0x", AxiS_strFormatItem(TypePath("data"), 'x', 32 // 4), ", dec: ", AxiS_strFormatItem(TypePath("data"), 'd', BinToBcd.decadic_deciamls_for_bin(32)), " is the value of data from example")) self.INPUT_T = Param(HStruct((uint32_t, "data"), )) self.ENCODING = Param("utf-8")
def test_BitsIndexTypes(self): t = Bits(8) v = t.fromPy(1) with self.assertRaises(TypeError): v[object()] with self.assertRaises(IndexError): v[9:] with self.assertRaises(IndexError): v[:-1] p = Param(2) self.assertIsInstance(v[p], RtlSignalBase) self.assertEqual(v[p]._dtype.bit_length(), 1) p2 = p._downto(0) self.assertIsInstance(v[p2], RtlSignalBase) self.assertEqual(v[p2]._dtype.bit_length(), 2) p3 = Param("abc") with self.assertRaises(TypeError): v[p3] a = RtlSignal(None, "a", BIT) a._const = False with self.assertRaises(TypeError): v[p] = a with self.assertRaises(TypeError): v[a] = p v[p] = 1 self.assertEqual(v, 5) v[p2] = 2 self.assertEqual(v, 6) with self.assertRaises(TypeError): v[hInt(None)] = 2 v[:] = 0 self.assertEqual(v, 0) v[2] = 1 self.assertEqual(v, 4) v[3:] = p self.assertEqual(v, 2) v._setitem__val(hInt(None), hInt(1)) with self.assertRaises(ValueError): int(v) with self.assertRaises(TypeError): v[hStr("asfs")]
def _config(self): self.intfCls._config(self) self.T = Param(self._structT) self.TRANSACTION_TEMPLATE = Param(self._tmpl) self.FRAME_TEMPLATES = Param(None if self._frames is None else tuple(self._frames)) # if this is true field interfaces will be of type VldSynced # and single ready signal will be used for all # else every interface will be instance of Handshaked and it will # have it's own ready(rd) signal self.SHARED_READY = Param(False) # if true, a new state for overflow will be created in FSM self.OVERFLOW_SUPPORT = Param(False)
def _config(self): self.PARAM_0 = Param(0) self.PARAM_10 = Param(10) try: self.PARAM_1_sll_512 = Param(INT.from_py(1 << 512)) raise AssertionError( "Parameter with int value which is" "too big to fit in integer type of target hdl language") except ValueError: # portable type for large int, generally int in verilog/vhdl is 32b wide self.PARAM_1_sll_512 = Param(Bits(512 + 1).from_py(1 << 512)) self.PARAM_1_sll_512_py_int = Param(1 << 512)
def _config(self): self.MAX_TRANS_OVERLAP = Param(16) self.MAX_LEN = Param(4096 // 8 - 1) self.ID_WIDTH = Param(4) self.ADDR_WIDTH = Param(32) self.USER_WIDTH = Param(0) self.DATA_WIDTH = Param(64) self.CACHE_VAL = Param(CACHE_DEFAULT) self.PROT_VAL = Param(PROT_DEFAULT) self.QOS_VAL = Param(QOS_DEFAULT) self.USE_STRB = Param(True)
def _registerParameter(self, pName, parameter: Param) -> None: """ Register Param object on interface level object """ nameAvailabilityCheck(self, pName, parameter) # resolve name in this scope assert parameter._name is None, ( "Param object is already assigned to %r.%s" % (parameter.unit, parameter._name)) # add name in this scope parameter._name = pName parameter._parent = self self._params.append(parameter)
def addP(n: str, p: Param): if n in params: raise IntfLvlConfErr( "Redefinition of generic/param '%s' while synthesis" " old:%r, new:%r" % (n, params[n], p)) p.hdl_name = n params[n] = p
def test_BitsConcatIncompatibleType(self): t = Bits(1) v = t.fromPy(1) with self.assertRaises(TypeError): v._concat(hInt(2)) p = Param(1) with self.assertRaises(TypeError): v._concat(p)
def GenericItem(cls, g: Param, ctx): v = g.get_hdl_value() if v._dtype == STR or v._dtype == INT or v._dtype == BOOL: t_str = "" else: t_str = cls.HdlType(v._dtype, ctx.forPort()) + " " v_str = cls.Value(v, ctx) return 'parameter %s %s= %s' % ( g.hdl_name, t_str, v_str)
def _config(self): self.ITEMS = Param(32) self.ITEM_WIDTH = Param(32) self.ID = Param(0) self.ID_WIDTH = Param(4) self.DATA_WIDTH = Param(64) self.ADDR_WIDTH = Param(32) self.MAX_TRANS_OVERLAP = Param(16)
def _config(self): self.TABLE_SIZE = Param(32) self.DATA_WIDTH = Param(32) self.KEY_WIDTH = Param(8) self.LOOKUP_KEY = Param(False) self.TABLE_CNT = Param(2) self.MAX_LOOKUP_OVERLAP = Param(16) self.MAX_REINSERT = Param(15)
def _config(self): self.ID_WIDTH = Param(4) self.ID = Param(3) # id of packet where last item is next addr self.ID_LAST = Param(4) self.BUFFER_CAPACITY = Param(32) self.ITEMS_IN_BLOCK = Param(4096 // 8 - 1) self.ADDR_WIDTH = Param(32) self.DATA_WIDTH = Param(64) self.PTR_WIDTH = Param(16)
def _config(self): self.ITEMS_CNT = Param(32) self.KEY_WIDTH = Param(16) self.DATA_WIDTH = Param(8) self.LOOKUP_ID_WIDTH = Param(0) self.LOOKUP_HASH = Param(False) self.LOOKUP_KEY = Param(False)
def _config(self): self.HASH_WIDTH = Param(8) self.KEY_WIDTH = Param(8) self.DATA_WIDTH = Param(0) self.LOOKUP_ID_WIDTH = Param(0) self.LOOKUP_HASH = Param(False) self.LOOKUP_KEY = Param(False)
def _config(self): self.DATA_WIDTH = Param(8) self.INIT = Param(0) self.IN_IS_BIGENDIAN = Param(False) self.POLY = Param(CRC_5_USB.POLY) self.POLY_WIDTH = Param(CRC_5_USB.WIDTH) self.REFIN = Param(False) self.REFOUT = Param(False) self.XOROUT = Param(0)
class CrcComb(Unit): """ CRC generator, polynomial can be string in usual format or integer ("x^3+x+1" or 0b1011) :ivar DATA_WIDTH: width of data in signal :ivar POLY: specified CRC polynome, str, int or Bits value :ivar POLY_WIDTH: width of POLY :ivar REFIN: This is a boolean parameter. If it is FALSE, input bytes are processed with bit 7 being treated as the most significant bit (MSB) and bit 0 being treated as the least significant bit. If this parameter is FALSE, each byte is reflected before being processed. :ivar REFOUT: Same as REFIN except for output :ivar XOROUT: value to xor result with .. hwt-schematic:: """ def _config(self): self.DATA_WIDTH = Param(8) self.INIT = Param(0) self.IN_IS_BIGENDIAN = Param(False) self.POLY = Param(CRC_5_USB.POLY) self.POLY_WIDTH = Param(CRC_5_USB.WIDTH) self.REFIN = Param(False) self.REFOUT = Param(False) self.XOROUT = Param(0) def setConfig(self, crcConfigCls): """ Apply configuration from CRC configuration class """ self.POLY.set(vec(crcConfigCls.POLY, crcConfigCls.WIDTH)) self.POLY_WIDTH.set(crcConfigCls.WIDTH) self.REFIN.set(crcConfigCls.REFIN) self.REFOUT.set(crcConfigCls.REFOUT) self.XOROUT.set(vec(crcConfigCls.XOROUT, crcConfigCls.WIDTH)) self.INIT.set(vec(crcConfigCls.INIT, crcConfigCls.WIDTH)) def _declr(self): addClkRstn(self) with self._paramsShared(): self.dataIn = VectSignal(self.DATA_WIDTH) self.dataOut = VectSignal(self.POLY_WIDTH)._m() @staticmethod def parsePoly(POLY, POLY_WIDTH) -> List[int]: """ :return: list of bits from polynome, extra MSB 1 is added len of this list is POLY_WIDTH + 1 """ PW = int(POLY_WIDTH) poly = int(POLY) # [TODO] poly in str if isinstance(poly, str): polyCoefs = parsePolyStr(poly, PW) elif isinstance(poly, int): polyCoefs = [selectBit(poly, i) for i in range(PW)] else: raise NotImplementedError() # LSB is usuaaly 1 return polyCoefs, PW # based on # hhttps://github.com/alexforencich/fpga-utils/blob/master/crcgen.py @staticmethod def buildCrcXorMatrix(data_width: int, polyBits: List[bool]) -> List[Tuple[List[bool], List[bool]]]: """ :param data_width: number of bits in input (excluding bits of signal wit current crc state) :param polyBits: list of bits in specified polynome :note: all bits are in format LSB downto MSB :return: crc_mask contains rows where each row describes which bits should be XORed to get bit of resut row is [mask_for_state_reg, mask_for_data] """ DW = data_width PW = len(polyBits) # list index is output bit index # initial state is 1:1 mapping from previous state to next state crc_mask = deque([ [[int(x == y) for y in range(PW)], [0] * DW] for x in range(PW) ]) for i in range(DW - 1, -1, -1): # determine shift in value # current value in last FF, XOR with input data bit (MSB first) val = crc_mask[-1] val[1][i] = int(not val[1][i]) # shift crc_mask.appendleft(val) crc_mask.pop() # add XOR inputs at correct indicies first = True val_s, val_d = val for cm, pb in zip(crc_mask, polyBits): if first: first = False elif pb: cm[0] = [a ^ b for a, b in zip(cm[0], val_s)] cm[1] = [a ^ b for a, b in zip(cm[1], val_d)] return crc_mask @classmethod def applyCrcXorMatrix(cls, crcMatrix: List, inBits: List, stateBits: List, refin: bool) -> List: if refin: inBits = reversedBitsInBytes(inBits) #stateBits = list(reversed(stateBits)) outBits = [] for (stateMask, dataMask) in crcMatrix: v = hBit(0) # neutral value for XOR assert len(stateMask) == len(stateBits) for useBit, b in zip(stateMask, stateBits): if useBit: v = v ^ b assert len(dataMask) == len(inBits), (len(dataMask), len(inBits)) for useBit, b in zip(dataMask, inBits): if useBit: v = v ^ b outBits.append(v) assert len(outBits) == len(stateBits) return outBits def _impl(self): DW = int(self.DATA_WIDTH) polyBits, PW = self.parsePoly(self.POLY, self.POLY_WIDTH) # xorMatrix = buildCrcMatrix_dataMatrix(polyCoefs, PW, DW) # initXorMatrix = buildCrcMatrix_reg0Matrix(polyCoefs, PW, DW) XOROUT = int(self.XOROUT) _INIT = int(self.INIT) initBits = [hBit(selectBit(_INIT, i)) for i in range(PW)] finBits = [hBit(selectBit(XOROUT, i)) for i in range(PW)] # rename to have shorter code _inD = self._sig("d", self.dataIn._dtype) _inD(self.dataIn) inBits = list(iterBits(_inD)) if not self.IN_IS_BIGENDIAN: inBits = reversedEndianity(inBits) outBits = iterBits(self.dataOut) crcMatrix = self.buildCrcXorMatrix(DW, polyBits) res = self.applyCrcXorMatrix( crcMatrix, inBits, initBits, bool(self.REFIN)) if self.REFOUT: res = list(reversed(res)) finBits = reversedBitsInBytes(finBits) for ob, b, fb in zip(outBits, res, finBits): ob(b ^ fb)