def main():
import unittest
from hwt.synthesizer.utils import to_rtl_str
u = ConstCondition()
print(to_rtl_str(u))
suite = unittest.TestSuite()
suite.addTest(unittest.makeSuite(ConstConditionTC))
runner = unittest.TextTestRunner(verbosity=3)
runner.run(suite)
def test_SubunitWithWrongDataT(self):
class InternUnit(Unit):
def _declr(self):
dt = Bits(64)
self.a = Signal(dtype=dt)
self.b = Signal(dtype=dt)._m()
def _impl(self):
self.b(self.a)
class OuterUnit(Unit):
def _declr(self):
dt = Bits(32)
self.a = Signal(dtype=dt)
self.b = Signal(dtype=dt)
self.iu = InternUnit()
def _impl(self):
self.iu.a(self.a)
self.b(self.iu.b)
self.assertRaises(TypeConversionErr, lambda: to_rtl_str(OuterUnit))
propagateClk(self)
PORT_CNT = self.PORT_CNT
fa = self.firstA
sa = self.secondA
If(self.select_sig,
self.ram0.port[0](fa),
self.ram1.port[0](sa)
).Else(
self.ram0.port[0](sa),
self.ram1.port[0](fa)
)
if PORT_CNT == 2:
fb = self.firstB
sb = self.secondB
If(self.select_sig,
self.ram0.port[1](fb),
self.ram1.port[1](sb),
).Else(
self.ram0.port[1](sb),
self.ram1.port[1](fb)
)
elif PORT_CNT > 2:
raise NotImplementedError()
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
print(to_rtl_str(FlipRam()))
).Else(data_out(Concat(BIT.from_py(0), half_count)))
def _impl(self):
raise NotImplementedError(
"This is an abstract method and should be overriden")
class CountLeadingZeros(_CountLeading):
"""
Count leading zeros in bit vector
.. hwt-autodoc::
"""
def _impl(self):
self.count_leading(self.data_in, self.data_out, 0)
class CountLeadingOnes(_CountLeading):
"""
Count leading zeros in bit vector
.. hwt-autodoc::
"""
def _impl(self):
self.count_leading(self.data_in, self.data_out, 1)
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
print(to_rtl_str(CountLeadingZeros()))
fRam[r1](a, fit=True),
self.k(fRam[r1]._unsigned(), fit=True)
)
if __name__ == "__main__": # alias python main function
from pprint import pprint
from hwt.synthesizer.utils import to_rtl_str
from hwt.serializer.hwt import HwtSerializer
from hwt.serializer.vhdl import Vhdl2008Serializer
from hwt.serializer.verilog import VerilogSerializer
from hwt.serializer.systemC import SystemCSerializer
from hwt.serializer.resourceAnalyzer.analyzer import ResourceAnalyzer
from hwt.synthesizer.utils import synthesised
# * new instance has to be created every time because to_rtl_str modifies the unit
# * serializers are using templates which can be customized
# serialized code is trying to be human and git friendly
print(to_rtl_str(Showcase0(), serializer_cls=HwtSerializer))
print(to_rtl_str(Showcase0(), serializer_cls=Vhdl2008Serializer))
print(to_rtl_str(Showcase0(), serializer_cls=VerilogSerializer))
print(to_rtl_str(Showcase0(), serializer_cls=SystemCSerializer))
u = Showcase0()
ra = ResourceAnalyzer()
synthesised(u)
ra.visit_Unit(u)
pprint(ra.report())
def test_regWhereNextIsOnlyOutput(self):
u = RegWhereNextIsOnlyOutput()
with self.assertRaises(SignalDriverErr):
to_rtl_str(u)
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
from hwt.interfaces.std import Signal
from hwt.synthesizer.unit import Unit
class ConstDriverUnit(Unit):
"""
.. hwt-autodoc::
"""
def _declr(self):
self.out0 = Signal()._m()
self.out1 = Signal()._m()
def _impl(self):
self.out0(0)
self.out1(1)
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
print(to_rtl_str(ConstDriverUnit()))
from hwt.interfaces.utils import addClkRst
from hwt.synthesizer.param import Param
from hwt.synthesizer.unit import Unit
class Cntr(Unit):
"""
.. hwt-autodoc::
"""
def _config(self):
self.DATA_WIDTH = Param(2)
def _declr(self):
addClkRst(self)
self.en = Signal()
self.val = VectSignal(self.DATA_WIDTH)._m()
def _impl(self):
reg = self._reg("counter", Bits(self.DATA_WIDTH), 0)
# if there is no assignment into reg, value is kept
If(self.en, reg(reg + 1))
self.val(reg)
if __name__ == "__main__": # "python main function"
from hwt.synthesizer.utils import to_rtl_str
# there is more of synthesis methods. to_rtl_str() returns formated vhdl string
print(to_rtl_str(Cntr()))
def test_invalidTypeConnetion(self):
u = InvalidTypeConnetion()
with self.assertRaises(TypeConversionErr):
to_rtl_str(u)
propagateClkRstn(self)
u = self.subunit0
u.a(self.a0)
self.b0(u.b)
class SimpleSubunit2TC(SimTestCase):
@classmethod
def setUpClass(cls):
cls.u = SimpleSubunit2()
cls.compileSim(cls.u)
def test_simplePass(self):
u = self.u
data = [(5, 1, 0), (6, 1, 1)]
u.a0._ag.data.extend(data)
self.runSim(50 * Time.ns)
self.assertEmpty(u.a0._ag.data)
self.assertValSequenceEqual(u.b0._ag.data, data)
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
print(to_rtl_str(SimpleSubunit2()))
import unittest
suite = unittest.TestSuite()
suite.addTest(unittest.makeSuite(SimpleSubunit2TC))
runner = unittest.TextTestRunner(verbosity=3)
runner.run(suite)
# SimTestCase is unittest.TestCase with some extra methods
class HandshakedBuilderSimpleTC(SimTestCase):
@classmethod
def setUpClass(cls):
# SimTestCase.setUpClass calls this method
# and will build a simulator of this component
cls.u = HandshakedBuilderSimple()
cls.compileSim(cls.u)
def test_passData(self):
# now in setUpClass call the simulator was build
# in setU call the simulator was initialized
# and signals in .u are replaced
# with proxies for simulator
u = self.u
# add data on input of agent for "a" interface
u.a._ag.data.extend([1, 2, 3, 4])
self.runSim(200 * Time.ns)
# check if data was recieved on "b" interface
self.assertValSequenceEqual(u.b._ag.data, [1, 2, 3, 4])
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
print(to_rtl_str(HandshakedBuilderSimple()))
eq(b_arr.f2._ag.dout, _f2_out, (i, i2))
emp(b_arr.f2._ag.din, (i, i2))
dinEq(a_arr.f2, _f2_in, (i, i2))
def test_ListOfInterfacesSample4b(self):
u = ListOfInterfacesSample4b()
self._test(u)
def test_ListOfInterfacesSample4c(self):
u = ListOfInterfacesSample4c()
self._test(u)
def test_ListOfInterfacesSample4d(self):
u = ListOfInterfacesSample4d()
self._test(u)
if __name__ == "__main__":
import unittest
suite = unittest.TestSuite()
# suite.addTest(ListOfInterfacesSample4TC('test_ListOfInterfacesSample4b_intfIterations'))
# suite.addTest(ListOfInterfacesSample4TC('test_ListOfInterfacesSample4b'))
suite.addTest(unittest.makeSuite(ListOfInterfacesSample4TC))
runner = unittest.TextTestRunner(verbosity=3)
runner.run(suite)
from hwt.synthesizer.utils import to_rtl_str
print(to_rtl_str(ListOfInterfacesSample4c()))
def set_data(self, intf, d):
return [
intf.data(d),
]
def _impl(self):
self.DATA_WIDTH = int(self.DATA_WIDTH)
dout = self.dataOut
DATA_LEN = len(self.DATA)
wordIndex_w = int(math.log2(DATA_LEN) + 1)
wordIndex = self._reg("wordIndex", Bits(wordIndex_w), def_val=0)
def set_data(d):
return self.set_data(dout, d)
Switch(wordIndex)\
.add_cases([(i, set_data(d))
for i, d in enumerate(self.DATA)])\
.Default(*set_data(None))
If(wordIndex < DATA_LEN, dout.vld(1)).Else(dout.vld(0))
If(self.dataRd(), self.nextWordIndexLogic(wordIndex))
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
print(to_rtl_str(HandshakedStoredBurst()))
self.clkOut(
(r_cnt != CNTR_MAX) & (f_cnt != CNTR_MAX)) # fall._eq(rise)
class ClkDiv3TC(SimTestCase):
@classmethod
def setUpClass(cls):
cls.u = ClkDiv3()
cls.compileSim(cls.u)
def test_oscilation(self):
self.runSim(10 * 10 * Time.ns)
expected = [(0, 0), (20000.0, 1), (35000.0, 0), (50000.0, 1),
(65000.0, 0), (80000.0, 1), (95000.0, 0)]
self.assertValSequenceEqual(self.u.clkOut._ag.data, expected)
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
print(to_rtl_str(ClkDiv3()))
import unittest
suite = unittest.TestSuite()
# suite.addTest(ClkDiv3TC('test_oscilation'))
suite.addTest(unittest.makeSuite(ClkDiv3TC))
runner = unittest.TextTestRunner(verbosity=3)
runner.run(suite)
fa_list = self.fa = HObjList()
for a, b in zip(self.a, self.b):
# [note] componnets do not have to be declared in _declr(), but it is better
# because the configuration of component can be still modified
# after _declr() in _impl() the configuration of component is locked imediately after registration
fa = FullAdder()
# [note] the component have to be registered in order to spot the IO
# the registration is done by assining to a property ot his object e.g. self.fa0 = fa
# or by adding to some already registered object, in this case HObjList instance
fa_list.append(fa)
fa.a(a)
fa.b(b)
fa.ci(carry)
carry = fa.co
# [note] we have to reverse because of downto indexing
self.s(Concat(*reversed([fa.s for fa in fa_list])))
self.co(carry)
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
u1 = RippleAdder1()
u2 = RippleAdder2()
u3 = RippleAdder3()
from hwt.serializer.verilog import VerilogSerializer
print(to_rtl_str(u1, serializer_cls=VerilogSerializer))
print(to_rtl_str(u2, serializer_cls=VerilogSerializer))
print(to_rtl_str(u3, serializer_cls=VerilogSerializer))
# 1
0b1001111,
# 2
0b0010010,
# 3
0b0000110,
# 4
0b1001100,
# 5
0b0100100,
# 6
0b0100000,
# 7
0b0001111,
# 8
0b0000000,
# 9
0b0000100,
]
Switch(self.dataIn) \
.add_cases(enumerate([self.dataOut(v) for v in dec])) \
.Default(
# display off when value is out of range
self.dataOut(0b1111111)
)
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
print(to_rtl_str(Segment7()))
def test_CntrCombLoop(self):
u = CntrCombLoop()
with self.assertRaises(HwtSyntaxError):
to_rtl_str(u)
def test_inconsistentIntfDirection(self):
u = InconsistentIntfDirection()
with self.assertRaises(SignalDriverErr):
to_rtl_str(u)
.. hwt-autodoc::
"""
def _declr(self):
self.addr = VectSignal(2)
self.dout = VectSignal(8)._m()
def _impl(self):
rom = self._sig("rom_data", Bits(8)[4], def_val=[1, 2, 3, 4])
self.dout(rom[self.addr])
class SimpleSyncRom(SimpleRom):
"""
.. hwt-autodoc::
"""
def _declr(self):
super()._declr()
self.clk = Clk()
def _impl(self):
rom = self._sig("rom_data", Bits(8)[4], def_val=[1, 2, 3, 4])
If(self.clk._onRisingEdge(),
self.dout(rom[self.addr])
)
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
print(to_rtl_str(SimpleSyncRom()))
def test_multipleDriversOfChildNet(self):
u = MultipleDriversOfChildNet()
with self.assertRaises((SignalDriverErr, AssertionError)):
to_rtl_str(u)
if __name__ == "__main__": # alias python main function
# to_rtl_str can be imported anywhere but we prefer to import it only
# when this script is running as main
from hwt.synthesizer.utils import to_rtl_str
from hwt.serializer.vhdl import Vhdl2008Serializer
# there are other serializers ...
# from hwt.serializer.hwt import HwtSerializer
# from hwt.serializer.simModel import SimModelSerializer
# from hwt.serializer.verilog import VerilogSerializer
# we create instance of our unit
u = SimpleUnit()
# to_rtl_str() returns hdl string, you can also generate files with to_rtl, IP-xact packages with IpPackager
print(to_rtl_str(u, serializer_cls=Vhdl2008Serializer))
# expected Output (without # ofcourse)
# -- In order to create a new unit you have to make new class derived from Unit.
# --
# -- You can use sphinx-hwt plugin for sphinx document generator
# -- to generate interactive schematic and documentation.
# -- Schematic is generated by directive bellow.
# LIBRARY IEEE;
# USE IEEE.std_logic_1164.ALL;
# USE IEEE.numeric_std.ALL;
#
# ENTITY SimpleUnit IS
# PORT (a : IN STD_LOGIC;
# b : OUT STD_LOGIC
# );
def test_multipleDriversOfChildNet2(self):
u = MultipleDriversOfChildNet2()
with self.assertRaises(SignalDriverErr):
to_rtl_str(u)
def test_optimizedOutReg(self):
u = OptimizedOutReg()
self.assertNotIn("unconnected", to_rtl_str(u))
def test_unusedSubunit2(self):
u = UnusedSubunit2()
with self.assertRaises(SignalDriverErr):
to_rtl_str(u)
def test_accessingSubunitInternalIntf(self):
u = AccessingSubunitInternalIntf()
with self.assertRaises(AssertionError):
to_rtl_str(u)
u.CLKFBOUT_PHASE = 0.0
u.CLKFBOUT_USE_FINE_PS = False
u.CLKIN1_PERIOD = 10.0
u.CLKIN2_PERIOD = 0.0
u.CLKOUT0_DIVIDE_F = 10.0
u.CLKOUT0_DUTY_CYCLE = 0.5
u.CLKOUT0_PHASE = 0.0
u.CLKOUT0_USE_FINE_PS = False
for i in range(1, 6 + 1):
setattr(u, f"CLKOUT{i:d}_DIVIDE", 1)
setattr(u, f"CLKOUT{i:d}_DUTY_CYCLE", 0.5)
setattr(u, f"CLKOUT{i:d}_PHASE", 0.0)
setattr(u, f"CLKOUT{i:d}_USE_FINE_PS", False)
u.CLKOUT4_CASCADE = False
u.COMPENSATION = "ZHOLD"
u.DIVCLK_DIVIDE = 1
u.IS_CLKINSEL_INVERTED = BIT.from_py(0)
u.IS_PSEN_INVERTED = BIT.from_py(0)
u.IS_PSINCDEC_INVERTED = BIT.from_py(0)
u.IS_PWRDWN_INVERTED = BIT.from_py(0)
u.IS_RST_INVERTED = BIT.from_py(0)
u.REF_JITTER1 = 0.01
u.REF_JITTER2 = 0.01
u.SS_EN = "FALSE"
u.SS_MODE = "CENTER_HIGH"
u.SS_MOD_PERIOD = 10000
u.STARTUP_WAIT = "FALSE"
print(to_rtl_str(u, target_platform=XilinxVivadoPlatform()))
# -*- coding: utf-8 -*-
from hwt.synthesizer.interfaceLevel.emptyUnit import EmptyUnit
from hwt.synthesizer.utils import to_rtl_str
from hwtLib.examples.base_serialization_TC import BaseSerializationTC
from hwtLib.peripheral.spi.intf import Spi
class EmptyUnitWithSpi(EmptyUnit):
def _declr(self):
self.spi = Spi()
class EmptyUnitWithSpiTC(BaseSerializationTC):
__FILE__ = __file__
def test_vhdl(self):
self.assert_serializes_as_file(EmptyUnitWithSpi(),
"EmptyUnitWithSpi.vhd")
if __name__ == "__main__":
import unittest
suite = unittest.TestSuite()
# suite.addTest(TwoCntrsTC('test_withStops'))
suite.addTest(unittest.makeSuite(EmptyUnitWithSpiTC))
runner = unittest.TextTestRunner(verbosity=3)
runner.run(suite)
print(to_rtl_str(EmptyUnitWithSpi()))
"""
This is comment for SimpleComentedUnit entity, it will be rendered before entity as comment.
Do not forget that class inheritance does apply for docstring as well.
"""
def _declr(self):
self.a = Signal()
self.b = Signal()._m()
def _impl(self):
self.b(self.a)
class SimpleComentedUnit2(SimpleComentedUnit):
"""single line"""
pass
class SimpleComentedUnit3(SimpleComentedUnit2):
pass
SimpleComentedUnit3.__doc__ = "dynamically generated, for example loaded from file or builded from unit content"
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
print(to_rtl_str(SimpleComentedUnit))
print(to_rtl_str(SimpleComentedUnit2))
print(to_rtl_str(SimpleComentedUnit3))
# )
# t = HUnion(
# (HStruct(
# (uint64_t, "itemA0"),
# (uint64_t, "itemA1")
# ), "frameA"),
# (HStruct(
# (uint32_t, "itemB0"),
# (uint32_t, "itemB1"),
# (uint32_t, "itemB2"),
# (uint32_t, "itemB3")
# ), "frameB")
# )
t = HStruct(
(HStream(uint8_t), "frame0"),
(uint16_t, "footer")
)
u = AxiS_frameParser(t)
u.USE_STRB = True
u.DATA_WIDTH = 32
return u
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
u = _example_AxiS_frameParser()
print(to_rtl_str(u))
class SwitchStmUnit(Unit):
"""
Example which is using switch statement to create multiplexer
.. hwt-autodoc::
"""
def _declr(self):
self.sel = VectSignal(3)
self.out = Signal()._m()
self.a = Signal()
self.b = Signal()
self.c = Signal()
def _impl(self):
Switch(self.sel)\
.Case(0,
self.out(self.a)
).Case(1,
self.out(self.b)
).Case(2,
self.out(self.c)
).Default(
self.out(0)
)
if __name__ == "__main__":
from hwt.synthesizer.utils import to_rtl_str
print(to_rtl_str(SwitchStmUnit()))
